Transistors having buried p-type layers beneath the source region and methods of fabricating the same

Field of the Invention

0001The present invention relates to microelectronic devices and more particularly to transistors, for example, metal-semiconductor field-effect transistors (MESFETs).

Background of the Invention

0002Electrical circuits requiring high power handling capability (>20 watts) while operating at high frequencies such as radio frequencies (500 MHz), S-band (3 GHz) and X-band (10 GHz) have in recent years become more prevalent. Because of the increase in high power, high frequency circuits there has been a corresponding increase in demand for transistors that are capable of reliably operating at radio frequencies and above while still being capable of handling higher power loads. Previously, bipolar transistors and power metal-oxide semiconductor field effect transistors (MOSFETs) have been used for high power applications but the power handling capability of such devices may be limited at higher operating frequencies. Junction field-effect transistors (JFETs) were commonly used for high frequency applications but the power handling capability of previously known JFETs may also be limited.

0003Recently, metal-semiconductor field effect transistors (MESFETs) have been developed for high frequency applications. The MESFET construction may be preferable for high frequency applications because only majority carriers carry current. The MESFET design may be preferred over current MOSFET designs because the reduced gate capacitance permits faster switching times of the gate input. Therefore, although all field-effect transistors utilize only majority carriers to carry current, the Schottky gate structure of the MESFET may make the MESFET more desirable for high frequency applications.

0004In addition to the type of structure, and perhaps more fundamentally, the characteristics of the semiconductor material from which a transistor is formed also affects the operating parameters. Of the characteristics that affect a transistor's operating parameters, the electron mobility, saturated electron drift velocity, electric breakdown field and thermal conductivity may have the greatest effect on a transistor's high frequency and high power characteristics.

0005Electron mobility is the measurement of how rapidly an electron is accelerated to its saturated velocity in the presence of an electric field. In the past, semiconductor materials which have a high electron mobility were preferred because more current could be developed with a lesser field, resulting in faster response times when a field is applied. Saturated electron drift velocity is the maximum velocity that an electron can obtain in the semiconductor material. Materials with higher saturated electron drift velocities are preferred for high frequency applications because the higher velocity translates to shorter times from source to drain.

0006Electric breakdown field is the field strength at which breakdown of the Schottky junction and the current through the gate of the device suddenly increases. A high electric breakdown field material is preferred for high power, high frequency transistors because larger electric fields generally can be supported by a given dimension of material. Larger electric fields allow for faster transients as the electrons can be accelerated more quickly by larger electric fields than by smaller.

0007Thermal conductivity is the ability of the semiconductor material to dissipate heat. In typical operations, all transistors generate heat. In turn, high power and high frequency transistors usually generate larger amounts of heat than small signal transistors. As the temperature of the semiconductor material increases, the junction leakage currents generally increase and the current through the field effect transistor generally decreases due to a decrease in carrier mobility with an increase in temperature. Therefore, if the heat is dissipated from the semiconductor, the material will remain at a lower temperature and be capable of carrying larger currents with lower leakage currents.

0008In the past, high frequency MESFETs have been manufactured of n-type III-V compounds, such as gallium arsenide (GaAs) because of their high electron mobilities. Although these devices provided increased operating frequencies and moderately increased power handling capability, the relatively low breakdown voltage and the lower thermal conductivity of these materials have limited their usefulness in high power applications.

0009Silicon carbide (SiC) has been known for many years to have excellent physical and electronic properties which should theoretically allow production of electronic devices that can operate at higher temperatures, higher power and higher frequency than devices produced from silicon (Si) or GaAs. The high electric breakdown field of about 4 x 10⁶ V/cm, high saturated electron drift velocity of about 2.0 x10⁷ cm/sec and high thermal conductivity of about 4.9 W/cm-°K indicate that SiC would be suitable for high frequency, high power applications. Unfortunately, difficulty in manufacturing has limited the usefulness of SiC for high power and high frequency applications.

0010MESFETs have been produced having channel layers of silicon carbide have been produced on silicon substrates <i>(See, e.g.,</i> United States Patent Nos. <patcit id="pcit0001" dnum="US4762806A"><text>4,762,806 to Suzuki et al.</text></patcit> and <patcit id="pcit0002" dnum="US4757028A"><text>4,757,028 to Kondoh et al.</text></patcit>). Because the semiconductor layers of a MESFET are epitaxial, the layer upon which each epitaxial layer is grown affects the characteristics of the device. Thus, a SiC epitaxial layer grown on a Si substrate generally has different electrical and thermal characteristics then a SiC epitaxial layer grown on a different substrate. Although the SiC on Si substrate devices described in <patcit id="pcit0003" dnum="US4762806A"><text>U.S. Pat. Nos. 4,762,806</text></patcit> and <patcit id="pcit0004" dnum="US4757028A"><text>4,757,028</text></patcit> may have exhibited improved thermal characteristics, the use of a Si substrate generally limits the ability of such devices to dissipate heat. Furthermore, the growth of SiC on Si generally results in defects in the epitaxial layers that result in high leakage current when the device is in operation.

0011Other MESFETs have been developed using SiC substrates. <patcit id="pcit0005" dnum="US54048890A" dnum-type="L"><text>U.S. patent application Ser. No. 07/540,488 filed Jun. 19, 1990</text></patcit> and now abandoned, describes a SiC MESFET having epitaxial layers of SiC grown on a SiC substrate. These devices exhibited improved thermal characteristics over previous devices because of the improved crystal quality of the epitaxial layers grown on SiC substrates. However, to obtain high power and high frequency it may be necessary to overcome the limitations of SiC's lower electron mobility.

0012Similarly, commonly assigned United States Patent No. <patcit id="pcit0006" dnum="US5270554A"><text>5,270,554</text></patcit> to Palmour describes a SiC MESFET having source and drain contacts formed on n⁺ regions of SiC and an optional lightly doped epitaxial layer between the substrate and the n-type layer in which the channel is formed. United States Patent No. <patcit id="pcit0007" dnum="US5925895A"><text>5,925, 895 to Sriram et al.</text></patcit> also describes a SiC MESFET and a structure that is described as overcoming"surface effects"which may reduce the performance of the MESFET for high frequency operation. Sriram <i>et al.</i> also describes SiC MESFETs which use n source and drain contact regions as well as a p-type buffer layer.

0013Furthermore, conventional SiC FET structures may provide the constant characteristics during the entire operating range of the FET, <i>i.e.</i> from fully open channel to near pinch-off voltage, by using a very thin, highly doped channel (a delta doped channel) offset from the gate by a lightly doped region of similar conductivity type. Delta doped channels are discussed in detail in an article by <nplcit id="ncit0001" npl-type="s"><text>Yokogawa et al. entitled Electronic Properties of Nitrogen Delta-Doped Silicon Carbide Layers, MRS Fall Symposium, 2000</text></nplcit> and an article by <nplcit id="ncit0002" npl-type="s"><text>Konstantinov et al. entitled Investigation of Lo-Hi-Lo and Delta Doped Silicon Carbide Structure, MRS Fall Symposium, 2000</text></nplcit>. However, further improvements may be made in SiC MESFETs.

0014For example, it may be important that SiC MESFETs have high breakdown voltages and relatively low leakage currents if they are used in high efficiency, high power, high linearity radio frequency (RF) applications. In an attempt to provide high breakdown voltages, devices have been provided having highly compensated substrates, such as Vanadium doped semi-insulating SiC. These devices typically provide adequate breakdown voltages as well as low leakage currents, but may sacrifice device performance due to unwanted trapping effects in the substrate.

0015Furthermore, devices having highly doped p-type layers under the channel of the FET have been provided and have been successful in providing good electron confinement and low leakage currents. However, these devices generally contain excessive parasitics that may degrade the RF performance of the device. Accordingly, further improvements may be made with respect to existing SiC FET devices such that they may provide improved breakdown voltages without sacrificing other performance characteristics of the device.

0016European Patent Application <patcit id="pcit0008" dnum="EP0305975A2"><text>EP0305975A2</text></patcit> discloses a semiconductor device with a first semiconductor layer doped with an impurity, i.e., a back-gate effect suppression layer, provided right under a channel layer. A control electrode is formed on the substrate, which is in ohmic contact with the back-gate effect suppression layer via a second highly concentrated semiconductor layer of the second conductivity, so as to control the potential of the back-gate effect suppression layer. With such a structure of the semiconductor device, in operation, a predetermined fixed voltage is applied to the control electrode, and hence the backgate effect suppression layer is impressed with the fixed voltage. Therefore, the back-gate effect can be suppressed to a minimum.

0017PCT patent application, publication number <patcit id="pcit0009" dnum="WO0186727A2PCT"><text>WO0186727A2</text></patcit> discloses SiC MESFETs which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants and SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided.

Summary of the Invention

0018In accordance with the present invention, there is provided a MESFET and corresponding method of manufacturing the same as claimed in any of the accompanying claims.

Brief Description of the Drawings

0019<ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001"><b>Figure 1</b></figref> is a cross-sectional view of a transistor according to embodiments of the present invention;</li><li><figref idref="f0001 f0002 f0003 f0004"><b>Figures 2A</b> through <b>2G</b></figref> illustrate processing steps in the fabrication of transistors according to embodiments of the present invention;</li><li><figref idref="f0005"><b>Figure 3</b></figref> is a cross-sectional view of a transistor according to further embodiments of the present invention;</li><li><figref idref="f0006"><b>Figure 4</b></figref> is a cross-sectional view of a transistor according to further embodiments of the present invention; <figref idref="f0006">Figure 5</figref> is a cross-sectional view of a transistor according to further</li><li><figref idref="f0006"><b>Figure 5</b></figref> is a cross-sectional view of a transistor according to further embodiments of the present invention;</li><li><figref idref="f0007"><b>Figure 6</b></figref> is a plan view of a transistor according to embodiments of the present invention;</li><li><figref idref="f0008"><b>Figures 7A</b></figref> and <b>7B</b> are graphs illustrating the drain current-voltage characteristics of conventional MESFETS; and</li><li><figref idref="f0010"><b>Figures 8A</b></figref> and <figref idref="f0011"><b>8B</b></figref> are graphs illustrating the drain current-voltage characteristics of MESFETS according to embodiments of the present invention.</li></ul>

Detailed Description of the Invention

0020The present invention will now be described with reference to the <figref idref="f0001 f0002 f0003 f0004 f0005 f0006 f0007 f0008 f0009 f0010 f0011"><b>Figures 1</b> through 8B</figref>, which illustrate various embodiments of the present invention. As illustrated in the Figures, the sizes of layers or regions are exaggerated for illustrative purposes and, thus, are provided to illustrate the general structures of the present invention. Furthermore, various aspects of the present invention are described with reference to a layer being formed on a substrate or other layer. As will be appreciated by those of skill in the art, references to a layer being formed "on" another layer or substrate contemplates that additional layers may intervene. References to a layer being formed on another layer or substrate without an intervening layer are described herein as being formed "directly on" the layer or substrate. Furthermore, relative terms such as beneath may be used herein to describe one layer or regions relationship to another layer or region as illustrated in the Figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, layers or regions described as "beneath" other layers or regions would now be oriented "above" these other layers or regions. The term "beneath" is intended to encompass both above and beneath in this situation. Like numbers refer to like elements throughout.

0021It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention.

0022Embodiments of the present invention will now be described in detail below with reference to <figref idref="f0001 f0002 f0003 f0004 f0005 f0006 f0007 f0008 f0009 f0010 f0011"><b>Figures 1</b> through <b>8B</b></figref> that illustrate various embodiments of the present invention and various processes of fabricating embodiments of the present invention. A transistor, for example, a metal-semiconductor field effect transistor (MESFET), is provided having p-type conductivity regions beneath the sources of the MESFET having ends that extend towards the drains of the MESFET. As described in detail below, the presence of this p-type conductivity region, for example, p-type conductivity silicon carbide (SiC), may provide, for example, devices having improved breakdown voltages without compromising other performance characteristics of the device. Improved breakdown voltages may be provided because the presence of the p-type conductivity region may inhibit electron injection from the source, which in turn may increase breakdown voltage. Transistors according to embodiments of the present invention may be useful in, for example, high efficiency linear power amplifiers, such as power amplifiers for base stations using complex modulation schemes such as code division multiple access (CDMA) and/or Wideband CDMA (WCDMA).

0023Referring to <figref idref="f0001"><b>Figure 1</b></figref>, transistors, for example, metal-semiconductor field effect transistors (MESFETs), according to embodiments of the present invention will now be described in detail. As seen in <figref idref="f0001"><b>Figure 1</b></figref>, a substrate <b>10</b> is provided. The substrate <b>10</b> may be a single crystal bulk silicon carbide (SiC) substrate of either p-type or n-type conductivity or semi-insulating. The substrate <b>10</b> of either p-type or n-type may be very lightly doped. The substrate may be formed of silicon carbide selected from the group of 6H, 4H, 15R or 3C silicon carbide. Although the present invention is described herein with reference to a SiC substrate, the present invention should not be limited to SiC. For example, in some embodiments, the substrate <b>10</b> may also include, for example, gallium arsenide (GaAs) and/or Gallium Nitride (GaN).

0024An optional buffer layer <b>12</b> of, for example, p-type silicon carbide may be provided on the substrate <b>10</b>. The buffer layer <b>12</b> may be formed of p-type conductivity silicon carbide of 6H, 4H, 15R or 3C polytype. The buffer layer <b>12</b> may, for example, have a carrier concentration of from about 0.5 x 10¹⁵ cm^-3 to about 3.0 x 10¹⁵ cm^-3. Suitable dopants include aluminum, boron and/or gallium. The buffer layer <b>12</b> may have a thickness of about 2.0 µm. Although the buffer layer <b>12</b> is described above as p-type silicon carbide, the invention should not be limited to this configuration. Alternatively, the buffer layer <b>12</b> may be undoped silicon carbide (<i>i.e.</i> not intentionally doped) or very low-doped n-type conductivity silicon carbide. If a very low doped n-type silicon carbide is utilized for the buffer layer <b>12,</b> the carrier concentration of the buffer layer <b>12</b> is preferably less than about 5.0 x10¹⁴ cm^-3.

0025As further illustrated in <figref idref="f0001"><b>Figure 1</b></figref>, a p⁺ region <b>14</b> is provided beneath a source of the device that has an end that extends towards the drain of the device. As used herein, "p⁺ " or ^"n⁺ " refer to regions that are defined by higher carrier concentrations than are present in adjacent or other regions of the same or another layer or substrate. In some embodiments of the present invention, the p⁺ conductivity region <b>14</b> may extend from beneath a source contact <b>26</b> and/or from beneath an n⁺ source implant region <b>13</b> without extending to beneath an n⁺ drain implant region <b>17</b>. In further embodiments of the present invention, the p⁺ conductivity region <b>14</b> may extend from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> without extending to beneath a drain contact <b>22</b>. In still further embodiments, the p⁺ conductivity region <b>14</b> may further extend from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> to the first sidewall of the gate <b>31</b> without extending past the first sidewall of the gate <b>31</b>, from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> to the second sidewall of the gate <b>33</b> without extending past the second sidewall of the gate <b>33</b> or from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> to a point between the first sidewall <b>31</b> and the second sidewall <b>33</b> of the gate <b>24</b>. In certain embodiments of the present invention, the p⁺ conductivity region <b>14</b> may extend to a point within about 0.1 to about 0.3 µm of the first sidewall <b>31</b> of the gate <b>24</b> on the source side.

0026The p⁺ region <b>14</b> is a region of p-type conductivity, for example, p-type conductivity silicon carbide. For the p⁺ region <b>14</b>, carrier concentrations of from about 1.0 x 10¹⁸ cm^-3 to about 1.0 x 10²⁰ cm^-3 may be suitable, but carrier concentrations as high as possible are preferred. The carrier concentration may not be constant throughout the p⁺ region <b>14</b>, but it is preferable that the carrier concentration be as high as possible at the surface of the p⁺ region <b>14</b> to facilitate the formation of ohmic contacts thereon. In some embodiments of the present invention, the p⁺ conductivity region <b>14</b> may be provided in the substrate <b>10</b> as illustrated in <figref idref="f0005"><b>Figure 3</b></figref>. The p⁺ conductivity region <b>14</b> may, for example, extend about 0.4 µm into the buffer layer <b>12</b> or the substrate <b>10</b>. The presence of the p⁺ conductivity region <b>14</b> beneath the source region may inhibit electron injection from the source, thus, possibly providing an improved breakdown voltage. Furthermore, the fact that the p⁺ conductivity region <b>14</b> does not extend to beneath the drain region may hinder the introduction of parasitics into the device and, thus, device performance may not be influenced.

0027The buffer layer <b>12</b> may be disposed between the substrate <b>10</b> and a second buffer layer <b>16.</b> The second buffer layer <b>16</b> may be, for example, p-type silicon carbide having a carrier concentration of from about 1 x 10¹⁶ cm^-3 to about 5 x 10¹⁶ cm^-3, but typically about 1.5 x 10¹⁶ cm^-3. The p-type silicon carbide buffer layer <b>16</b> may also have a thickness of from about 0.5 µm to about 1.0 µm. Although the second buffer layer <b>16</b> is described above as being of p-type conductivity silicon carbide, it will be understood that the present invention is not limited to this configuration. Alternatively, for example, the second buffer layer <b>16</b> may be of n-type conductivity, for example, very lightly doped n-type conductivity SiC or undoped SiC as discussed above with respect to buffer layer <b>12</b>. In some embodiments of the present invention, the second buffer layer <b>16</b> may be provided directly on the substrate <b>10</b> as illustrated in <figref idref="f0005"><b>Figure 3</b></figref>.

0028An n-type conductivity channel layer <b>18</b> is provided on the second buffer layer <b>16</b>, as illustrated in <figref idref="f0001"><b>Figure 1</b></figref>. The n-type conductivity channel layer <b>18</b> may be formed of n-type conductivity silicon carbide of 6H, 4H, 15R or 3C polytype. The n-type conductivity channel layer may include one or more layers of, for example, n-type conductivity silicon carbide having different carrier concentrations. For example, the n-type conductivity channel layer <b>18</b> may include a first n-type conductivity channel layer <b>15</b> and a second n-type conductivity channel layer <b>19</b> as illustrated in <figref idref="f0006"><b>Figure 4</b></figref>. Alternatively, the n-type conductivity channel layer <b>18</b> may include first, second and third layers of n-type conductivity SiC as discussed in detail in commonly assigned United States Patent Application published as <patcit id="pcit0010" dnum="US20030075719A1"><text>US 2003-0075719 A1 to Sriram</text></patcit>.

0029As further illustrated in <figref idref="f0001"><b>Figure 1</b></figref><b>,</b> n⁺ regions <b>13</b> and <b>17</b> are provided in the source and drain regions of the device, respectively. Regions <b>13</b> and <b>17</b> are typically of n-type conductivity silicon carbide and have carrier concentrations that are greater than the carrier concentration of the n-type conductivity channel layer <b>18</b>. For the n⁺ regions <b>13</b> and <b>17</b>, carrier concentrations of about 1 x 10¹⁹ cm^-3 may be suitable, but carrier concentrations as high as possible are preferred.

0030Ohmic contacts <b>26</b> and <b>22</b> are provided on the implanted regions <b>13</b> and <b>17</b>, respectively, and are spaced apart so as to provide the source contact <b>26</b> and the drain contact <b>22.</b> Ohmic contact <b>25</b> is provided on the p⁺ conductivity region <b>14</b> to provide a p⁺ contact <b>25</b>. The ohmic contacts <b>25, 26</b> and <b>22</b> are preferably formed of nickel or other suitable metals. The p⁺ conductivity region <b>14</b> is maintained at the same potential as the source by, for example, electrically coupling the p⁺ ohmic contact <b>25</b> to the source contact <b>26</b>. An insulator layer <b>20</b>, such as an oxide, may be further provided on the exposed surface of the device.

0031Transistors according to certain embodiments of the present invention include a first recess <b>43</b> and a contact via hole <b>42</b>. The first recess <b>43</b> is provided between first and second n⁺ regions <b>13</b> and <b>17</b>, <i>i.e.</i> between the source region and the drain region. The first recess <b>43</b> extends into the n-type conductivity channel layer <b>18</b> and exposes the n-type conductivity channel layer <b>18.</b> The contact via hole <b>42</b> is provided adjacent the source region <b>13</b> and exposes at least a portion of the p⁺ region <b>14</b>.

0032Transistors according to embodiments of the present invention may include a double recessed structure containing first and second recesses as illustrated in <figref idref="f0006">Figure <b>4</b></figref>. In particular, a first recess <b>53</b> has a floor <b>60</b> that extends through the first n-type conductivity channel layer <b>19</b> to the second n-type channel layer <b>15</b>. A second recess <b>54</b> is provided between the sidewalls <b>61, 62</b> of the first recess. A first sidewall <b>61</b> of the first recess <b>53</b> is between the source <b>26</b> and the gate <b>24</b> and a second sidewall <b>62</b> of the first recess <b>53</b> is between the drain <b>22</b> and the gate <b>24</b>. The floor of the second recess <b>54</b> extends into the second n-type conductivity channel layer <b>15</b>, for example, a distance of about 600 Å. The double recessed structure is discussed further in commonly assigned United States Patent Application published as <patcit id="pcit0011" dnum="US20030075719A1"><text>US 2003-0075719 A1 to Sriram</text></patcit>.

0033Referring again to <figref idref="f0001"><b>Figure 1</b></figref>, the gate contact <b>24</b> may be provided in the first recess <b>43</b> between the source region <b>13</b> and the drain region <b>17</b>. In embodiments of the present invention having a double recessed structure as discussed above, the gate <b>24</b> may be disposed in the second recess <b>54</b> as illustrated in <figref idref="f0006"><b>Figure 4</b></figref><b>.</b> Furthermore, in certain embodiments of the present invention, the gate contact <b>24</b> may be disposed on the n-type conductivity channel layer <b>18</b> as illustrated in <figref idref="f0006"><b>Figure 5</b></figref> and may not be provided in, for example, the first recess <b>43</b> or the second recess <b>54.</b>

0034The gate contact <b>24</b> may be formed of chromium, platinum, platinum silicide, nickel, and/or TiWN, however, other metals such as gold, known to one skilled in the art to achieve the Schottky effect, may be used. The Schottky gate contact <b>24</b> typically has a three layer structure. Such a structure may have advantages because of the high adhesion of chromium (Cr). For example, the gate contact <b>24</b> can optionally include a first gate layer of chromium (Cr) contacting the n-type conductivity channel layer <b>18.</b> The gate contact <b>24</b> may further include an overlayer of platinum (Pt) and gold <b>32</b> or other highly conductive metal. Alternatively, the gate contact <b>24</b> may include a first layer of nickel in the first recess <b>43</b> on the n-type conductivity channel layer <b>18.</b> The gate contact <b>24</b> may further include an overlayer on the first layer of nickel that includes a layer of gold.

0035As further illustrated in <figref idref="f0001"><b>Figure 1</b></figref>, metal overlayers <b>28, 30</b> and <b>32</b> may be provided on the source and p⁺ contacts <b>26</b> and <b>25,</b> the drain contact <b>22</b> and the gate contact <b>24,</b> respectively. The overlayers <b>28, 30</b> and <b>32</b> may be gold, silver, aluminum, platinum and/or copper. Other suitable highly conductive metals may also be used for the overlayer. Furthermore, the metal overlayer <b>28</b> may electrically couple the p⁺ contact <b>25</b> of the p⁺ region <b>14</b> to the source contact <b>26.</b>

0036In selecting the dimensions of the MESFET, the width of the gate is defined as the dimension of the gate perpendicular to the flow of current. As shown in the cross-section of <figref idref="f0001"><b>Figure 1</b></figref>, the gate width runs into and out of the page. The length of the gate is the dimension of the gate parallel to the flow of current. As seen in the cross-sectional views of <figref idref="f0001"><b>Figure</b> 1</figref>, the gate length is the dimension of the gate <b>24</b> that is in contact with the n-type conductivity channel layer <b>18.</b> For example, the gate length of the MESFET according to certain embodiments of the present invention may be from about 0.4 µm to about 0.7 µm. Another important dimension is the source to gate distance, which is shown in the cross-section of <figref idref="f0001"><b>Figure 1</b></figref>, as the distance from the source contact <b>26</b> or n⁺ region <b>13</b>, to the gate contact <b>24</b>. The source to gate distance according to certain embodiments of the present invention may be from about 0.5 µm to about 0.7 µm. Furthermore, the distance from the drain <b>22</b> to the gate <b>24</b> may be from about 1.5 µm to about 2 µm. Embodiments of the present invention may further include a plurality of unit cells of MESFETs, and the distance from a first gate of the unit cells to a second gate may be, for example, from about 20 µm to about 50 µm.

0037<figref idref="f0001 f0002 f0003 f0004 f0005"><b>Figures 2A</b> through <b>2H</b></figref> illustrate the fabrication of FETs according to embodiments of the present invention. As seen in <figref idref="f0001"><b>Figure 2A</b></figref>, an optional buffer layer <b>12</b> may be grown or deposited on a substrate <b>10</b>. The substrate <b>10</b> may be a semi-insulating SiC substrate, a p-type substrate or an n-type substrate. The substrate <b>10</b> may be very lightly doped. The buffer layer <b>12</b> may be of p-type conductivity silicon carbide having a carrier concentration of about 3.0 x 10¹⁵ cm^-3 or less, but typically 1.0 x 10¹⁵ cm^-3 or less. Alternatively, the buffer layer <b>12</b> may be n-type silicon carbide or undoped silicon carbide.

0038If the substrate <b>10</b> is semi-insulating it may be fabricated as described in commonly assigned United States Patent No. <patcit id="pcit0012" dnum="US6218680B"><text>6,218,680 to Carter et al.</text></patcit> entitled "Semi-insulating Silicon Carbide Without Vanadium Domination". Such a semi-insulating substrate may be produced by providing silicon carbide substrates with sufficiently high levels of point defects and sufficiently matched levels of p-type and n-type dopants such that the resistivity of the silicon carbide substrate is dominated by the point defects. Such a domination may be accomplished by fabricating the silicon carbide substrate at elevated temperatures with source powders that have concentrations of heavy metals, transition elements or other deep level trapping elements of less than about 1 x 10¹⁶ cm^-3 and preferably less than about 1.0 x 10¹⁴ cm^-3. For example, temperatures between about 2360 °C and 2380 °C with the seed being about 300 °C to about 500 °C lower may be utilized. Thus, it is preferred that the semi-insulating substrate be substantially free of heavy metal, transition element dopants or other deep level trapping elements, such as vanadium, such that the resistivity of the substrate is not dominated by such heavy metals or transition elements. While it is preferred that the semi-insulating substrate be free of such heavy metal, transition element dopants or deep level trapping elements, such elements may be present in measurable amounts while still benefiting from the teachings of the present invention if the presence of such materials does not substantially affect the electrical properties of the MESFETs described herein.

0039As further illustrated in <figref idref="f0001"><b>Figure 2A</b></figref>, a mask <b>45</b> may be formed for implanting the p⁺ region <b>14</b>. The p⁺ region <b>14</b> is typically formed by ion implantation of, for example, aluminum, boron and/or gallium, followed by a high temperature anneal. Suitable anneal temperatures may be from about 1300 to about 1600 ° C, typically about 1500 ° C. The ion implantation may be performed on the regions that are not covered by the mask <b>45</b> to form p⁺ region <b>14</b> as illustrated in <figref idref="f0002"><b>Figure 2B</b></figref>. Thus, the ions are implanted in portions of the buffer layer <b>12</b>, if present, or the substrate <b>10</b>, to provide a highly doped region of p-type conductivity, for example, p-type conductivity silicon carbide. Once implanted, the dopants are annealed to activate the implant. The highly doped region of p-type conductivity may extend about 0.4 µm into the buffer layer <b>12</b> or the substrate <b>10.</b>

0040As seen in <figref idref="f0002"><b>Figure 2B</b></figref>, a second buffer layer <b>16</b> and an n-type conductivity channel layer <b>18</b> are grown or deposited on the buffer layer <b>12.</b> It will be understood that if the buffer layer <b>12</b> is not included, the second buffer layer <b>16</b> and the n-type conductivity channel layer <b>18</b> may be grown or deposited on the substrate <b>10.</b> The second buffer layer <b>16</b> is formed on the buffer layer <b>12</b> and the n-type conductivity channel layer <b>18</b> is formed on the second buffer layer <b>16</b> as illustrated in <figref idref="f0002"><b>Figure 2B</b></figref>.

0041As illustrated in <figref idref="f0002"><b>Figure 2C</b></figref>, a mask <b>50</b> may be formed for implanting n⁺ regions <b>13</b> and <b>17.</b> Regions <b>13</b> and <b>17</b> are typically formed by ion implantation of, for example, nitrogen (N) or phosphorus (P), followed by a high temperature anneal. Suitable anneal temperatures may be from about 1100 to about 1600 ° C. The ion implantation may be performed on the regions which are not covered by the mask <b>50</b> to form n⁺ regions <b>13</b> and <b>17</b> as illustrated in <figref idref="f0003"><b>Figure 2D</b></figref><b>.</b> Thus, the ions are implanted in portions of the n-type conductivity channel layer <b>18</b> to provide highly doped regions of n-type conductivity, for example, n-type conductivity SiC, having higher carrier concentrations than the n-type conductivity channel layer <b>18.</b> Once implanted, the dopants are annealed to activate the implant.

0042As seen in <figref idref="f0003"><b>Figure 2D</b></figref>, the substrate <b>10</b>, the buffer layer <b>12</b>, the p⁺ region <b>14</b>, the second buffer layer <b>16</b> and the n-type conductivity channel layer <b>18</b> may be etched to form an isolation mesa. The mesa has sidewalls <b>55, 57</b> defined by the substrate <b>10</b>, the buffer layer <b>12</b>, the p⁺ region <b>14</b>, the second buffer layer <b>16</b> and the n-type conductivity channel layer <b>18</b> that define the periphery of the transistor. The sidewalls of the mesa extend downward past the p⁺ conductivity region <b>14.</b> The mesa may be formed to extend into the substrate <b>10</b> of the device as shown in <figref idref="f0003"><b>Figure 2D</b></figref>. The mesa may extend past the depletion region of the device to confine current flow in the device to the mesa and reduce the capacitance of the device. The mesa is preferably formed by reactive ion etching the above described device, however, other methods known to one skilled in the art may be used to form the mesa. Furthermore, if a mesa is not utilized the device may be isolated using other methods such as proton bombardment, counterdoping with compensating atoms or other methods known to those skilled in the art.

0043In certain embodiments, only the second buffer layer <b>16</b> and the n-type conductivity channel layer <b>18</b> may be etched to form an isolation mesa as shown in <figref idref="f0006"><b>Figure 4</b></figref>. In these embodiments, the sidewalls <b>55, 57</b> are defined by the second buffer layer <b>16</b> and the n-type conductivity channel layer <b>18</b>, which define the periphery of the transistor.

0044<figref idref="f0003"><b>Figure 2D</b></figref> further illustrates the formation of a first recess <b>43</b> of the MESFET. The first recess <b>43</b> may be formed by forming a mask <b>47</b> and then etching through the n-type conductivity channel layer <b>18</b> to form the first recess <b>43</b> according to the mask <b>47.</b> The first recess <b>43</b> may be formed by an etching process, such as a dry or wet etch process. For example, the first recess <b>43</b> may be formed by dry etching, for example, Electron Cyclotron Resonance (ECR) or Inductively Coupled Plasma (ICP) etching. The mask <b>47</b> may be removed.

0045As discussed above, embodiments of the present invention may include a double recessed structure instead of the single recess <b>43.</b> As illustrated in <figref idref="f0006"><b>Figure 4</b></figref>, a first recess <b>53</b> of the double recessed structure may be formed by forming a mask for the first recess <b>53</b> and etching through the first n-type conductivity channel layer <b>19</b> to form the first recess <b>53</b> according to the mask. An insulation layer may be formed after the first recess <b>53</b> has been formed. After forming the ohmic contacts as illustrated in <figref idref="f0004"><b>FIG. 2G</b></figref>, a second recess <b>54</b> of the double recessed structure may be formed by forming a second mask for the second recess and etching the recess according to the mask. The second n-type conductivity channel layer <b>15</b> may be etched into a distance of, for example, about 600 Å to form the second recess <b>54.</b> Methods of fabricating the double recessed structure are discussed further in commonly assigned United States Patent Application published as <patcit id="pcit0013" dnum="US20030075719A1"><text>US 2003-0075719 A1 to Sriram</text></patcit>.

0046<figref idref="f0003"><b>Figure 2E</b></figref> illustrates the formation of an insulator layer <b>20,</b> for example, an oxide layer, after the first recess <b>43</b> has been formed as discussed above. The insulator layer <b>20</b> may be grown or deposited over the exposed surface of the existing structure, <i>i.e.</i> on the isolation mesa, n⁺ regions <b>13</b> and <b>17</b>, the n-type conductivity channel layer <b>18</b> and in the first recess <b>43</b>. The oxidation process may remove, for example, SiC that may have been damaged by the etch process and may also smooth out roughness that may have been created on the surface by the etch.

0047As illustrated in <figref idref="f0004"><b>Figure 2F</b></figref>, contact windows may be etched through the insulator layer <b>20</b> to the n⁺ regions <b>13</b> and <b>17</b>. A third contact window <b>41</b> may be etched in the insulator layer <b>20</b> above the highly doped p⁺ region <b>14.</b> Nickel may then be evaporated to deposit the source and drain contacts <b>26</b> and <b>22</b>, respectively. The nickel may be annealed to form the ohmic contacts <b>26</b> and <b>22</b> as illustrated in <figref idref="f0004"><b>Figure 2F</b></figref>. Such a deposition and annealing process may be carried out utilizing conventional techniques known to those of skill in the art. For example, the ohmic contacts <b>26</b> and <b>22</b> may be annealed at a temperature of from about 950 ° C to about 1100 ° C for about 2 minutes. However, other times and temperatures may also be utilized. Times from about 30 seconds to about 10 minutes may be, for example, acceptable.

0048As illustrated in <figref idref="f0004"><b>Figure 2G</b></figref>, a contact via hole <b>42</b> of the MESFET may be formed. The contact via hole <b>42</b> may be etched in the portion of the MESFET defined by window <b>41</b> in the insulator layer <b>20.</b> The n-type conductivity channel layer <b>18</b> and the second buffer layer <b>16</b> may be etched through to expose the p⁺ conductivity region <b>14</b> to form the contact via hole <b>42</b>. The etching process may be, for example, a dry or wet etch process. As further illustrated in <figref idref="f0004"><b>Figure 2G</b></figref>, nickel may be evaporated to deposit the p⁺ contact <b>25</b>. The nickel may be annealed to form the ohmic contact <b>25</b>. Such a deposition and annealing process may be carried out utilizing conventional techniques known to those of skill in the art. For example, the ohmic contact <b>25</b> may be annealed at a temperature of from about 600 ° C to about 1050 ° C.

0049<figref idref="f0005"><b>Figure 2H</b></figref> illustrates the formation of the gate contact <b>24</b> and the overlayers <b>28, 30</b> and <b>32</b>. For example, a window may be opened in the insulator <b>20</b> and a layer of chromium may be deposited in the first recess <b>43</b>. Typically, the chromium layer is formed by evaporative deposition. The gate structure may then be completed by deposition of platinum and gold. As will also be appreciated by those of skill in the art, the overlayers <b>28</b> and <b>30</b> may be formed either before or after formation of the gate structure. In fact, if the titanium/platinum/gold structure is utilized, the platinum and gold portions of the overlayer may be formed in the same processing steps as the platinum and gold portions <b>32</b> of the gate structure. Accordingly, the overlayers <b>28</b> and <b>30</b> may be formed prior to the formation of a gate contact or after the formation of a gate contact. As further illustrated, the source contact <b>26</b> and the p⁺ contact share a single overlayer <b>28</b>, which electrically couples the source to the highly doped p-type conductivity region <b>14</b>. Alternatively, as discussed above the first recess <b>43</b> may be a double recess structure and the gate may be disposed within the double recessed structure.

0050Referring now to <figref idref="f0005"><b>Figure 3</b></figref>, a cross-sectional view of a transistor according to further embodiments of the present invention will be discussed. Like numbers refer to like elements in previously described figures, thus, detailed descriptions of these elements will be omitted. As seen in <figref idref="f0005"><b>Figure 3</b></figref>, a substrate <b>10</b> is provided. The substrate <b>10</b> may be, for example, SiC, GaAs or GaN. A p⁺ region <b>14</b> is provided beneath a source of the device and has an end that extends towards the drain of the device. In some embodiments of the present invention, the p⁺ conductivity region <b>14</b> may extend from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> extending to beneath the n⁺ drain implant region <b>17</b>. In further embodiments of the present invention, the p⁺ conductivity region <b>14</b> may extend from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> without expending to beneath the drain contact <b>22.</b> In embodiments of the present invention illustrated in <figref idref="f0005"><b>Figure 3</b></figref>, the p⁺ conductivity region <b>14</b> is provided in the substrate <b>10</b>.

0051A second buffer layer <b>16</b> is provided on the substrate <b>10</b> and the p⁺ conductivity region <b>14.</b> An n-type conductivity channel layer <b>18</b> is provided on the second buffer layer <b>16</b>. The n⁺ regions <b>13</b> and <b>17</b> are provided in the source and drain regions of the device, respectively. Ohmic contacts <b>26</b> and <b>22</b> are provided on the implanted regions <b>13</b> and <b>17</b>, respectively, and are spaced apart so as to provide the source contact <b>26</b> and the drain contact <b>22</b>. Ohmic contact <b>25</b> is provided on the p⁺ conductivity region <b>14</b> to provide a p⁺ contact <b>25</b>. The p⁺ conductivity region <b>14</b> is maintained at the same potential as the source by, for example, electrically coupling the p⁺ ohmic contact <b>25</b> to the source contact <b>26</b>. An insulator layer <b>20</b>, such as an oxide, is further provided on the exposed surface of the device.

0052A first recess <b>43</b> is provided between first and second n⁺ regions <b>13</b> and <b>17</b>, <i>i.e.</i> between the source region and the drain region. The first recess <b>43</b> extends into the n-type conductivity channel layer <b>18</b> and exposes the n-type conductivity channel layer <b>18</b>. A contact via hole <b>42</b> is provided adjacent the source region <b>13</b> and exposes at least a portion of the p⁺ region. The gate contact <b>24</b> is provided in the first recess <b>43</b> between the source region <b>13</b> and the drain region <b>17</b>. As further illustrated in <figref idref="f0005"><b>Figure 3</b></figref>, metal overlayers <b>28, 30</b> and <b>32</b> may be provided on the source and p⁺ contacts <b>26</b> and <b>25</b>, the drain contact <b>22</b> and the gate contact <b>24</b>, respectively. Furthermore, metal overlayer <b>28</b> may electrically couple the p⁺ contact <b>25</b> of the p⁺ region <b>14</b> to the source contact <b>26</b>.

0053Referring now to <figref idref="f0006"><b>Figure 4</b></figref>, a cross-sectional view of a transistor according to further embodiments of the present invention will be discussed. Like numbers refer to like elements in previously described figures, thus, detailed descriptions of these element will be omitted. As seen in <figref idref="f0006"><b>Figure 4</b></figref>, a substrate <b>10</b> is provided. The substrate <b>10</b> may be, for example, SiC, GaAs or GaN. A p⁺ region <b>14</b> is provided beneath a source of the device and has an end that extends toward the drain of the device. In some embodiments of the present invention, the p⁺ conductivity region <b>14</b> may extend from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> without extending to beneath the n⁺ drain implant region <b>17</b>. In further embodiments of the present invention, the p⁺ conductivity region <b>14</b> may extend from beneath the source contact <b>26</b> and/or from beneath the n⁺ source implant region <b>13</b> without extending to beneath the drain contact <b>22</b>. The p⁺ conductivity region <b>14</b> is provided in the substrate <b>10</b>. A buffer layer <b>16</b> is provided on the substrate <b>10</b> and the p⁺ conductivity region <b>14</b>. The buffer layer <b>16</b> may be, for example, p-type conductivity silicon carbide having a carrier concentration of about 1.5 x 10¹⁶ cm^-3 and a thickness of about 0.5 µm.

0054A first n-type conductivity channel layer <b>15</b> is provided on the buffer layer <b>16</b>. The first n-type conductivity channel layer <b>15</b> may have, for example, a carrier concentration of about 3 x 10¹⁷ cm^-3 and a thickness of about 0.28 µm. The second n-type conductivity channel layer <b>19</b> may be on the first n-type channel layer <b>15</b> and may have, for example, a carrier concentration of about 1 x 10¹⁶ cm^-3 and a thickness of about 900 Å.

0055The n⁺ regions <b>13</b> and <b>17</b> are provided in the source and drain regions of the device, respectively. Ohmic contacts <b>26</b> and <b>22</b> are provided on the implanted regions <b>13</b> and <b>17</b>, respectively, and are spaced apart so as to provide the source contact <b>26</b> and the drain contact <b>22</b>. Ohmic contact <b>25</b> is provided on the p⁺ conductivity region <b>14</b> to provide a p⁺ contact <b>25</b>. The p⁺ conductivity region <b>14</b> is maintained at the same potential as the source by, for example, electrically coupling the p⁺ ohmic contact <b>25</b> to the source contact <b>26</b>. An insulator layer <b>20</b>, such as an oxide, is further provided on the exposed surface of the device. The second buffer layer <b>16</b>, the first n-type conductivity channel layer <b>15</b> and the second n-type conductivity layer <b>19</b> may be etched to form an isolation mesa. As illustrated, the mesa includes sidewalls <b>55, 57</b> that define the periphery of the transistor.

0056As illustrated in <figref idref="f0006"><b>Figure 4</b></figref>, a double recess in provided in the transistor of <figref idref="f0006"><b>Figure 4</b></figref>. The double recessed structure is provided between first and second n⁺ regions <b>13</b> and <b>17,</b><i>i.e.</i> between the source region and the drain region. The first recess <b>53</b> has a floor <b>60</b> that extends through the second n-type conductivity channel layer <b>19</b> to the first n-type conductivity channel layer <b>15</b> and exposes the first n-type conductivity channel layer <b>15.</b> In certain embodiments, the first recess <b>53</b> may extend into the first n-type conductivity channel layer <b>15.</b> The second recess <b>54</b> is provided between the sidewalls <b>61, 62</b> of the first recess. A first sidewall <b>61</b> of the first recess <b>53</b> is between the source 26 and the gate <b>24</b> and a second sidewall <b>62</b> of the first recess <b>53</b> is between the drain <b>22</b> and the gate <b>24.</b> The floor of the second recess <b>54</b> extends into the second n-type conductivity channel layer <b>15</b>, for example, a distance of about 600 Å.

0057A contact via hole <b>42</b> is provided adjacent the source region <b>13</b> and exposes at least a portion of the p⁺ region. The gate contact <b>24</b> is provided in the second recess <b>54</b> between the source region <b>13</b> and the drain region <b>17</b>. As further illustrated in <figref idref="f0006"><b>Figure 4</b></figref>, metal overlayers <b>28, 30</b> and <b>32</b> may be provided on the source and p⁺ contacts <b>26</b> and <b>25</b>, the drain contact <b>22</b> and the gate contact <b>24</b>, respectively. Furthermore, metal overlayer <b>28</b> may electrically couple the p⁺ contact <b>25</b> of the p⁺ region <b>14</b> to the source contact <b>26.</b>

0058Now referring to <figref idref="f0006"><b>Figure 5</b></figref>, a cross-sectional view of a MESFET according to further embodiments of the present invention will be discussed. Like numbers refer to like elements in previously described figures, thus, descriptions of these elements will be omitted. As illustrated in <figref idref="f0006"><b>Figure 5</b></figref>, the gate <b>24</b> is disposed on the n-type conductivity channel layer <b>18</b> and is not disposed in a single or double recess.

0059Referring now to <figref idref="f0007"><b>Figure 6</b></figref>, a plan view (top view) of MESFETs according to certain embodiments of the present invention will be described. As illustrated in <figref idref="f0007"><b>Figure 6</b></figref>, a plurality of unit cells are provided on a substrate <b>10.</b> A gate <b>24</b> is situated between a source region <b>26</b> and a drain region <b>22</b>. As illustrated in <figref idref="f0007"><b>Figure 6</b></figref>, the source contacts <b>26</b> and drain contacts <b>22</b> are interdigitated. An overlayer <b>28</b> electrically couples the source region <b>26</b> to a p⁺ region (not shown) via a p⁺ contact (not shown) that is disposed in the contact via hole <b>43</b>.

0060<figref idref="f0008"><b>Figures 7A</b></figref><b>and7B</b> are graphs illustrating the drain current-voltage characteristics of conventional MESFETs at low voltages and high voltages, respectively. <figref idref="f0010"><b>Figures 8A</b></figref> and <figref idref="f0011"><b>8B</b></figref> are graphs illustrating the drain current-voltage characteristics of MESFETs according to embodiments of the present invention at low voltages and high voltages, respectively. The data illustrated in <figref idref="f0008"><b>Figures 7A</b></figref>, <figref idref="f0009"><b>7B</b></figref>, <figref idref="f0010"><b>8A</b></figref> and <figref idref="f0011"><b>8B</b></figref> was obtained from a conventional MESFET device and a MESFET device according to embodiments of the present invention that were fabricated on the same wafer. Fabrication of these devices on the same wafer may reduce the number of uncertainties due to variations in wafer properties.

0061Referring now to <figref idref="f0008"><b>Figures 7A</b></figref> and <figref idref="f0010"><b>8A</b></figref>, the conventional MESFET and the MESFET according to embodiments of the present invention may have similar characteristics at low drain voltages. However, as illustrated in <figref idref="f0009"><b>Figures 7B</b></figref> and <figref idref="f0011"><b>8B</b></figref>, at high drain voltages, <i>e.g.</i> drain voltages exceeding 70 volts, the conventional MESFET experiences excessive leakage current and low transconductance (<figref idref="f0009"><b>Figure 7B</b></figref>). These device characteristics may degrade the power output and RF gain of such devices. In contrast, as illustrated in <figref idref="f0011"><b>Figure 8B</b></figref>, MESFETs according to embodiments of the present invention that include the p-type conductivity layer may provide a low leakage current and increased transconductance at high drain voltages.

0062Although the present invention is described above with respect to particular MESFETs having particular layers, regions and recesses, it will be understood that embodiments of the present invention are not limited to the above described MESFETs. A p-type conductivity region beneath the source region of according to embodiments of the present invention may be incorporated in to other types of transistors. For example, the p-type conductivity region according to embodiments of the present invention may be incorporated into MESFETs described in commonly assigned United States Patent Application Serial No. <patcit id="pcit0014" dnum="US09567717B"><text>09/567,717</text></patcit> entitled <i>Silicon Carbide Metal Semiconductor Field Effect Transistors</i> to Allen <i>et al</i> published as patent <patcit id="pcit0015" dnum="US6686616B"><text>US 6 686 616</text></patcit>.

0063As is briefly described above, transistors according to embodiments of the present invention provide a p-type conductivity region beneath the source region of the transistor having an end that extends towards the drain region of the transistor. The presence of this p-type conductivity region may provide, for example, devices having improved breakdown voltages without compromising other performance characteristics of the device because the p-type conductivity region may inhibit electron injection from the source. This may provide an advantage over conventional field effect transistors that may sacrifice device performance characteristics to obtain a high breakdown voltage.

0064Although the present invention is described above with reference to SiC MESFETs, the present invention is not limited to SiC MESFETs. For example, MESFETs according to embodiments of the present invention may be, for example, gallium arsenide (GaAs) MESFETs or Gallium Nitride (GaN) MESFETs. In particular, if the present invention were described with respect to GaAs MESFETs, the p-type conductivity regions might be p-type conductivity GaAs regions, the n-type conductivity channel layers might be n-type conductivity GaAs layers and the like.

0065In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.