Data management apparatus and method of flash memory

0001The present invention relates to a data management apparatus and method for use in a flash memory, and more particularly, to a data management apparatus and method for use in a flash memory, which can deal with defective blocks in each flash memory in a system using at least one flash memory by taking into consideration how the system processes data stored in each flash memory.

0002In general, home appliances, communications devices, and embedded systems, such as set-top boxes, use non-volatile memories as storage devices for storing and processing data.

0003Flash memories are one type of non-volatile memory, in which data can be electrically erased and overwritten. Flash memories are suitable for portable devices because they consume less power than magnetic disc memory-based storage mediums, are as accessible as hard discs, and are compact-sized.

0004Due to the hardware characteristics of flash memories, data recorded on a flash memory should be erased before data is overwritten on the flash memory.

0005A unit in which data is recorded on a flash memory may differ from a unit in which data is erased from the flash memory, which may result in deterioration of the performance of the flash memory.

0006In order to prevent the performance of the flash memory from deteriorating for this reason, logical addresses and physical addresses have been suggested. Logical addresses are virtual addresses specified by a user when executing a data operation on the flash memory with the use of a program. By comparison, physical addresses are actual addresses referenced when executing the data operation on the flash memory.

0007Flash memory is generally classified into either a small block flash memory or a large block flash memory. In a small block flash memory, a logical operation unit is equal to a physical operation unit, whereas in a large block flash memory, a logical operation unit is smaller than a physical operation unit.

0008In other words, supposing that the logical operation unit and physical operation unit of the flash memory are respectively referred to as a sector and a page, a sector and a page of the small block flash memory are identical, but a page of the large block flash memory is a predetermined number of times larger than a sector of the large block flash memory.

0009Data can be erased from a flash memory only a limited number of times. If data is erased from some of a plurality of blocks of the flash memory more than a maximum number of times that data can be erased from the flash memory, or if some of the blocks of the flash memory, from which data is erased almost as many times as the maximum number, are fragile for some reason, the corresponding blocks may become defective.

0010Defective blocks of the flash memory are categorized into initial defective blocks, which are defective blocks detected before the flash memory is shipped out of the factory, or run-time defective blocks, which are defective blocks generated by a user during executing a data operation on the flash memory.

0011All of the blocks of the flash memory may become defective, and defective blocks of the flash memory considerably affect the performance of the flash memory. Thus, various methods to efficiently deal with the defective blocks of the flash memory have been developed.

0012<figref idref="f0001">Figure 1</figref> is a schematic diagram illustrating the structure of a typical flash memory. Referring to <figref idref="f0001">Figure 1</figref>, the typical flash memory includes a defective block management area 10, in which defective blocks of the typical flash memory are dealt with, and a data area 20, in which data computations are executed.

0013Specifically, the defective block management area 10 includes a defective block information area 11, which includes mapping information on the defective blocks of the typical flash memory, and a spare area 12, which provides substitute blocks that respectively replace the defective blocks of the typical flash memory.

0014Here, the mapping information on the defective blocks of the typical flash memory is realized as a mapping table that respectively maps the defective blocks of the typical flash memory with the substitute blocks in the spare area 12.

0015A conventional data management method using the defective block management area 10 will now be described. As shown in <figref idref="f0002">Figure 2</figref>, in operation S11, it is determined whether there is an indication that a predetermined or current block of the typical flash memory is an initial defective block.

0016In operation S12, it is determined whether the predetermined block is an initial defective block based on the determination results obtained in operation S11.

0017In operation S13, if the predetermined block is an initial defective block, the predetermined block of the flash memory is replaced with a normal block, specifically, a substitute block in the spare area 12, by referencing the mapping table.

0018Accordingly, a data operation, which is supposed to be performed on the predetermined block, can be performed on the substitute block that replaces the predetermined block.

0019In operation S14, it is determined if all blocks in the flash memory are subjected to defective block determination. If the predetermined block is not the last one, the iteration is initiated in operation S15 so that operations S11 through S14 can be performed on a block subsequent to the predetermined block.

0020If a defect occurs while performing the data operation on a block of the flash memory that has already been determined non-defective through operations S11 through S14, the corresponding block is determined to be a run-time defective block.

0021A conventional data management method for dealing with run-time defective blocks of a typical flash memory is illustrated in <figref idref="f0003">Figure 3</figref>. Referring to <figref idref="f0003">Figure 3</figref>, in operation S21, a data operation is performed on a predetermined or current block. In operation S22, it is determined whether the data operation has been successfully performed on the predetermined block.

0022Specifically, referring to <figref idref="f0004">Figure 4A</figref>, the data operation is performed on a block 21 of a flash memory, and then it is determined whether the data operation has been successfully performed on the block 21 of the flash memory.

0023If the data operation is determined unsuccessful, then in operation S23 the predetermined block is determined defective and then registered with the mapping table.

0024In operation S24, the predetermined block is mapped with a substitute block in the spare area 12. In operation S25, a data operation, which is supposed to be performed on the predetermined block, is performed on the substitute block.

0025Specifically, referring to <figref idref="f0005">Figure 4B</figref>, data stored in the block 21 in the data area 20 is transferred to a block 12a in the spare area 12.

0026Then, a data operation, which is supposed to be performed on the block 21 in the data area 20, is performed on the block 12a in the spare area 12 by referencing the mapping table specifying that the block 21 in the data area 20 is replaced with the block 12a in the spare area 12.

0027For example, if a defect occurs while writing data on the block 21 in the data area 20, part of the data that has been written on the block 21 is transferred from the block 21 to the block 12a in the spare area 12.

0028In addition, when a data operation is again performed on the block 21, the rest of the data is written on the block 12a in the spare area 12 by referencing the mapping table.

0029Thereafter, in operation S26, it is determined whether the data operation is complete. Unless the data operation is complete, operations S21 through S25 are repeatedly performed.

0030However, the above conventional data management methods of a flash memory can only be applied to a single flash memory and thus are not suitable for a system using plural flash memory.

0031<patcit id="pcit0001" dnum="US6081878A"><text>US 6,081,878</text></patcit> discloses a digital system having a controller semiconductor device coupled to a host and a non-volatile memory bank including a plurality of non-volatile memory devices. The memory bank includes a plurality of memory blocks comprised of a first sub-block of a first flash memory chip and a corresponding second sub-block of a second flash memory chip. A defect block flag provides information concerning the status of a whole block of the memory bank. A block that is unsuccessfully programmed is marked as defective by setting the defect flag. A block marked as defective is programmed into a corresponding free block. This document forms the precharacterising of the claims appended hereto.

0032<patcit id="pcit0002" dnum="US20020181285A"><text>US 2002/0181285</text></patcit> discloses a non-volatile storage system including a plurality of non-volatile memories and a control unit.

0033According to the present invention there is provided an apparatus and method as set forth in the appended claims. Preferred features of the invention will be apparent from the dependent claims, and the description which follows.

0034The present invention provides a data management apparatus and method of a flash memory, which can efficiently deal with defective blocks in each flash memory in a system using plural flash memory.

0035The above stated object as well as other objects, features and advantages, of the present invention will become clear to those skilled in the art upon review of the following description, the attached drawings and appended claims.

0036According to an exemplary embodiment of the present invention, there is provided a data management apparatus comprising: a device driver arranged to control a plurality of flash memories; a controller arranged to generate an upper block by combining together blocks of the plurality of flash memories having a same offset value; wherein the controller is arranged to transfer data stored in a defective block of one of the plurality of flash memories to a predetermined different block of said one flash memory; and characterized in that the controller allows the predetermined different block to be included in the upper block.

0037According to another exemplary embodiment of the present invention, there is provided a data management method of a flash memory comprising generating an upper block by combining together blocks of a plurality of flash memories having a same offset value; identifying a defective block that has occurred in at least one first flash memory; transferring data stored in the defective block to a predetermined different block in the first flash memory; and characterised in that further comprising allowing the predetermined different block to be included in the upper block.

0038When performing the data operation on the predetermined block, the identifying operation may comprise identifying a block of the first flash memory as the defective block depending on whether the data operation has been successfully performed on the predetermined block of the first flash memory.

0039The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: <ul id="ul0001" list-style="none"><li><figref idref="f0001">Figure 1</figref> is a schematic diagram of a typical flash memory;</li><li><figref idref="f0002">Figure 2</figref> is a flowchart of a conventional data management method that deals with initial defective blocks in a flash memory;</li><li><figref idref="f0003">Figure 3</figref> is a flowchart of a conventional data management method that deals with run-time defective blocks in a flash memory;</li><li><figref idref="f0004">Figure 4A</figref> is a diagram illustrating a data operation performed on a typical flash memory;</li><li><figref idref="f0005">Figure 4B</figref> is a diagram illustrating a method of transferring data stored in a run-time defective block in a data area of a typical flash memory to a substitute block in a spare area of the typical flash memory;</li><li><figref idref="f0006">Figure 5A</figref> is a block diagram of a typical multi-channel system using at least one flash memory;</li><li><figref idref="f0006">Figure 5B</figref> is a diagram illustrating a typical data operation performed in the typical multi-channel system of <figref idref="f0006">Figure 5A</figref>;</li><li><figref idref="f0007">Figure 6A</figref> is a block diagram of a typical interleaved system using one or more flash memories;</li><li><figref idref="f0007">Figure 6B</figref> is a diagram illustrating a typical data operation performed in the typical interleaved system of <figref idref="f0007">Figure 6A</figref>;</li><li><figref idref="f0008">Figure 7</figref> is a block diagram of a data management apparatus of a flash memory, according to an exemplary embodiment of the present invention;</li><li><figref idref="f0009">Figure 8</figref> is a diagram illustrating a data operation performed in a multi-channel system using one or more flash memories, according to an exemplary embodiment of the present invention;</li><li><figref idref="f0010">Figure 9</figref> is a diagram illustrating a data operation performed in an interleaved system using one or more flash memories, according to an exemplary embodiment of the present invention;</li><li><figref idref="f0011">Figure 10</figref> is a diagram illustrating virtual block management areas of <figref idref="f0010">Figure 9</figref>;</li><li><figref idref="f0012">Figure 11</figref> is a diagram illustrating a data operation performed on an upper block of <figref idref="f0010">Figure 9</figref>;</li><li><figref idref="f0013">Figure 12</figref> is a flowchart of a data management method of a flash memory, according to an exemplary embodiment of the present invention;</li><li><figref idref="f0014">Figure 13</figref> is a diagram illustrating a method of dealing with initial defective blocks of a flash memory, according to an exemplary embodiment of the present invention;</li><li><figref idref="f0015">Figures 14A and 14B</figref> are diagrams illustrating mapping tables, which respectively map defective blocks in a flash memory with substitute blocks in a spare area of the flash memory;</li><li><figref idref="f0016">Figure 15</figref> is a flowchart of a method of dealing with run-time defective blocks of one or more flash memories in a multi-channel system, according to an exemplary embodiment of the present invention;</li><li><figref idref="f0016">Figure 16</figref> is a diagram illustrating a method of transferring data stored in a run-time defective block in one or more flash memories in a multi-channel system to a block in a spare area of a corresponding flash memory;</li><li><figref idref="f0017">Figure 17</figref> is a flowchart of a method of dealing with run-time defective blocks in one or more flash memories in an interleaved system, according to an exemplary embodiment of the present invention;</li><li><figref idref="f0017">Figure 18</figref> is a diagram illustrating a data operation performed in an interleaved system using one or more flash memories, according to another exemplary embodiment of the present invention; and</li><li><figref idref="f0018">Figure 19</figref> is a diagram illustrating a method of transferring data stored in a run-time defective block in one or more flash memories in an interleaved system to a block in a spare area of a corresponding flash memory.</li></ul>

0040Advantages and features of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.

0041The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.

0042Recently, the performance of a system using one or more flash memories has been improved by adopting a multi-channel or interleaved approach.

0043In a multi-channel approach, the flash memories share a control line with one another, and thus data can be written in parallel on the flash memories at the same time.

0044Specifically, referring to <figref idref="f0006">Figure 5A</figref>, two flash memories 111 and 112 and a device driver 113, which controls the flash memories 111 and 112, share a control line 114. The flash memories 111 and 112 use different data lines, i.e., the flash memories 111 and 112 use data lines 115 and 116, respectively.

0045Therefore, the multi-channel approach enables m flash memories each comprised of n bits (where m and n are integers) to be operated as if there were only one flash memory, by making the m flash memories share mxn buses with one another.

0046Referring to <figref idref="f0006">Figure 5B</figref>, which illustrates the operation of the typical multi-channel system of <figref idref="f0006">Figure 5A</figref>, a control signal, including a data computation command and an address at which a data operation is to be performed, is transmitted (117) to the flash memory 112 and to the flash memory 113 at the same time because the flash memories 112 and 113 share the control line 114 with each other.

0047Since the flash memories 112 and 113 use the data lines 115 and 116, respectively, data can be respectively loaded (118) in the flash memory 112 and in the flash memory 113 at the same time, and the data operation can be performed (119) on the flash memory 112 and the flash memory 113 at the same time.

0048Complete data, which is supposed to be recorded in an entire flash memory unit comprised of the flash memories 112 and 113, is obtained by summing up the data respectively loaded in the flash memories 112 and 113.

0049In an interleaved manner, a plurality of flash memories share a data line with one another. Specifically, in the case of performing multiple write operations, data is loaded in a first flash memory, and then other data is loaded in a second flash memory while loading data in the first flash memory.

0050Referring to <figref idref="f0007">Figure 6A</figref>, which illustrates a typical interleaved system using one or more flash memories, two flash memories 121 and 122 and a device driver 123, which controls the two flash memories 121 and 122, share a data line 124 with one another. The flash memories 121 and 122 use separate control lines, i.e., the flash memories 121 and 122 use control lines 125 and 126, respectively.

0051Referring to <figref idref="f0007">Figure 6B</figref>, which illustrates the operation of the typical interleaved system of <figref idref="f0007">Figure 6A</figref>, a control signal, including a data computation command and an address at which a first data operation is to be performed is transmitted (127a) to, for example, the first flash memory, data is loaded (128a) in the first flash memory, and the first data operation is performed (129a) on the first flash memory. While the first data operation is being performed (129a) on the first flash memory, another control signal, including a data computation command and an address at which a second data operation is to be performed, is transmitted (127b) to, for example, the second flash memory, another data is loaded (128b) in the second flash memory, and the second data operation is performed (129b) on the second flash memory.

0052A data management apparatus according to an exemplary embodiment of the present invention will now be described more fully with reference to <figref idref="f0008">Figure 7</figref>. The data management apparatus can guarantee the stability of data stored in a plurality of flash memories and can efficiently deal with defective blocks in each of the flash memories. Referring to <figref idref="f0008">Figure 7</figref>, the data management apparatus includes a plurality of flash memories, i.e., flash memories 210, 220, and 230, a device driver 300, which controls the operation of each of the flash memories 210, 220, and 230, and a controller 400, which transfers data stored in a defective block in any of the flash memories 210, 220, and 230 to a non-defective block in a corresponding flash memory.

0053The data management apparatus according to the exemplary embodiment of the present invention will now be described by taking examples of a multi-channel system using plural flash memories and an interleaved system using one or more flash memories.

0054Referring first to <figref idref="f0009">Figure 8</figref>, flash memories 510 and 520 include virtual block management areas 511 and 521, respectively, spare areas 512 and 522, respectively, and data areas 513 and 523, respectively. Each of the virtual block management areas 511 and 521 includes mapping information of defective blocks in a corresponding flash memory. Each of the spare areas 512 and 522 includes substitute blocks, to which data stored in the defective blocks in the corresponding flash memory are respectively transferred. In each of the data areas 513 and 523, predetermined data operations are executed.

0055In the multi-channel approach, a data operation can be performed in parallel on the flash memories 510 and 520. Thus, if data exists in a block 513a of the flash memory 510, data also exists in a block 523a of the flash memory 520 that has the same offset value as the block 513a.

0056If a defect occurs in a block of one of the flash memories 510 and 520 (hereinafter referred to as a first flash memory), the controller 400 of the data management apparatus of <figref idref="f0008">Figure 7</figref> transfers data stored in the defective block of the first flash memory to a block in the spare area (512 or 522) of the first flash memory.

0057Thereafter, the controller 400 also transfers data, which is stored in a block of the other flash memory (hereinafter referred to as a second flash memory) that has the same offset value as the defective block of the first flash memory, to a block in the spare area of the second flash memory.

0058This is because the data stored in the defective block of the first flash memory may cause data loss by adversely affecting the data stored in the block of the second flash memory having the same offset value as the defective block of the first flash memory, due to the characteristics of the multi-channel approach.

0059Alternatively, flash memories 510 and 520 include virtual block management areas 511 and 521, respectively, spare areas 512 and 522, respectively, and data areas 513 and 523, respectively. Each of the virtual block management areas 511 and 521 includes mapping information on defective blocks in a corresponding flash memory. Each of the spare areas 512 and 522 includes substitute blocks, to which data stored in the defective blocks in the corresponding flash memory are respectively transferred. Predetermined data operations are executed in each of the data areas 513 and 523.

0060In addition, as shown in <figref idref="f0010">Figure 9</figref>, the controller 400 forms an upper block 530 by combining together a block 510a of the flash memory 510 and a block 520a of the flash memory 520, which have the same offset value.

0061Here, as shown in <figref idref="f0011">Figure 10</figref>, the virtual block management areas 511 and 521 include upper block management areas 511a and 521a, respectively, and defective block management areas 511b and 521b, respectively. Each of the upper block management areas 511a and 521a includes information on the upper block 530. Each of the defective block management areas 511b and 521b is comprised of a mapping table that respectively maps defective blocks in the data area of a corresponding flash memory with non-defective blocks in the spare area of the corresponding flash memory.

0062Thus, the controller 400 performs a data operation, which is supposed to be sequentially performed on the block 510a of the flash memory 510 and on the block 520a of the flash memory 520, on the upper block 530 by referencing the information on the upper block 530 stored in each of the upper block management areas 511a and 521a. Obviously, it is more convenient to perform the data operation on the upper block 530 than to perform the data operation on the block 510a of the flash memory 510 and then on the block 520a of the flash memory 520.

0063In this case, according to the interleaved manner, if a defect occurs in a block of one of the flash memories 510 and 520 (hereinafter referred to as first flash memory) data stored in the defective block of the first flash memory is transferred to a non-defective block in the spare area (512 or 522) of the first flash memory.

0064Then, an upper block is generated by combining the non-defective block in the spare area of the first flash memory with a predetermined block of the other flash memory (hereinafter referred to as second flash memory).

0065As described above, information on the non-defective block in the spare area of the first flash memory and the predetermined block of the second flash memory, which forms the upper block together with the non-defective block in the spare area of the first flash memory, is stored in each of the upper block management areas 511a and 521a.

0066Thus, a data operation, which is supposed to be performed on the upper block comprised of the defective block of the first flash memory and the predetermined block of the second flash memory, can be performed on the upper block comprised of the non-defective block in the spare area of the first flash memory and the predetermined block of the second flash memory by referencing the information stored in each of the upper block management areas 511a and 521a.

0067A data management method of a system using one or more flash memories, according to an exemplary embodiment of the present invention will be described more fully.

0068Referring to <figref idref="f0013">Figure 12</figref>, in operation S110, it is determined whether each of the flash memories in the system has initial defective blocks.

0069Here, the initial defective blocks are defective blocks detected before a flash memory is shipped out of the factory. In operation S120, a mapping table is generated by identifying the initial defective blocks in each of the flash memories in the system.

0070The mapping table matches the initial defective blocks in the flash memories in the system with non-defective blocks in spare areas of the respective flash memories and is stored in a virtual block management area in each of the flash memories so that a data operation, which is supposed to be performed on the initial defective blocks of the corresponding flash memory, can be performed on the non-defective blocks in the spare area of the corresponding flash memory.

0071Referring to <figref idref="f0014">Figure 13</figref>, reference numerals 631 and 632 denote initial defective blocks generated in a data area 630.

0072Specifically, the initial defective blocks 631 and 632 are respectively mapped with non-defective blocks 621 and 622 of a spare area 620 so that a data operation can be performed on the non-defective blocks 621 and 622, rather than on the initial defective blocks 631 and 632.

0073A mapping table that respectively maps the initial defective blocks 631 and 632 with the non-defective blocks 621 and 622 is stored in a virtual block management area 610.

0074The mapping table may respectively match addresses of the non-defective 621 and 622 with addresses of the initial defective blocks 631 and 632, as shown in <figref idref="f0015">Figure 14A</figref>. Alternatively, the mapping table may respectively match offset values assigned to the non-defective blocks 621 and 622 with the addresses of the initial defective blocks 631 and 632, as shown in <figref idref="f0015">Figure 14B</figref>.

0075In operation S130, a user issues a request for performing a data operation on a predetermined or current block of one of the flash memories (hereinafter referred to as first memory). In operation S140, it is determined whether the predetermined block is an initial defective block by determining whether the predetermined block is included in the mapping block.

0076In operation S150, if the predetermined block turns out to be an initial defective block, a data operation is performed on a non-defective block in a spare area of the first flash memory, rather than on the predetermined block.

0077In operation S160, if the predetermined block turns out to be a non-defective block, the data operation is performed on the predetermined block. In operation S170, it is determined whether a defect has occurred in the predetermined block in the process of performing the data operation on the predetermined block.

0078If a defect has occurred in the predetermined block while performing the data operation on the predetermined block, then in operation S180 the predetermined block is determined to be a run-time defective block.

0079In operation S190, the predetermined block is registered with the mapping table so that it can be matched with a non-defective block in the spare area of the first flash memory.

0080In operation S200, data stored in the predetermined block is transferred to the non-defective block in the spare area of the first flash memory. In operation S210, a data operation is performed on the non-defective block in the spare area of the first flash memory, rather than on the predetermined block.

0081If the system is an interleaved system, the data operation is performed on an upper block, which is comprised of the non-defective block in the spare area of the first flash memory and a block in the other flash memory that has the same offset value as the non-defective block in the spare area of the first flash memory.

0082A method of transferring data stored in a defective block in each flash memory of a system to a non-defective block in a spare area of a corresponding flash memory will now be described in further detail.

0083Referring to <figref idref="f0016">Figure 15</figref>, in operation S311, data stored in a defective block in one of the flash memories (hereinafter, referred to as first flash memory) is transferred to a non-defective block in a spare area of the first flash memory.

0084In operation S312, data, which is stored in a block of the other flash memory (hereinafter, referred to as second flash memory) that has the same offset value as the defective block in the first flash memory, is also transferred to a non-defective block in a spare area of the second flash memory.

0085Specifically, referring to <figref idref="f0016">Figure 16</figref>, flash memories 710 and 720 include data areas 713 and 723, respectively. When a defect occurs in a block 713a in the flash memory 710, data stored in the defective block 713a is transferred to a non-defective block 712a in a spare area 712 of the flash memory 710.

0086A mapping table that matches the defective block 713a with the non-defective block 712a in the spare area 712 is stored in a virtual block management area 711.

0087Given that in the multi-channel system, a data operation is performed in parallel, data, which is stored in a block 723a of the flash memory 720 that has the same offset value as the defective block 713a of the flash memory 710, is also transferred to a block 722a in a spare area 722 of the flash memory 720.

0088In addition, a mapping table that matches the block 723a in the data area 723 with the block 722a in the spare area 722 is stored in a virtual block management area 721.

0089Alternatively, referring to <figref idref="f0017">Figure 17</figref>, in operation S321, data stored in a defective block in one of the flash memories (hereinafter referred to as first flash memory) is transferred to a non-defective block in a spare area of the first flash memory.

0090In operation S322, an upper block is generated by combining the non-defective block in the spare area of the first flash memory with a block of the other flash memory (hereinafter, referred to as second flash memory) having the same offset value as the defective block of the first flash memory.

0091Specifically, referring to <figref idref="f0017">Figure 18</figref>, flash memories 810 and 820 have no defective blocks. Blocks 813a and 823a of the flash memories 810 and 820, which have the same offset value, are integrated into an upper block 830. Information on the upper block 830 is stored in virtual block management areas 811 and 821 of the flash memories 810 and 820.

0092Referring to <figref idref="f0018">Figure 19</figref>, if a defect occurs in the block 813a of the flash memory 810, data stored in the block 813a is transferred to a non-defective block 812a in a spare area 812 of the flash memory 810.

0093Thereafter, the non-defective block 812a in the spare area 812 of the flash memory 810 and the block 823 of the flash memory 820 are integrated into an upper block 830.

0094Information on the upper block is stored in the virtual block management areas 811 and 821 of the flash memories 810 and 820.

0095While the data management apparatus and method of a flash memory have been described with reference to the illustrative embodiments and drawings, it is to be appreciated that the above described embodiment is for purposes of illustration only and not to be construed as a limitation of the invention, and all variations and equivalents which fall within the range of the claims are intended to be embraced therein.

0096As described above, the data management apparatus and method according to the present invention have the following advantages.

0097First, it is possible to efficiently prevent the performance of a system using one or more flash memories from deteriorating due to defective blocks therein.

0098Second, it is possible to provide a system with an optimal data management method by using various methods depending on how the system manages data stored in each of the flash memories when dealing with defective blocks in each of the flash memories.

0099Although a few preferred embodiments have been shown and described, it will be appreciated by those skilled in the art that various changes and modifications might be made without departing from the scope of the invention, as defined in the appended claims.

0100All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

0101Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

0102The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.