Circuit for power factor correction in switching power supplies, chargers and the like

The present invention relates to a circuit for power factor correction for Switching power supplies, chargers and the like, in particular for use in a Truck.

If a non-sinusoidal current drawn from the 230 V network, thus causing a high Harmonic content increased power loss, for example, in the transformer stations. This power loss must ultimately generated by the power plants in addition to and in the Power can be fed. The law requires the standard DIN EN 6100-3-2 for electromagnetic compatibility (EMC), that during the removal of non-sinusoidal Current power factor correction (PFC = Power Factor Correction) to has done.

Due to legal regulations are a variety of different circuits Known for power factor correction. A critical factor in the circuits for power factor correction is occurring in the circuit power dissipation, the is composed of the on-state losses and switching losses.

The invention has the object of providing a circuit for power factor correction provide that at a possible simple and robust control only one low power dissipation has.

According to the invention the task by a circuit having the features of Claim 1 dissolved. Advantageous embodiments of the circuit according to the invention form the subject matter of the subclaims.

The inventive circuit has a bridge circuit, the four in two Half-bridge-connected diodes having. Here, as a half-bridge one Part of the bridge circuit referred, which the terminals of the bridge to the contacts the diagonal links. (In Fig. 1 form D2 and D4 a first half bridge and D1 D3 and the second half bridge.)

In a first half-bridge are parallel to the two switching transistors diodes connected. Here preferably a diode and a switching transistor respectively form a MOSFET transistor. Two coils are each a between the terminals AC voltage source and two terminals of the bridge circuit connected. Diagonally in the bridge circuit is a capacitor connected to the energy storage serves. The diagonal connection of the first half-bridge, so the half-bridge, which is provided with the switching transistors is grounded. The inventive Circuit arrangement, the power dissipation is reduced by 40% or more be without the effort to control the MOSFET switching transistors located significantly increased.

preferably takes place for the inventive circuit that control via a Control, which comprises a half-wave detector to the control depending on make the half-shafts.

was to better understand the circuit and its control between a charging and a discharging of the coil distinguished with the Discharging one of the switching transistors in accordance with a predetermined duty ratio is driven. During charging, the coil includes one of the switching transistors during a first half-wave such that via the diode to the second Switching transistor is a closed circuit to the main terminals is present. While the subsequent half-wave includes the second switching transistor such that a Circuit with the AC power source through the diode of the first switching transistor closed is.

During the unloading of the coil, a first half-wave during a closed circuit via a first diode in the second half bridge - in the Half bridge without switching transistor - the bridge diagonal and a diode of the first Half bridge made. In the second half-wave is a closed circuit through the second diode in the second half bridge, the bridge diagonal and a Diode front in the first half bridge. The controller controls, in this embodiment a first switching transistor with a predetermined cycle for power factor correction to when the power circuit via the diode of the other switching transistor closed is.

The above circuit may be used as a circuit for power factor correction having be construed half a synchronous rectifier.

In a particularly preferred development of the circuit according to the invention are also in the second half bridge two switching transistors in parallel with the diode connected. This circuit can be used as a circuit for power factor correction having be regarded a complete synchronous rectifier.

Preferably, the control of this circuit is carried out during a charging operation of the Coil by a first switching transistor in one of the half-bridge during a first Includes half wave such that via the other diode in the half-bridge, a closed Circuit with the AC terminals is present. During the other Half cycle of the second switching transistor is closed in the half-bridge such that on the other diode in the half-bridge is a closed circuit to the main terminals present.

During the unloading of the coil, a first half-wave during a closed circuit through one of the diodes in one of the half-bridge, the bridge diagonal and one of the diodes in the other half-bridge closed. In the following second half-wave, the closed circuit via the bridge diagonal and the other two diodes closed.

When switching transistors MOSFETs are preferably provided.

The control is in the configuration with four MOSFETs preferably by a driven first MOSFET with a predetermined timing for power factor correction , when the circuit via the diode of the other MOSFET in the half-bridge is controlled, one of the MOSFETs in the other half-bridge to Reducing the drain-source voltage is inverted with a predetermined clock is driven.

Preferably, the coils have the same windings and are coupled to each other, said windings have the same resistance and the same inductivity.

The inventive circuit will now be based on two Ausfiihrungsbeispielen explained in more detail. It shows:<dl tsize="6"><dt>Fig. 1</dt><dd>a basic circuit diagram of a PFC circuit with half synchronous rectifier, </dd><dt>FIG. 2</dt><dd>a circuit diagram in detail,</dd><dt>Fig. 3</dt><dd>a basic circuit diagram of a PFC circuit with complete synchronous rectifier,</dd><dt>Fig. 4</dt><dd>a diagram in detail of the circuit of FIG. 3,</dd><dt>Fig. 5</dt><dd>a PFC circuit according to the prior art, and</dd><dt>Fig. 6</dt><dd>a disturbance model to the PFC circuit according to the invention.</dd></dl>

. To explain the circuit of Figure 5 will first be explained: the circuit having a rectifier bridge 10, in which the diodes D1 to D4 arranged. D1 and D3 and D2 and D4 in this case each form a half-bridge. The half-bridge are connected to a power supply to the terminals P and N. The diagonal connection the rectifier bridge between the diodes D2 and D4 in a Half-bridge is 12 to ground. The second diagonal connection between the diodes D1 and D3 is connected with a storage or booster inductor 14 (L1). Behind the Throttle 14 is a booster diode 5 in the forward direction in an intermediate circuit connected. The intermediate circuit has a parallel capacitor 16 (C1) and a switching transistor 18 (T1). The switching transistor 18 is connected via a shunt 20 to Mass connected.

The control of the switching transistor 18 via a controller 20, which the Transistor 18 depending on the power factor correction to be carried out with a pulse-width modulated clock signal switches.

During a charging operation of the storage inductor, the current flows during a positive half-wave of the network port P via diode D1 through the coil L1 and transistor T1 back to diode D2 into the net N. A negative half wave flows Current through the diode D3, the coil 14, the transistor T1 and the diode D4 Reset for mains connection P.

In a discharging operation of the coil 14 flows in a positive half-wave of the current P from the mains through diode D1 and L1 via diode D5 and through the capacitor 16 back via the diode D5 to the network in the terminal N. For the negative half-wave the current flows through the diode D3, the coil L1, diode D5, capacitor C1 and diode D4 back to the terminal P. The discharging functions depends on the duty cycle the switching transistor 18, since switched transistor 18 of the power after the Coil 14 bypassing Booster diode D5 and intermediate circuit capacitor C1 can flow back.

The DC voltage is applied to the circuit to, for example in Fig.16. The duty cycle determined in this circuit, the harmonic content and thus the power factor.

The losses result in this circuit than the power loss from the state losses and in addition the switching losses of three active semiconductor components (D1, T1 and D2 or D1, D5 and D2) and the additional resistors in the circuit.

Fig. 1 shows a bridge rectifier including diodes D1 to D4. The switching transistors T1 and T2 are connected in parallel with the diodes D2 and D4. In the bridge diagonal is connected to a resistor R3, a capacitor C1. The diagonal connection in the half-bridge D2, D4, in which the switching transistors are connected in D1 and D2, is grounded. The lines to the bridge circuit, two windings of a Storage or booster inductor L1 connected with their windings L1_1 and L1_2.

The structure has, for example, two MOSFET switch transistors T1 and T2, as well as two diodes D1 and D2, which may also be replaced by a double diode. Further, in the circuit, the memory and booster inductor L1 and the Memory circuit capacitor C1 is provided as an energy store.

The storage inductor L1 is comprised of two separate windings and L1_1 L1_2 with the same total resistance and the same total inductance as already was described for the circuit in FIG. 5. The interpretation takes place the throttle Consequently, as in the standard circuit.

. The operation of the circuit of Figure 1 can be described as follows:<ul><li>Charging the storage choke: during a positive half-wave flows Power from the mains via P L1_1 and transistor T1 back through the diode D2 and L1_2 to the mains N. For the negative half cycle, the current flows from Mains connection N on L1_2 and transistor T2 back through the diode D4, the associated with the transistor T1 back to the mains connection T.</li><li>During the discharging of the storage inductor current flows during positive half-wave of the network port P via the coil through the diode D1 L1_1 and capacitor C1 returns through the diode D2 and L1_2 back on Power Supply N. In the negative half cycle of the current through the mains connection N flows about L1_2 via the diode D3 and the capacitor C1 returns through the diode 4 and L1_1 on Power Supply P.</li></ul>

Fig. 2 shows a concrete embodiment of the circuit with a controller 22 to which abut on the terminals 24 and 26 values ​​of the mains voltage, through the outputs 28 and 30, the switching transistors T1 and T2 connected. In 32, the voltage value is from to DC. When controlling both switching transistors switch T1 and T2 on the minus potential or to ground. The MOSFET, which is being used as a diode, receives a high signal at the gate over the entire Half-wave, while the other MOSFET in the predetermined pulse width modulated Clock controller is switched 22nd Over the next half-wave is applied to the gate the other MOSFET to the high signal, so that this MOSFET used as a diode, is, and the other MOSFET is switched clocked. In the drive 22 this only a half-wave detector and logic required. The cooling surfaces can be reduced and the power per unit volume increases. If you compare the power dissipation of the described under Fig. 5 standard PFC circuit with a Booster diode, this reduces the power dissipation to 56% of the standard solution. Known in the art is also a power factor correction circuit without booster diode D5, the loss of power may already be reduced to 67% of the standard solution, but still well above the solution proposed in FIG. 2.

Fig. Figure 3 shows schematically the structure of a power factor correction circuit with a complete synchronous rectifier with four switching transistors T1 to T4 in a Bridge circuit behind the storage or booster inductor L 1 with its windings L1_1 and L1_2. The intermediate circuit capacitor C1 with the shunt resistor R1 is connected in the bridge diagonal.

The charging process of the storage inductor is as described above, wherein again no current flows through the bridge diagonal. In discharging flows of Current from the power supply P via L1_1 through the diode D1 and capacitor C1 back to diode D2 and L1_2 on Power Supply N. In the negative half wave the current flows from the power supply terminal N on L1_2, the diode D3 and the capacitor C1 back through the diode D4 and L1_1 toward the power supply P.

Fig. 4 shows an embodiment of the above circuit with a controller 34, at which the AC voltage values ​​applied in 36 and 38th The switching transistors T1 and T2 are controlled via the terminals 40 and 42, while the switching transistors are driven T3 and T4 via the terminals 44 and 46th The control 34 has two galvanically isolated driver arranged in the half-bridges Switching transistors. The control of the synchronous rectifier is carried out in the positive mains half-wave by diode of T2 is permanently switched on high and T1 is connected with the PWM clock. The booster diode T3 is pulse width modulated inverted clocked at the MOSFET, the voltage U_sd to reduce. In the negative half-cycle is T2 replaced with T1 and T3 with T4.

The power loss is reduced in this circuit at 45% of the FIG. 5 described standard circuit, said comparison for MOSFET transistors having lower on-state resistance (R_dson) Is considered.

In standard PFC model (Fig. 5) it can be seen that the mass of the MOSFETs in the positive half-wave at the network "N" and in the negative half cycle to "P" is due through the rectifier directly from the mains. The voltage swing of the DC - Booster throttle the drain - the MOSFETs always acts with the full intermediate circuit voltage to the Housing (SL-terminal). Since the drain terminal of a MOSFET, a relatively large Surface forms the heatsink, this results in a parasitic coupling capacitance to Housing or to the protective conductor. Since the switching speed of the transistors constantly increases and the Standard Model the full U_c = Intermediate circuit voltage of the capacitor effect, resulting in a high dv / dt of the drain voltage of T1 to the housing (for example, dv / dt = 400 V / 0.1 us = 4000 V / us).

Fig. Figure 6 shows a disturbance model to the PFC circuit of the present invention in which the 50 Drain to, for example, +200 V, 52 the source connected to, for example, -200 V and 54 a parasitic coupling resistor shows. 56 denotes the filter capacitors (Y capacitors), the housing with heat sink with the power connector Electrically bond.

In the disturbance model of FIG. 6 can be seen that the mass of the PFC circuit in Power-on state (that is, the charge phase, the inductor, for example, in the positive half wave) is approximately located on protective conductor potential. In the off state (in the discharge the throttle) migrates, the drain of T1 to the positive half DC link voltage and the ground (source of T1) to half the negative Intermediate circuit voltage. This results from the source voltage symmetrically distributed AC Booster throttle before the rectifier. This results in a half as large Drain voltage T1 for housing (eg du / dt = 200 V / 0.1 us = 2000 V / us). The Web filter expense is here reduced significantly.