Intelligent power system

FIELD OF THE INVENTION

0001The present invention relates generally to power systems and more particularly to a system which can detect and isolate failed segments and reconfigure the system to restore power.

BACKGROUND OF THE INVENTION

0002Conventional power distribution systems typically include multiple power sources and storage elements and are lcnown by those of reasonable skill in the art. Despite the relative simplicity and wide acceptance of this conventional power distribution architecture, the conventional architecture suffers from several disadvantages. With few exceptions, unregulated energy sources are incompatible with parallel connection to a common bus. One problem of the conventional approach is that the architecture requires power regulators to interface incompatible sources to the bus. If such unregulated sources such as batteries are connected to the common bus, the unregulated source with the highest voltage will back-feed other sources thereby generating circulating currents.

0003The magnitude of these currents depends on the voltage difference between the various sources and the total resistance of the current path. Because the source and bus resistances are low, the circulating currents will degrade system efficiency and may even damage components and wiring.

0004Another problem associated with this power system architecture is its susceptibility to single point failures. If the common bus, the load, or the output of a single voltage regulator is shorted, the whole system can be disabled. Still another problem associated with conventional power system architectures is the systems inability to control the power flow. Because there is only one bus that connects all loads and all power sources, this architecture does not allow delivering power to a section of the load from selected sources. The conventional architecture lacks flexibility, i. e. , failed elements or bus segments cannot be isolated and disconnected from the system.

0005<patcit id="pcit0001" dnum="US3515893A"><text>US 3,515,893</text></patcit> teaches a method of improving the stability of interconnected power systems. <patcit id="pcit0002" dnum="US5764099A"><text>US 5,764,099</text></patcit> teaches an integrated voltage regulating circuit useful in high voltage electronic encoders.

SUMMARY OF THE INVENTION

0006The invention is defined in the claims to which reference is now directed. A common power source subsystem and a plurality of power system subsystem components are fully interconnected to provide an intelligent power system. With such a configuration, the system is able detect and isolate failed segments of the power system and is reconfigurable to restore power.

BRIEF DESCRIPTION OF THE DRAWINGS

0007The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which: <ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">Figure 1</figref> is a block diagram of a conventional power system;</li><li><figref idref="f0002">Figure 2</figref> is a block diagram of the power architecture of the present invention;</li><li><figref idref="f0003">Figure 3</figref> is a block diagram of a common source element of the present invention;</li><li><figref idref="f0004">Figure 4</figref> is a block diagram of a subsystem element of the present invention;</li><li><figref idref="f0005">Figure 5</figref> is a block diagram of a single unregulated source embodiment of the present architecture;</li><li><figref idref="f0006">Figure 6</figref> is a block diagram of a three-regulator embodiment of the present invention;</li><li><figref idref="f0007">Figure 7A </figref>is a block diagram of a time-shared embodiment of the present architecture;</li><li><figref idref="f0007">Figure 7B </figref>is a timing diagram of the time-shared embodiment of <figref idref="f0007">Figure 7A</figref>;</li><li><figref idref="f0008">Figure 8</figref> is a block diagram showing an arrangement wherein three subsystems are operating from a single regulator in the time-shared mode;</li><li><figref idref="f0009">Figure 9</figref> is a timing diagram showing the time-shared mode of operation;</li><li><figref idref="f0010">Figure 10</figref> is a graph showing output voltage versus output current for a regulator of the present power system;</li><li><figref idref="f0011">Figure 11A</figref> is a block diagram showing an arrangement wherein two subsystems are operating from a single power source;</li><li><figref idref="f0011">Figure 11B</figref> is a timing diagram showing power delivery for the arrangement of <figref idref="f0011">Figure 11A</figref>;</li><li><figref idref="f0012">Figure 12A</figref> is a block diagram showing another arrangement wherein two subsystems are operating from a single power source;</li><li><figref idref="f0012">Figure 12B</figref> is a timing diagram showing power delivery for the arrangement of <figref idref="f0012">Figure 12A</figref>;</li><li><figref idref="f0013">Figure 13A</figref> is a block diagram showing an arrangement having multiple faults; and</li><li><figref idref="f0013">Figure 13B</figref> is a timing diagram showing power delivery for the arrangement of <figref idref="f0013">Figure 13A</figref>.</li></ul>

DETAILED DESCRIPTION OF THE INVENTION

0008The present invention comprises a new power system architecture that resolves the problems associated with conventional power systems and further provides important advantages not available with conventional power system architectures. Autonomous power systems have to satisfy conflicting requirements such as high density, low weight and volume, energy storage, continuous and reliable operation with partial damage, fault isolation and self-generating and restoring capabilities.

0009Referring now to <figref idref="f0001">Figure 1</figref>, a prior art power system architecture 1 is shown. This architecture 1 uses individual voltage regulators 10a - 10N to couple multiple power sources 20a - 20N to a common regulated bus 30. The regulated bus 30 is used to provide power to one or more loads 40a-40N. The regulators can be realized as voltage source regulators 10a - 10N to couple voltage sources 20a - 20N to the regulated bus 30, and also as storage regulators 50a - 50N to couple storage sources 60a - 60N to the regulated bus 30.

0010Referring now to <figref idref="f0002">Figure 2</figref>, a high-level block diagram of the presently disclosed power system 100 is presented. This architecture comprises a common power source and <b><i>m</i>*<i>n</i></b> interconnected subsystems 120. The number of connections between subsystems 120 and the common power source 110 is <b><i>m</i>*<i>n</i></b> (a source-dependent system). Each line between a subsystem 120 and the common power source 110 represents multiple power and signal connections. The number of interconnections between subsystems is <b><i>m</i>*<i>n -1</i></b> (a fully connected system). Each line between subsystems 120 in <figref idref="f0002">Figure 2</figref> represents multiple power and signal connections between the subsystems 120. Another version of this architecture includes multiple subsystems wired together and connected to the common power source as groups.

0011A block diagram of the common power source 110 is shown in <figref idref="f0003">Figure 3</figref>. The common power source 110 includes an unregulated voltage bus 112, a regulated voltage bus 114, Po power sources 116, Ro regulators 118, So bus stabilizers 111, Eo energy storage units 113, sensors 115 and a controller 117. A power source 110 may be realized as a battery, a generator, a fuel cell, a solar cell or the like. A stabilizer 111 is similar to a regulator in that a stabilizer is a power conversion device wherein one voltage level is converted to another voltage level. An energy storage device 113 may be realized as a battery, flywheel, capacitor, inductor or similar type device. All elements of the common power source except the controller 117 and sensors 115 are connected to one or both buses through controlled switches 119. The switches 119 may be electronic solid state, vacuum tube, or electro-mechanical devices. The output of each regulator 118 is connected to regulated buses of all subsystems as well as the regulated bus 114 of the common source. As an alternative, the common regulated bus 114 may be connected to one or more regulated buses of individual subsystems. The subsystem-to-subsystem control signals interconnect may be the same interconnect (electrical (wire-based), optical, infrared, RF, etc.) used for interconnecting a subsystem controller to a power source controller, although other embodiments may use a different interconnect for the subsystem-to-subsystem control signals interconnect than the subsystem-to-power source control signals interconnect.

0012Referring now to <figref idref="f0004">Figure 4</figref> a block diagram of a subsystem 120 (subsystem 1,1 of <figref idref="f0002">Figure 2</figref> in this example) is shown. The subsystem includes a regulated voltage bus 122, an unregulated voltage bus 123, PR regulated power sources 127 (only one shown in <figref idref="f0004">Figure 4</figref>), R regulators 126 (only one shown in <figref idref="f0004">Figure 4</figref>), S bus stabilizers 129, E energy storage units 128 (only one shown in <figref idref="f0004">Figure 4</figref>), D loads 121, sensors 124 and a subsystem controller 125. All subsystem elements except the controller 125 and sensors 124 are connected to one or both buses through controlled switches 130. Each regulated power source 127 is connected to regulated buses of all other subsystems as well as to the internal regulated bus 122.

0013The presently disclosed architecture provides several advantages not available from conventional power systems. A system comprising incompatible sources can operate without regulators. One way of achieving this is to activate only a single power source at any moment in time. Another method is to break connections between subsystems that contain power sources using controlled switches and operate all sources simultaneously (completely independent system). The presently disclosed architecture can also use switches to operate power sources in a sequential way or switching between the two modes described above. Thus, the new approach applies to systems that contain both regulated and unregulated buses.

0014Because the system comprises self-sufficient interconnected subsystems as well as the common power source, the presently disclosed power system is not susceptible to single point failures.

0015Each subsystem or element of the new system is connected to all other elements and to the common energy source and storage. Controllers can direct power flow from one subsystem to another subsystem, from the central source to any number of subsystems, and from any number of subsystems to storage elements. This control is accomplished by a controller opening and/or closing the appropriate switches to provide the desired configuration. Each controller is in communication with a respective sensor and further each controller is in communication with each other controller.

0016In the event of a failure, the controllers, by way of the sensors, will detect failed elements or bus segments. The controllers then isolate the failed element or bus segment and re-configure the distribution to restore power by activating and/or deactivating the appropriate switches. Constant monitoring of the power flow through bus segments allows the controller to determine their condition and identify failures. For any waveforms of voltage V(t) and current I(t), the instantaneous power at the output of the power source or at the load fed by a bus segment is expressed as follows: <maths id="math0001"><math display="block"><mi mathvariant="normal">P</mi><mo mathvariant="normal">=</mo><mn mathvariant="normal">1</mn><mo mathvariant="normal">/</mo><mi mathvariant="normal">T</mi><mspace width="1em" /><mo mathvariant="normal">∫</mo><mi mathvariant="normal">V</mi><mfenced><mi mathvariant="normal">t</mi></mfenced><mo>⁢</mo><mi mathvariant="normal">I</mi><mfenced><mi mathvariant="normal">t</mi></mfenced><mspace width="1em" /><mi>dt for the integration time interval from</mi><mspace width="1em" /><mn mathvariant="normal">0</mn><mspace width="1em" /><mi>to T</mi></math><img file="EP1559178B1_D0001.tif" /></maths>

0017This expression can be simplified for specific waveforms. For example, in the case of sinusoidal voltage and current the power is: <maths id="math0002"><math display="block"><msub><mi mathvariant="normal">P</mi><mi>SINE</mi></msub><mo mathvariant="normal">=</mo><msub><mi mathvariant="normal">V</mi><mi>RMS</mi></msub><mo>⁢</mo><msub><mi mathvariant="normal">I</mi><mi>RMS</mi></msub></math><img file="EP1559178B1_D0002.tif" /></maths>

0018One way to identify failed elements or bus segments is to compare the power supplied by a source with the power consumed by a load and voltage at the source with voltage at the load. For example, if a system consists of one source and multiple loads the power balance for lossless distribution is expressed as follows: <maths id="math0003"><math display="block"><msub><mi mathvariant="normal">P</mi><mi>SOURCE</mi></msub><mo mathvariant="normal">=</mo><mi mathvariant="normal">Σ</mi><mo>⁢</mo><mfenced><msub><mi mathvariant="normal">P</mi><mrow><mi>LOAD</mi><mo>⁢</mo><mn mathvariant="normal">1</mn></mrow></msub><mo mathvariant="normal">+</mo><msub><mi mathvariant="normal">P</mi><mrow><mi>LOAD</mi><mo>⁢</mo><mn mathvariant="normal">2</mn></mrow></msub><mo mathvariant="normal">+</mo><mo mathvariant="normal">⋯</mo><mo mathvariant="normal">+</mo><msub><mi mathvariant="normal">P</mi><mi>LOADG</mi></msub></mfenced><mo mathvariant="normal">,</mo><mi>summing from</mi><mspace width="1em" /><mn mathvariant="normal">1</mn><mspace width="1em" /><mi>to G</mi></math><img file="EP1559178B1_D0003.tif" /></maths> Where P_SOURCE is power at the source P_LOAD1 through P_LOADG is power at the load

0019Assuming that the loads are not regenerative, power at the source always equals to the total power consumed by the loads. If the bus segment feeding one load failed, the power balance equation would not hold. To eliminate the possibility that the load itself failed, the controller would measure the voltage at the load terminals. If the load voltage equals to the source voltage and the load does not draw its share of power, then the load has failed. If the load voltage does not equal to the source voltage (for lossless distribution) and the load does not draw its rated power, then the bus segment has failed.

0020Referring now to <figref idref="f0005">Figure 5</figref>, an application involving an unregulated system 200 is shown. The system comprises two subsystems 120a and 120b, and a common power source 110. All power sources in this system are unregulated and are therefore incompatible with parallel operation. For the mode of operation shown in <figref idref="f0005">Figure 5</figref>, the common power source 110 and source in the subsystem 2 are disconnected and both loads operate from the single power source located in the subsystem 1.

0021The reliability of the new architecture is based upon the power transfer between components through the interconnect. Because power flows through multiple conductors and the system contains multiple sources, the failure of any single element (or possibly multiple elements) does not disrupt operation of the power system.

0022Conductor 1 provides power from subsystem 120a to energy storage unit 113 of the common power source 110. Additionally, conductors 2 and 3 provide power from subsystem 120a to energy storage unit 113 of the common power source 110. Conductors 3 and 4 also provide power from subsystem 120a to subsystem 120b unregulated bus 123, load 121b and energy storage device 128. Conductors 1, 2 and 6 also provide power from subsystem 120a to subsystem 120b unregulated bus 123, load 121b and energy storage device 128.

0023The power source 210 is disconnected from the common bus of Common Power Source 110 by opening switch 211. Similarly, the power source 116b of subsystem 120b is also disconnected from the unregulated bus by opening switch 212 and is further disconnected from the unregulated bus of subsystem 120a by the opening of switch 213. In order to permit power source 116a of subsystem 120a to provide power to load 121a of subsystem 120a and also to load 121b of subsystem 120b switches 214-218 of subsystem 120a are closed as are switches 219, 219a and 220 of subsystem120b. Power from power source 116a flows from subsystem 120a to common power source 110 through conductor 1 of the system interconnect. Power from power source 116a also flows from subsystem 210a to subsystem 120b through conductor 3, 4 and 6 of the system interconnect. Power also flows from power source 116a through common power source 110 and to subsystem 120b through conductor 2 of the system interconnect. With such an arrangement power source 116a is able to provide power to load 121a and also to load 121b.

0024Other modes of operation supported by the present power system architecture include a self-sufficient mode of operation wherein both subsystems are disconnected from each other and the common source, a mode wherein operation is from the common power source, a node wherein operation is from the power source in the second subsystem, and a time-shared mode of operation wherein some or all of the power sources are turned on sequentially.

0025Referring now to <figref idref="f0006">Figure 6</figref>, a power system 300 comprising a common power source 110 feeding two subsystems 120a and 120b is shown. Subsystem 120a includes one main regulator 310 and one redundant regulator 320 with each regulator capable of providing full power for either subsystem 120a or 120b. <figref idref="f0006">Figure 6</figref> illustrates one mode of operation when regulator 330 of subsystem 120b has failed and regulator 320 in subsystem 120a continuously provides power to the subsystem 120b.

0026Switches 340 and 341 of common power source 110 are closed, switches 333 and 334 of subsystem 120a are open while switches 335 through 339 of subsystem 120a are closed. In subsystem 120b, switches 331 and 332 are open while switches 342, 443 and 334 are closed. With this arrangement power from power source 210 of common power source 110 is provided to regulator 310 and regulator 320 of subsystem 120a. The regulators then provide regulated power to the load 121a of subsystem 120a and to the load 121b of subsystem 120b.

0027This example demonstrates the ability of the present power system architecture to reduce the total number of regulators to three and maintain redundancy for both subsystems. A conventional solution calls for connecting buses 1 and 2 in parallel, but if the voltage V1 (bus 1) is different from the voltage 2 (bus 2) this approach will not be feasible. In this case, the buses have to be separate and redundant operation of subsystem 2 will require an additional regulator (four total).

0028<figref idref="f0007">Figure 7A</figref> shows the same system as <figref idref="f0006">Figure 6</figref>, but operating under a different set of conditions. This system is labeled 300'. In this example, two of the regulators are out of service (regulators 310 and 330 have failed, while regulator 320 remains operational). As shown in <figref idref="f0007">Figure 7A</figref>, the power system overcomes these failures by operating on a time-shared basis. As shown in the timing diagram of <figref idref="f0007">Figure 7B</figref>, regulator 320 feeds the subsystem 120a for time interval T1 and feeds subsystem 120b for time interval T2. This mode does not have to be periodic and controllers can modify both time intervals as required. Similarly to the previous case, if the input voltage for the two subsystems is different, the subsystem 120a controller can vary the output of regulator 330 to satisfy each subsystem's requirements.

0029In the system 300' switches 340 and 341 of the common power source are closed. In subsystem 102a switches 333, 336 and 338 are opened, switch 339 is closed and switches 334, 335 and 337 are cycled between the open and closed positions. In subsystem 120b, switches 331, 332 and 342 are opened while switches 343 and 344 are cycled. As shown in <figref idref="f0007">Figure 7B</figref>, power is delivered to subsystem 120a for a predetermined period of time, then to subsystem 120b for a predetermined period of time, and there is no overlap between the power delivery to the two subsystems. Switches 337 and 344 are closed and switches 334, 335 and 343 are opened to provide power to load 121a of subsystem 120a. Switches 337 and 344 are opened and switches 334, 335 and 343 are closed to provide power to load 121b of subsystem 120b. These switches 334, 335, 337, 343 and 344 are cycled in order to provide power on a time-shared basis to subsystem 120a and subsystem 120b.

0030<figref idref="f0008 f0009 f0010">Figures 8 through 10</figref> illustrate a method of using energy storage devices to feed pulsed loads. <figref idref="f0008">Figure 8</figref> shows a configuration 500 including three subsystems 120a, 120b and 120c that operate from a single regulator 510 while three other regulators 520, 530, and 540 are out of service. Also, as shown in graph 600 of <figref idref="f0009">Figure 9</figref>, loads for subsystems 120a and 120b draw pulsed power that exceeds the rated power of the regulator 510.

0031Even under these demanding conditions, the present power system architecture provides power on a time-shared basis to all loads if the following conditions are met:

0032Time intervals when one regulator is connected to a given subsystem do not overlap, <maths id="math0004"><math display="block"><mi mathvariant="normal">T</mi><mo mathvariant="normal">≥</mo><msub><mi mathvariant="normal">ΣT</mi><mi mathvariant="normal">a</mi></msub><mspace width="1em" /><mi>for the summation from a</mi><mo mathvariant="normal">=</mo><mn mathvariant="normal">1</mn><mspace width="1em" /><mi>to a</mi><mo mathvariant="normal">=</mo><mn mathvariant="normal">3</mn></math><img file="EP1559178B1_D0004.tif" /></maths>

0033Where T_a is the time interval when a subsystem is connected to the regulator and T is the repeatable time interval.

0034The average power P_reg delivered by the regulator does not exceed the total average power consumed by all loads or, for a lossless system: <maths id="math0005"><math display="block"><msub><mi mathvariant="normal">P</mi><mi>reg</mi></msub><mo mathvariant="normal">≥</mo><mfenced><mn mathvariant="normal">1</mn><mo mathvariant="normal">/</mo><mi mathvariant="normal">T</mi></mfenced><mo mathvariant="normal">*</mo><mo mathvariant="normal">∫</mo><mrow><mo mathvariant="normal">(</mo><mi mathvariant="normal">Σ</mi><mfenced><msub><mi mathvariant="normal">P</mi><mi mathvariant="normal">a</mi></msub><mfenced><mi mathvariant="normal">t</mi></mfenced></mfenced></mrow><mi>dt</mi></math><img file="EP1559178B1_D0005.tif" /></maths> for the interval of integration from t = 0 to t = T and the summation from a = 1 to a = 3

0035Where P_a(t) is the load power for a given subsystem load, a is the load number.

0036The system 500 operates as follows. Because load 511 of subsystem 120a requires more power than regulator 510 can deliver, the energy storage 512 provides the rest of the power. When the load 511 is turned off, the regulator 510 recharges the energy storage 512 during the remainder of the time interval T1.

0037When load 513 of subsystem 120b is turned on, the regulator is still connected to the subsystem 120a. Consequently, the energy storage unit 514 is feeding the subsystem 120b until the beginning of time interval T2. At this time, regulator 510 of subsystem 120a starts delivering power to load 513 and recharging the energy storage 514 of the subsystem 120b.

0038Subsystem 120c operates in a similar way. The only difference is that subsystem 120c has a constant load thereby its power demand never exceeds the rated power of the regulator 510. During time intervals T1 and T2 the energy storage unit 516 of subsystem 120c provides power to load 515. When regulator 510 is connected to subsystem 120c, it starts recharging the energy storage unit 516 and feeding load 515.

0039Similar to the previous described configurations, the pulsed load mode does not have to be periodic and controllers can modify all time intervals as needed as long as the conditions listed above are satisfied. Also, if the input voltage needed by subsystems is different, the subsystem controller can vary the output of the regulator to satisfy each system's requirements.

0040Referring now to <figref idref="f0010">Figure 10</figref>, a graph 700 showing the different modes of operation of the regulator is shown. The graph 700 shows a first mode of operation referred to as the voltage mode 710. As can be seen in the voltage mode of operation the voltage is nearly constant regardless of the output current. Output voltage versus current (VA) characteristic of the regulators also has constant power mode 720. In this mode the voltage varies directly opposite the current resulting in constant power over a range of voltages and currents. Additionally, the regulators have a constant current mode 730. In this mode the regulator provides a constant current value over a range of voltages. A foldback mode 740 is also shown. In foldback mode the regulator decrease the output current with increasing overload, reaching a minimum at short circuit. This minimizes internal power dissipation under overload conditions.

0041Referring now to <figref idref="f0011">Figure 11A</figref>, a system 800 is shown in a configuration wherein two subsystems 120a and 120b operate from a common power source. An additional unregulated power source 810 is incorporated in the subsystem 120a. If the rated power of unregulated power source 810 is sufficient to feed only one subsystem, time-sharing will allow operating both subsystems 120a and 120b in the event of a failure of the common power source.

0042Switch 801 of common power source 110 is closed, switch 813 is open and switches 802 and 803 are cycled. In subsystem 120a switches 805, 806 and 808 are closed while switches 807 and 804 are cycled. In subsystem 120b, switch 812 is closed while switches 809 and 811 are cycled. With this arrangement power from power source 810 of subsystem 120a is provided to regulator 820 at one time interval through switch 807. Further, power is delivered from power source 810 of subsystem 120a to regulator 830 of subsystem 120b via switch 804 during a second time interval.

0043As shown in <figref idref="f0011">Figure 11B</figref>, during time interval T1 the power source 810 delivers power to the subsystem 120a through the regulator 820 while the regulator 830 is disconnected from the system. As the time interval T2 begins, the regulator 820 is turned off and power starts flowing from power system 810 to the subsystem 120b through the regulator 830. This example shows a case when either load does not exceed the rated power of the source. If this condition is not satisfied, energy sources can be used to average peak power demands of the loads as described above with respect to <figref idref="f0008 f0009 f0010">Figures 8-10.</figref>

0044<figref idref="f0012">Figure 12A</figref> shows a system 900 in a configuration wherein two subsystems 120a and 120b are fed by a common power source 110. Unlike the system shown in <figref idref="f0011">Figure 11A</figref>, the power source 910 in this system generates regulated voltage and does not have a connection to the second subsystem 120b. Again, if the common source 920 fails, the power source 910 can feed both subsystems 120a and 120b on a time-shared basis.

0045Switch 901 of common power source 110 is closed, and switch 902 is open. Switch 904 of subsystem 120a is closed while switches 903 and 905 are cycled. In subsystem 120b, switch 908 is closed and switches 906 and 907 are cycled. With this arrangement power from power source 910 of subsystem 120a is provided to the load of subsystem 120a through switch 903 during a first time interval and power is delivered to subsystem 120b through switch 905 during a second time interval.

0046As shown in <figref idref="f0012">Figure 12B</figref>, during the time interval T1, power source 910 delivers power directly to the subsystem 120a bypassing the regulator 930 that is disconnected via switch 905 from the regulated bus 940 of subsystem 120a. During the time interval T2, the regulator 930 is connected to regulated bus 940 via switch 905 and converts its voltage V1 to the input voltage for the regulator 950 that feeds the second subsystem 120b. This mode of operation is particularly useful when one common source powers several subsystems that have different regulated bus voltages. To enable this mode of operation, the regulator 930 is bi-directional i.e. it is able to send power from the input to the output and vice versa. If either subsystem needs pulsed power, energy sources can be used to average peak power loads as described above.

0047Referring now to <figref idref="f0013">Figure 13A</figref>, an embodiment 1000 which demonstrates how the new architecture improves reliability and maintains operation in the presence of multiple faults is presented. In this example, a second failure disabled the regulator 1010, so neither power source 1020 nor regulator 1010 are in service. Under these conditions, the regulated power source 1030 feeds both subsystems 120a and 120b on a time-shared basis while the regulator 1040 is turned off via switch 1007.

0048Switches 1001 and 1002 of common power source 110 are open. Switch 1006 of subsystem 120a is closed, switch 1007 is open and switches 1003-1005 are cycled. In subsystem 120b, switch 1009 is open and switch 1008 is cycled. With this arrangement power from power source 1030 of subsystem 120a is provided to the load 121a of subsystem 120a via switches 1003 and 1005 during a first time interval and power is delivered to subsystem 120b via switch 1004 during a second time interval.

0049As shown in <figref idref="f0013">Figure 13B</figref>, during the time interval T1, the power source 1030 delivers power to the subsystem 120a. During the time interval T2, power source 1030 is switched from bus 1050 with voltage V1 to the bus 1060 with voltage V2. To enable this mode of operation, the source's output has to be programmable and its range shall include voltage V2. This example shows a case when either load does not exceed the rated power of the power source 1030. If this condition is not met, energy sources can be used to average peak power loads as described above with respect to <figref idref="f0008 f0009 f0010">Figures 8-10</figref>.

0050An intelligent power system has been described. The power system includes one or more common power sources and one or more subsystem components interconnected with the common power sources. With such a configuration, the system is able detect and isolate failed segments of the power system and is reconfigurable to restore power.

0051Having described preferred embodiments of the invention it will now become apparent to those of ordinary skill in the art that other embodiments incorporating these concepts may be used. Additionally, the software included as part of the invention may be embodied in a computer program product that includes a computer useable medium. For example, such a computer usable medium can include a readable memory device, such as a hard drive device, a CD-ROM, a DVD-ROM, or a computer diskette, having computer readable program code segments stored thereon. The computer readable medium can also include a communications link, either optical, wired, or wireless, having program code segments carried thereon as digital or analog signals. Accordingly, it is submitted that that the invention should not be limited to the described embodiments but rather should be limited only by the scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.