Two-layer film for next generation damascene barrier application with good oxidation resistance

Description of equivalent WO 2004033752 A2

0001TWO-LAYER FILM FOR NEXT GENERATION DAMASCENE BARRIER APPLICATION WITH GOOD OXIDATION RESISTANCE

BACKGROUND OF THE INVENTION

0003Field of the Invention

0004[0001] The invention relates to the fabrication of integrated circuits, more specifically to a process for depositing dielectric layers on a substrate, and to the structures formed by the dielectric layer. The invention further relates to a process for depositing barrier layers on a substrate, and to the structures formed by the barrier layers.

0005Description of the Related Art

0006[0002] Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35μm and even 0.18μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.

0007[0003] To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constants of less than 4.0) to also reduce the capacitive coupling between adjacent metal lines. Such low k materials include silicon oxycarbide deposited by a' chemical vapor deposition process and silicon carbide, both of which may be used as dielectric materials in fabricating damascene features.

0008[0004] One conductive material having a low resistivity is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.

0009[0005] One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.

0010[0006] One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, e.g., vias, and horizontal interconnects, e.g., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.

0011[0007] However, low k dielectric materials are often porous and susceptible to interlayer diffusion of conductive materials, such as copper, which can result in the formation of short-circuits and device failure. Furthermore, low k dielectric materials are often susceptible to oxidation. A dielectric barrier layer material is often disposed between the copper material and surrounding the low k material to prevent interlayer diffusion. However, traditional dielectric barrier layer materials, such as silicon nitride, often have high dielectric constants of 7 or greater. The combination of such a high k dielectric material with surrounding low k dielectric materials results in dielectric stacks having a higher than desired dielectric constant. [0008] Therefore, there remains a need for an improved process for depositing dielectric barrier layer materials with low dielectric constants and good resistance to oxidation for damascene applications.

SUMMARY OF THE INVENTION

0013[0009] Aspects of the invention generally provide a method for depositing a barrier layer having a low dielectric constant and a cap layer adjacent the barrier layer. In one aspect, the invention provides a method for processing a substrate including depositing a silicon carbide barrier layer on the substrate by introducing a processing gas comprising an organosilicon compound into a processing chamber, wherein the organosilicon compound has the formula SiH_a(CH₃)b(C₆H5)c, wherein a is 0 to 3, b is 0 to 3, and c is 1 to 4, and reacting the processing gas to deposit the barrier layer, wherein the barrier layer has a dielectric constant less than 4 and contains phenyl groups attached to silicon atoms, and depositing a silicon carbide cap layer on the barrier layer by introducing a second processing gas mixture comprising an oxygen-free organosilicon compound into the processing chamber, and reacting the second processing gas mixture to deposit the silicon carbide cap layer, wherein the silicon carbide cap layer has substantially no phenyl groups attached to silicon atoms.

0014[0010] In another aspect, a method is provided for processing a substrate including depositing a silicon carbide barrier layer on the substrate by introducing a first processing gas mixture comprising a first organosilicon compound into a processing chamber, wherein the first organosilicon compound has the formula SiH_a(CH₃)_b(C₆H₅)_c, wherein a is 0 to 3, b is 0 to 3, and c is 1 to 4, and reacting the processing gas to deposit the barrier layer, wherein the barrier layer has a dielectric constant of less than 4, and depositing a silicon carbide cap layer on the barrier layer by introducing a second processing gas mixture comprising a second organosilicon compound having the formula SiH_x(CH₃)_y(C₂H5)_z> wherein x is 1 to 3, y is 0 to 3, and z is 0 to 3 into the processing chamber, and reacting the second processing gas mixture to deposit the silicon carbide cap layer. BRIEF DESCRIPTION OF THE DRAWINGS

0015[0011] So that the manner in which the above aspects of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.

0016[0012] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

0017[0013] Figure 1 is a cross sectional view showing a dual damascene structure comprising a low k barrier layer and a low k dielectric layer described herein; and

0018[0014] Figures 2A-2H are cross sectional views showing one embodiment of a dual damascene deposition sequence of the invention.

0019[0015] For a further understanding of aspect of the invention, reference should be made to the ensuing detailed description.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

0021[0016] Aspects of the invention described herein refer to methods and precursors for depositing a silicon carbide barrier layer having a low dielectric constant. The silicon carbide barrier layer may also include hydrogen and may be doped with oxygen, nitrogen, boron, phosphorus, or combinations thereof, to improve film properties. Doped silicon carbide generally includes less than about 15 atomic percent (atomic %) or less of a dopant, such as oxygen, nitrogen, boron, phosphorus, or combinations thereof.

0022[0017] The silicon carbide barrier layer is deposited by reacting a processing gas including an organosilicon compound having the formula SiH_a(CH₃)_b(C₆H₅)_c, wherein a is 0 to 3, b is 0 to 3, and c is 1 to 4, in a plasma to form a dielectric layer comprising carbon-silicon bonds and a dielectric constant less than 4, preferably less than about 3.5. A dopant-containing material, such as oxygen (O₂) or a siloxane compound for oxygen doping, or borane (BH₃) for boron doping, may also be present during the deposition process.

0023[0018] It was unexpectedly and surprisingly discovered that depositing silicon carbide materials with an organosilicon compound having the formula SiH_a(CH₃)_b(C₆H₅)_c, wherein a is 0 to 3, b is 0 to 3, and c is 1 to 4, under the processing parameters described herein, produced a silicon carbide film having a dielectric constant of less than 4 with improved barrier layer properties, such as an interlayer diffusion resistance of about 100% greater than silicon carbide film produced by commercially available alkylsilane precursors, such as trimethylsilane (TMS). This is unexpected because it has been observed that phenyl groups increase the porosity of the deposited dielectric material, thereby reducing the interlayer diffusion resistance of the deposited dielectric material. In embodiments in which the barrier layers are deposited adjacent dielectric layers, the barrier layers are preferably deposited adjacent dielectric layers comprising silicon, oxygen, carbon, and hydrogen, which have a dielectric layer of less than about 4, such as less than about 3.

0024[0019] The organosilicon compounds used for barrier layer materials generally include the structure:

0025R¹

I

0027R-Si-R²,

I

0029R³ wherein R is a phenyl group, and R¹, R², and R³ are groups containing H, C, and/or Si. The organosilicon compound includes the formula SiH_a(CH₃)_b(C₆H₅)_c> wherein a is 0 to 3, b is 0 to 3, and c is 1 to 4, and a+b+c is equal to 4. Examples of suitable precursors derived from this formula include diphenylsilane, dimethylphenylsilane, diphenylmethylsilane, phenylmethylsilane, and combinations thereof. Preferably, b is 1 to 3 and c is 1 to 3. The most preferred organosilicon compounds for deposition as barrier layer materials include organosilicon compounds having the formula SiH_a(CH₃)b(C6H5)_c, wherein a is 1 or 2, b is 1 or 2, and c is 1 or 2. Examples of preferred precursors include dimethylphenylsilane and diphenylmethylsilane. The processing gas may also include an inert gas, such as argon (Ar), helium (He), neon (Ne), xenon (Xe), nitrogen (N₂), and combinations thereof.

0030[0020] The processing gas may further include compounds having Si-O-Si bonding groups, such as organosiloxane compounds, compounds having Si-N-Si bonding groups, such as silazane compounds, and combinations thereof, for doping the deposited silicon carbide material with oxygen and nitrogen respectively. Alkylsilane precursors, such as trimethylsilane (TMS), may also be used with the organosilicon precursors described herein to modify or change desired film properties.

0031[0021] Precursors with siloxane bonds provide silicon carbide films with bonded oxygen that can reduce the dielectric constant of the film as well as reduce the current leakage of the film. Examples of suitable siloxane precursors include cyclic compounds, for example, 1 ,3,5,7-tetramethylcyclotetrasiloxane (TMCTS) or octamethylcyclotetrasiloxane (OMCTS), and aliphatic compounds, such as 1 ,1 ,3,3- tetramethyldisiloxane (TMDSO).

0032[0022] Compounds having bonded nitrogen, such as in the silazane compounds, can improve the hardness of films as well as reduce the current leakage of the films. Examples of suitable silizane precursors includes aliphatic compounds, such as hexamethyldisilazane and divinyltetramethyldisilizane, as well as cyclic compounds, such as hexamethylcyclotrisilazane.

0033[0023] The barrier layer may further be doped with oxygen, boron, or phosphorous to reduce the dielectric constant of the deposited material. An atomic ratio of dopant to organosilicon compound in the processing gas is about 1 :5 or greater, such as between about 1 :5 and about 1 :100. Phosphorus and/or boron doping of the low k silicon carbide layer may be performed by introducing phosphine (PH₃) or borane (BH₃), or borane derivatives thereof, such as diborane (B₂H₆), into the chamber during the deposition process.

0034[0024] Oxygen doping may occur by optionally including an oxygen-containing gas, for example, oxygen (O₂), ozone (O₃), nitrous oxide (N₂O), carbon monoxide (CO), carbon dioxide (CO₂), or combinations thereof. A siloxane compound may also be used with the processing gas for oxygen doping of the deposited material. Nitrogen doping may occur by optionally including a nitrogen-containing gas, for example, ammonia (NH₃), nitrogen (N₂), a silazane compound, or combinations thereof.

0035[0025] A silicon carbide barrier layer may be deposited in one embodiment by supplying an organosilicon compound, such as diphenylsilane, to a plasma processing chamber at a flow rate between about 10 milligrams/minute (mgm) and about 1500 mgm, optionally supplying a dopant at a flow rate between about 10 seem and about 2000 seem, supplying an inert gas at a flow rate between about 1 seem and about 10000 seem, maintaining a substrate temperature between about 0°C and about 500°C, maintaining a chamber pressure below about 500 Torr and an RF power of between about 0.03 watts/cm² and about 1500 watts/cm².

0036[0026] The RF power can be provided at a high frequency such as between 13 MHz and 14 MHz and/or at a low frequency such as between 100 kHz and 1000 kHz. The RF power can be provided continuously or in short duration cycles wherein the power is on at the stated levels for cycles less than about 200 Hz and the on cycles total between about 10% and about 30% of the total duty cycle. The processing gas may be introduced into the chamber by a gas distributor, the gas distributor may be positioned between about 200 mils and about 1200 mils from the substrate surface. The gas distributor may be positioned between about 300 mils and about 800 mils during the deposition process.

0037[0027] A suitable reactor for performing the processes described herein is a DxZ™ chemical vapor deposition chamber commercially available from Applied Materials, Inc., Santa Clara, California. An example of a CVD reactor that may be used with the processes herein is described in U.S. Patent 5,000,113, entitled A Thermal CVD/PECVD Reactor and Use for Thermal Chemical Vapor Deposition of Silicon Dioxide and In-situ Multi-step Planarized Process, issued to Wang et al. and assigned to Applied Materials, Inc., the assignee of the present invention.

0038[0028] The above process parameters provide a deposition rate for the silicon carbide layer in the range of about 50 A/min to about 20,000 A/min, such as a range between about 100 A/min and about 3000 A/min, when implemented on a 200 mm (millimeter) substrate in a deposition chamber available from Applied Materials, Inc., Santa Clara, California.

0039[0029] An example of a preferred silicon carbide barrier layer deposition process includes introducing dimethylphenylsilane at about 500 mg/min into the processing chamber, introducing helium at about 1000 seem into the processing chamber, generating a plasma in the processing chamber by applying 200 watts of RF power, maintaining the substrate temperature at about 350°C, maintaining the chamber pressure at about 6 Torr to deposit a silicon carbide barrier layer. The spacing between the gas distributor and the substrate surface was 450 mil. A silicon carbide layer barrier can be deposited at about 1500 A/min by this process. The deposited silicon carbide barrier layer exhibited a dielectric constant of about 3.4.

0040[0030] Other examples of preferred silicon carbide barrier layer deposition processes include introducing dimethylphenylsilane at about 100 mg/min into a processing chamber, introducing helium at about 2000 seem into the processing chamber, generating a plasma in the processing chamber by applying 100, 200, or 300 watts of RF power, maintaining the substrate temperature at about 350°C, and maintaining the chamber pressure at about 6 Torr to deposit a silicon carbide barrier layer. The spacing between the gas distributor and the substrate surface was 650 mil. The deposited silicon carbide barrier layers exhibited dielectric constants of about 3.42 to about 3.96.

0041[0031] Following deposition, the deposited dielectric material, i.e., the deposited silicon carbide barrier layer, may be annealed at a temperature between about 100°C and about 450°C for between about 1 minute and about 60 minutes, preferably at about 30 minutes, to reduce the moisture content and increase the solidity and hardness of the dielectric material, if desired. The anneal is preferably performed before the deposition of the next layer which prevents shrinkage or deformation of the dielectric layer. Inert gases, such as argon and helium, may be added to the annealing atmosphere. [0032] The deposited silicon carbide barrier layer may be plasma treated to remove contaminants or otherwise clean the exposed surface of the silicon carbide layer prior to subsequent deposition of materials thereon. The plasma treatment may be performed in the same chamber used to deposit the silicon and carbon containing material. The plasma treatment is believed to improve film stability by forming a protective layer of a higher density material than the untreated silicon carbide material. The plasma treatment is also believed to improve film adhesion to subsequent layers. The higher density silicon carbide material is believed to be more resistive to chemical reactions, such as forming oxides when exposed to oxygen, than the untreated silicon carbide material.

0042[0033] The plasma treatment generally includes providing an inert gas including helium, argon, neon, xenon, krypton, or combinations thereof, of which helium is preferred, and/or a reducing gas including hydrogen, ammonia, and combinations thereof, to a processing chamber. The inert gas or reducing gas is introduced into the processing chamber at a flow rate between about 500 seem and about 3000 seem, and generates a plasma in the processing chamber.

0043[0034] The plasma may be generated using a power density ranging between about 0.03 W/cm² and about 3.2 W/cm², which is a RF power level of between about 10 W and about 1000 W for a 200 mm substrate. Preferably, at a power level of about 100 watts for a silicon carbide material on a 200 mm substrate. The RF power can be provided at a high frequency such as between 13 MHz and 14 MHz and/or at a low frequency such as between 100 kHz and 1000 kHz. The RF power can be provided continuously or in short duration cycles wherein the power is on at the stated levels for cycles less than about 200 Hz and the on cycles total between about 10% and about 30% of the total duty cycle.

0044[0035] The processing chamber is preferably maintained at a chamber pressure of between about 1 Torr and about 12 Torr, for example about 3 Torr. The substrate is preferably maintained at a temperature between about 200°C and about 450°C during the plasma treatment. A substrate temperature of about the same temperature of the silicon carbide deposition process, for example about 290°C, may be used during the plasma treatment. The plasma treatment may be performed between about 2 seconds and about 100 seconds, with a plasma treatment between about 15 seconds and about 60 seconds preferably used. The processing gas may be introduced into the chamber by a gas distributor, the gas distributor may be positioned between about 200 mils and about 1200 mils from the substrate surface. The gas distributor may be positioned between about 300 mils and about 800 mils during the plasma treatment.

0045[0036] However, it should be noted that the respective parameters may be modified to perform the plasma processes in various chambers and for different substrate sizes, such as 300 mm substrates. An example of a plasma treatment for a silicon and carbon containing film is further disclosed in U.S. Patent Application Serial No. 09/336,525, entitled, "Plasma treatment to Enhance adhesion and to Minimize Oxidation of Carbon-Containing Layers," filed on June 18, 1999, which is incorporated herein by reference to the extent not inconsistent with the disclosure and claimed aspects of the invention described herein.

0046[0037] The barrier layers are preferably deposited adjacent cap layers and optionally, adjacent dielectric layers comprising silicon, oxygen, and carbon, a dielectric constant of less than about 4, such as less than about 3. The adjacent or nearby dielectric layers for use with the barrier layer material described herein have a carbon content of about 1 atomic percent excluding hydrogen atoms, preferably between about 5 and about 30 atomic percent excluding hydrogen atoms. As used herein, "nearby" dielectric layers refer to dielectric layers that are separated from the barrier layers by an intervening cap layer. The adjacent or nearby dielectric layer may be deposited by oxidizing an organosiliane compound in a plasma enhanced chemical vapor deposition technique. For example, a suitable adjacent or nearby dielectric material may be deposited by reacting trimethylsilane and oxygen in a plasma enhanced chemical vapor deposition technique, with the plasma formed under conditions including a high frequency RF power density from about 0.16 W/cm² to about 0.48 W/cm².

0047[0038] Examples of methods and uses for the adjacent or nearby dielectric layers comprising silicon, oxygen, and carbon, having a dielectric constant of less than about 3 are more further described in United States Patent No. 6,054,379, issued May 25, 2000, United States Patent No. 6,287,990, issued September 11 , 2001 , and United States Patent No. 6,303,523, issued on October 16, 2001 , which are incorporated by reference herein to the extent not inconsistent with the disclosure and claims described herein.

0048[0039] An adjacent cap layer is deposited adjacent a barrier layer described herein by reacting a processing gas including an oxygen-free organosilicon compound in a plasma to form a silicon carbide cap layer. In one embodiment, the oxygen-free organosilicon compound has the formula SiH_x(CH₃)y(C₂H₅)z, wherein x is 1 to 3, y is 0 to 3, and z is 0 to 3, and x+y+z is equal to 4. The oxygen-free organosilicon compound may be an alkylsilane, such as methylsilane, dimethylsilane, trimethylsilane, or tetramethylsilane. Preferably, the oxygen-free organosilicon compound is trimethylsilane. The silicon carbide cap layer may also include nitrogen.

0049[0040] In another embodiment, the oxygen-free organosilicon compound may be a phenyl-containing organosilicon compound. The phenyl-containing organosilicon compound may be an organosilicon compound that is used to deposit a silicon carbide barrier layer on which the cap layer is deposited. However, the barrier layer is deposited using processing conditions that allow phenyl groups to remain attached to silicon atoms in the deposited barrier layer. The silicon carbide cap layer is deposited using processing conditions such that substantially no phenyl groups are attached to silicon atoms in the deposited cap layer.

0050[0041] A silicon carbide cap layer may be deposited in one embodiment by supplying an oxygen-free organosilicon compound, such as trimethylsilane, to a plasma processing chamber at a flow rate between about 50 seem and about 800 seem, supplying an oxygen-free carrier gas, such as helium, argon, nitrogen, or ammonia at a flow rate between about 50 seem and about 2000 seem, maintaining a substrate temperature between about 250°C and about 450°C, maintaining a chamber pressure between about 3 Torr and about 15 Torr, and a RF power of between about 0.02 watts/cm² and about 5 watts/cm², or between about 200 watts and about 800 watts. [0042] The RF power can be provided at a high frequency such as between 13 MHz and 14 MHz and/or at a low frequency such as between 100 kHz and 1000 kHz. The RF power can be provided continuously or in short duration cycles wherein the power is on at the stated levels for cycles less than about 200 Hz and the on cycles total between about 10% and about 30% of the total duty cycle. The processing gas may be introduced into the chamber by a gas distributor, the gas distributor may be positioned between about 200 mils and about 1200 mils from the substrate surface. The gas distributor may be positioned between about 300 mils and about 800 mils during the deposition process.

0051[0043] The cap layer may be deposited in the same chamber in which the barrier layer is deposited. In one embodiment, the cap layer is deposited in a Producer^® Chamber, available from Applied Materials, Inc., Santa Clara, California. An example of a Producer^® Chamber is described in U.S. Patent No. 5,855,681 , which is incorporated by reference herein.

0052[0044] The above process parameters provide a deposition rate for the cap layer in the range of about 100 A/min to about 1000 A/min, when implemented on a 200 mm substrate in a deposition chamber.

0053[0045] An example of a preferred silicon carbide cap layer deposition process includes introducing trimethylsilane at about 320 seem into a processing chamber, introducing helium at about 800 seem into the processing chamber, generating a plasma in the processing chamber by applying about 400 watts of RF power, maintaining the substrate temperature at about 350°C, maintaining the chamber pressure at about 12 Torr to deposit a silicon carbide cap layer. The spacing between the gas distributor and the substrate surface is about 400 mil. A silicon carbide cap layer may be deposited at about 370 A/min by this process and have a dielectric constant of about 4.2.

0054[0046] The deposited silicon carbide cap layer may be plasma treated, as described with respect to the deposited silicon carbide barrier layer. [0047] The embodiments described herein for depositing silicon carbide layers adjacent low k dielectric layers are provided to illustrate the invention, the particular embodiment shown should not be used to limit the scope of the invention.

0055Deposition of a Barrier Layer for a Dual Damascene Structure

0056[0048] An example of a damascene structure 50 that is formed using the silicon carbide material described herein as a barrier layer is shown in Figure 1. A silicon carbide barrier layer 10 is generally deposited using the precursors according to the processes described herein on the substrate surface to eliminate inter-level diffusion between the substrate and subsequently deposited material. The substrate surface may comprise metal features 7 formed in a dielectric material 5.

0057[0049] A first silicon carbide cap layer 11 is generally deposited on the silicon carbide barrier layer 10 using the precursors described herein for depositing silicon carbide cap layers. A first dielectric layer 12, comprising silicon, oxygen, and carbon, as described herein is deposited on the silicon carbide cap layer 11. An etch stop (or second barrier layer) 14 of a silicon carbide material or oxidized organo silane layer is then deposited on the first dielectric layer 12. The etch stop 14 may include a silicon carbide material deposited from the organosilicon precursors described herein or an oxidized organo silane layer. Alternatively, the etch stop 14 may be a nitrogen containing silicon carbide material. The etch stop 14 is then pattern etched to define the openings of the interconnects or contacts/vias 16.

0058[0050] A second dielectric layer 18 is then deposited over the patterned etch stop. A photoresist is then deposited and patterned by conventional means known in the art to define the contacts/via 16. A single etch process is then performed to define the contact/vias 16 down to the etch stop and to etch the unprotected dielectric exposed by the patterned etch stop to define the contacts/vias 16. One or more conductive materials 20 such as copper are then deposited to fill the formed contacts/vias 16.

0059[0051] A preferred dual damascene structure fabricated in accordance with the invention including a silicon carbide barrier layer and a silicon carbide cap layer deposited by the processes described herein is sequentially depicted schematically in Figures 2A-2H, which are cross sectional views of a substrate having the steps of the invention performed thereon.

0060[0052] As shown in Figure 2A, a silicon carbide barrier layer 110 is deposited on the substrate surface from the organosilicon precursors described herein for depositing silicon carbide barrier layers. The silicon carbide barrier layer 110 may be doped with oxygen, boron, phosphorus, or combinations thereof. The silicon carbide barrier layer 110 may be deposited by introducing diphenylsilane at about 500 mg/min into the processing chamber, introducing helium at about 500 seem into the processing chamber, generating a plasma in the processing chamber by applying 100 watts of RF energy, maintaining the substrate temperature at about 290°C, maintaining the chamber pressure at about 3 Torr to deposit a silicon carbide layer. The silicon carbide material is deposited at about 1500 A/min by this process. The deposited silicon carbide layer has a dielectric constant of about 3.4.

0061[0053] A cap layer 111 of silicon carbide is deposited on the barrier layer 110. The silicon carbide cap layer may be deposited in situ by a nitrogen doped silicon carbide process with the source of nitrogen minimized or eliminated during the deposition process. Preferably, the cap layer 111 is deposited by the processes described herein for depositing silicon carbide cap layers from a gas mixture that comprises an oxygen-free organosilicon compound and is reacted to form a plasma.

0062[0054] The silicon carbide barrier layer 110 and the cap layer 111 may be plasma treated with an inert gas including helium (He), argon (Ar), neon (Ne), and combinations thereof, and/or a reducing gas including hydrogen, ammonia, and combinations thereof. The plasma treatment may be performed in situ with the deposition of the barrier layer and the cap layer. Such a plasma treatment is believed to clean contaminants from the exposed surface of the silicon carbide materials and may be used to stabilize the layers, such that they become less reactive with moisture and/or oxygen under atmospheric condition as well as the adhesion of layers formed thereover.

0063[0055] The plasma process includes a processing gas of helium or a reducing gas, such as hydrogen, at a power level of between about 200 watts and about 800 watts for between about 5 seconds and about 60 seconds for a 200 millimeter substrate. The processing chamber is maintained at a pressure of about 8.7 Torr or less and at a substrate temperature of about the deposition temperature of the layer, for example about 350°C for dimethylphenylsilane, during the reactive clean process.

0064[0056] The first dielectric layer 112 of interlayer dielectric material is deposited on the cap layer 111 by oxidizing an organosilane or organosiloxane, such as trimethylsilane, to a thickness of about 5,000 to about 15,000 A, depending on the size of the structure to be fabricated. An example of a low dielectric constant material that may be used as an interlayer dielectric material is Black Diamond™ film commercially available from Applied Materials, Inc., of Santa Clara, California. Alternatively, the first dielectric layer may also comprise other low k dielectric material such as a low k polymer material including parylene or a low k spin-on glass such as un-doped silicon glass (USG) or fluorine-doped silicon glass (FSG).

0065[0057] The first dielectric layer 112 may then be treated by a plasma process including helium or a reducing gas, such as hydrogen, at a power level of between about 200 watts and about 800 watts for between about 5 seconds and about 60 seconds for a 200 millimeter substrate. The processing chamber is maintained at a pressure and at a substrate temperature of about the deposition pressure and temperature of the first dielectric layer 112 during the reactive clean process.

0066[0058] As shown in Figure 2B, the low k etch stop 114, which may be a silicon carbide material, is then deposited on the first dielectric layer to a thickness of about 200 to about 1000 A. The low k etch stop 114 may be deposited from the same precursors and by the same process as the silicon carbide barrier layer 110. The low k etch stop 114 may be plasma treated as described herein for the silicon carbide barrier layer 110. The low k etch stop 114 is then pattern etched to define the contact/via openings 116 and to expose first dielectric layer 112 in the areas where the contacts/vias are to be formed as shown in Figure 2C. Preferably, the low k etch stop 114 is pattern etched using conventional photolithography and etch processes using fluorine, carbon, and oxygen ions. A nitrogen-free silicon carbide, or silicon oxide cap layer 115 between about 100 A and about 500 A thick, such as between about 30 A and about 100 A, may be deposited on the etch stop 114 prior to depositing further materials. A nitrogen-free silicon carbide cap layer 115 may be deposited by the processes described herein for depositing cap layers from a gas mixture comprising an oxygen-free organosilicon compound.

0067[0059] After low k etch stop 114, and the cap layer 115, if present, have been etched to pattern the contacts/vias and the photoresist has been removed, a second dielectric layer 118 of silicon oxycarbide is deposited to a thickness of about 5,000 to about 15,000 A as shown in Figure 2D. The second dielectric layer 118 may be plasma treated with helium or a reducing gas, such as hydrogen, at a power level of between about 600 watts and about 800 watts for between about 15 seconds and about 60 seconds for a 200 millimeter substrate. The processing chamber is maintained at a pressure of about 20 Torr or less and at a substrate temperature of about 450°C or less during the reactive clean process. The plasma treatment is believed to reduce the reactivity of the surface of the layer 118 to subsequently deposited materials.

0068[0060] In an alternative embodiment, a nitrogen-free silicon carbide or silicon oxide cap layer (not shown) between about 100 A and about 500 A thick may be deposited on second dielectric layer 118 prior to depositing additional materials, such as photoresist materials. In a further alternative embodiment, a silicon carbide cap layer (not shown) may be deposited from the same precursors and by the same process as the silicon carbide barrier layer 110 on the second dielectric layer 118 prior to depositing additional materials, such as photoresist materials.

0069[0061] A photoresist material 122 is then deposited on the second dielectric layer 118 (or cap layer) and patterned preferably using conventional photolithography processes to define the interconnect lines 120 as shown in Figure 2E. The photoresist material 122 comprises a material conventionally known in the art, preferably a high activation energy photoresist, such as UV-5, commercially available from Shipley Company Inc., of Marlborough, Massachusetts. The interconnects and contacts/vias are then etched using reactive ion etching or other anisotropic etching techniques to define the metallization structure (i.e., the interconnect and contact/via) as shown in Figure 2F. Any photoresist or other material used to pattern the etch stop 114, the cap layer 115, or the second dielectric layer 118 is removed using an oxygen strip or other suitable process.

0070[0062] The metallization structure is then formed with a conductive material such as aluminum, copper, tungsten or combinations thereof. Presently, the trend is to use copper to form the smaller features due to the low resistivity of copper (1.7 μΩ- cm compared to 3.1 μΩ-cm for aluminum). Preferably, as shown in Figure 2G, a suitable barrier layer 124 such as tantalum nitride is first deposited conformally in the metallization pattern to prevent copper migration into the surrounding silicon and/or dielectric material. Thereafter, copper 126 is deposited using either chemical vapor deposition, physical vapor deposition, electroplating, or combinations thereof to form the conductive structure. Once the structure has been filled with copper or other metal, the surface is planarized using chemical mechanical polishing, as shown in Figure 2H.

0071Examples

0072[0063] Organosilicon compounds described herein were deposited as barrier layers on a substrate surface and analyzed. In one example, a silicon carbide barrier film was deposited from a diphenylsilane compound and compared to a silicon carbide barrier film from a conventional silicon carbide precursor, trimethylsilane.

0073[0064] Both diphenylsilane and trimethylsilane precursors were deposited by introducing diphenylsilane or trimethylsilane at about 500 mg/min into the processing chamber, introducing helium at about 500 seem into the processing chamber, generating a plasma in the processing chamber by applying 100 watts of RF energy, maintaining the substrate temperature at about 290°C, maintaining the chamber pressure at about 3 Torr to deposit a silicon carbide layer. The heater spacing was about 450 mils from the substrate surface.

0074[0065] The deposited films were examined and analyzed for dielectric constant and barrier layer diffusion. The diphenylsilane silicon carbide film had a measured dielectric constant of about 3.4 and the trimethylsilane silicon carbide film had a measured dielectric constant of about 4.3. [0066] The barrier layer properties were tested by a Bias Temperature test, which was performed by forming a damascene device using the above described silicon carbide films and subjecting the deposited films to a substrate temperature of about 275°C while measuring leakage current for a device. Leakage current increases with degrading barrier layer properties. When leakage current reaches about 10^"3 amps/cm², the barrier layer is considered to have failed. When 50% of the devices failed under these processing conditions, the time was measured to indicate barrier effectiveness for the deposited films. Comparison of the films indicated that the diphenylsilane silicon carbide had a leakage current of about 1e^"09 amps/cm² at 1 mega volts/cm (MV/cm) and about 1e^"8 amps/cm² at 2 MV/cm and had a 50% failure rate after about 7.9 hours while the trimethylsilane silicon carbide film had a leakage current of about 1e^"09 amps/cm² at 1 MV/cm and about 1e^"6 amps/cm² at 2 MV/cm and had a 50% failure rate after about 4.4 hours.

0075[0067] In a further example, diphenylmethylsilane was used to deposit a silicon carbide barrier layer by introducing the diphenylmethylsilane at about 500 mg/min into the processing chamber, introducing helium at about 500 seem into the processing chamber, generating a plasma in the processing chamber by applying 100 watts of RF energy, maintaining the substrate temperature at about 290°C for a diphenylsilane deposited film, maintaining the chamber pressure at about 3 Torr to deposit a silicon carbide layer. The heater spacing was about 450 mils from the substrate surface.

0076[0068] The deposited films were examined and analyzed for dielectric constant and barrier layer diffusion. The diphenylmethylsilane silicon carbide film had a measured dielectric constant of about 3.6 compared to about 4.3 for trimethylsilane deposited silicon carbide films. Comparison of the films indicated that the diphenylmethylsilane silicon carbide had a leakage current of about 3e^"9 amps/cm² at 1 MV/cm and about 4e^"8 amps/cm² at 2 MV/cm and had a 50% failure rate after about 10 hours while the trimethylsilane silicon carbide film had a leakage current of about 1e^"09 amps/cm² at 1 MV/cm and about 1e^"6 amps/cm² at 2 MV/cm and had a 50% failure rate after about 4.4 hours. [0069] In a further example, dimethylphenylsilane was used to deposit a silicon carbide barrier layer by introducing the dimethylphenylsilane at about 500 mg/min into the processing chamber, introducing helium at about 1000 seem into the processing chamber, generating a plasma in the processing chamber by applying 200 watts of RF energy, maintaining the substrate temperature at about 350°C for a diphenylsilane deposited film, maintaining the chamber pressure at about 6 Torr to deposit a silicon carbide layer. The heater spacing was about 450 mils from the substrate surface.

0077[0070] The deposited films were examined and analyzed for dielectric constant and barrier layer diffusion. The dimethylphenylsilane silicon carbide film had a measured dielectric constant of about 3.5 compared to about 4.3 for trimethylsilane deposited silicon carbide films. Comparison of the films indicated that the dimethylphenylsilane silicon carbide had a leakage current of about 1e^"9 amps/cm² at 1 MV/cm and about 2e^"8 amps/cm² at 2 MV/cm and had a 50% failure rate after about 11 hours while the trimethylsilane silicon carbide film had a leakage current of about 1 e^"09 amps/cm² at 1 MV/cm and about 1 e^"6 amps/cm² at 2 MV/cm and had a 50% failure rate after about 4.4 hours.

0078[0071] This data indicates a significant and unexpected improvement in barrier layer properties and dielectric constant for diphenylsilane or alkyl substituted diphenylsilane compounds in comparison to available barrier layer processes.

0079[0072] Data was also collected to compare the properties of the barrier layers described herein with the properties of a combination of the barrier layers and cap layers described herein. A barrier layer was deposited in a Producer^® Chamber using a plasma from a flow of dimethylphenylsilane between about 100 mg/min and about 300 mg/min, a flow of helium between about 500 seem and about 2000 seem, a spacing between about 350 mils and about 600 mils, and a RF power between about 200 watts and about 500 watts. The barrier layer had a dielectric constant k of 3.4 and a leakage current at 1 MV/cm of 2e^"9 amps/cm². A silicon carbide cap layer was deposited using a Producer^® Chamber using a plasma from a flow of trimethylsilane at 320 seem, a flow of helium at 800 seem, a 400 mil spacing, a pressure of 12 Torr, and a RF power of 400 watts. The silicon carbide cap layer had a dielectric constant k of 4.2 and a leakage current at 1 MV/cm of 3.5e^"9 amps/cm². The combination, i.e., the stack, of the barrier layer and the cap layer had a dielectric constant k of 3.43 and a leakage current at 1 MV/cm of 2e^"9 amps/cm². Thus, the stack of the barrier layer and the cap layer did not have a significantly higher k than the barrier layer alone.

0080[0073] The barrier layers, cap layers, and combined stack of barrier layers and cap layers described herein were treated with an oxygen (O₂) plasma to measure the oxidation of the layers. The results are shown in Table 1.

0081Table 1.

0082<img file="WO2004033752A2_D0001.tif" />

0083[0074] Two sets of values are shown for each type of deposited layer, as data was collected from layers deposited in each of the two processing regions of a Producer^® Chamber. The thickness of the oxidized layer after the oxygen plasma treatment was significantly larger for barrier layers without cap layers than barrier layers with cap layers, as shown in Table 1. Thus, it is believed that the cap layers described herein reduce the amount, i.e., the depth, of oxidation of the barrier layers described herein.

0084[0075] While the foregoing is directed to preferred embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims which follow.