Method and device for automated layer generation for double-gate finFET designs

A combined cell structure 'C' (508) (FIGURE 5C) contains two single cell structures 'A' and 'B' (502', 504') (FIGURE 5B) placed adjacent to each other. The combined fin shapes (540) lead to a violation of a design rule related to fin topology in the overlapping region within the indicated two circles (570, 580). This violation is characterized by the step-like shape of the fins, in particular proximity of these steps to the gates (505, 515). Figure 5D shows a corresponding cell structure 'C' (512) that contains the same placement of cell structure 'A' (502) and cell structure 'B' (504) but without previously generated fins (540) in cell structure 'A' (502) and cell structure 'B' (504). Considering any placement combinations of cell structure 'A' (502) and cell structure 'B' (504), respectively, to other cell structures, occurring in the design hierarchy. A fin generation tool thus decides not to place the fins in the hierarchy of cell structure 'A' and cell structure 'B'. The fin generation is delegated to the hierarchy above thus revealing a combined fin shape (560) without any steps, as indicated by circle (590).