Improved FFT/IFFT processor

Field of the invention:

0001The present invention relates to the field of digital signal processing. More particularly the invention relates to an improved FFT / IFFT processor.

Background of the invention:

0002The class of Fourier transforms that refer to signals that are discrete and periodic in nature are known as Discrete Fourier Transforms (DFT). The discrete Fourier transform (DFT) plays a key role in digital signal processing in areas such as spectral analysis, frequency domain filtering and poly-phase transformations.

0003The DFT of a sequence of length N can be decomposed into successively smaller DFTs. The manner in which this principle is implemented falls into two classes. The first class is called a "decimation in time" approach and the second is called a "decimation in frequency" method. The first derives its name from the fact that in the process of arranging the computation into smaller transformations the sequence "x(n)" (the index 'n' is often associated with time) is decomposed into successively smaller subsequences. In the second general class the sequence of DFT coefficients "x(k)" is decomposed into smaller subsequences (k denoting frequency). The present concept of the invention applies to both "decimation in time" as well as "decimation in frequency".

0004Since the amount of storing and processing of data in numerical computation algorithms is proportional to the number of arithmetic operations, it is generally accepted that a meaningful measure of complexity, or of the time required to implement a computational algorithm, is the number of multiplications and additions required. The direct computation of the DFT requires "4N²" real multiplications and "N(4N-2)" real additions. Since the number of computations and thus the computation time is approximately proportional to "N²" it is evident that the number of arithmetic operations required to compute the DFT by the direct method becomes very large for large values of "N". For this reason, computational procedures that reduce the number of multiplications and additions are of considerable interest. The Fast Fourier Transform (FFT) is an efficient algorithm for computing the DFT.

0005The basic computational block is called a "butterfly" ---- a name derived from the appearance of flow of the computations involved in it. Fig.-1 shows a typical radix-2 butterfly computation. 1.1 represents the 2 inputs (referred to as the "odd" and 'even" inputs) of the butterfly and 1.2 refers to the 2 outputs. One of the inputs (in this case the odd input) is multiplied by a complex quantity called the twiddle factor (W_N^k). The general equations describing the relationship between inputs and outputs are as follows:<maths id="math0001" num=""><math display="block"><mrow><msub><mrow><mtext>X[k] = x[n] + x[n+N/2]W</mtext></mrow><mrow><mtext>N</mtext></mrow></msub><msup><mrow><mtext>​</mtext></mrow><mrow><mtext>k</mtext></mrow></msup></mrow></math><img file="EP1538533A2_D0001.tif" /></maths><maths id="math0002" num=""><math display="block"><mrow><msub><mrow><mtext>X[k+N/2] = x[n] - x[n+N/2]W</mtext></mrow><mrow><mtext>N</mtext></mrow></msub><msup><mrow><mtext>​</mtext></mrow><mrow><mtext>k</mtext></mrow></msup></mrow></math><img file="EP1538533A2_D0002.tif" /></maths>

0006An FFT butterfly calculation is implemented by a z-point data operation wherein "z" is referred to as the "radix". An "N" point FFT employs "N/z" butterfly units per stage (block) for "log_z N" stages. The result of one butterfly stage is applied as an input to one or more subsequent butterfly stages.

0007The conventional method of implementing an FFT or Inverse Fourier Transform (IFFT) uses a radix-2 / radix-4 / mixed-radix approach with either "decimation in time (DIT)" or a "decimation in frequency (DIF)" approach.

0008Computational complexity for an N-point FFT calculation using the radix-2 approach = O(N/2 * log₂N) where "N" is the length of the transform. There are exactly "N/2 * log₂N" butterfly computations, each comprising 3 complex loads, 1 complex multiply, 2 complex adds and 2 complex stores. A full radix-4 implementation on the other hand requires several complex load/store operations.

0009With the advancement of VLSI technology, it has become possible to incorporate several execution units like ALUs (Arithmetic and Logic unit) and multipliers in the processor cores, thereby permitting computational throughput to be increased. All these advancements may be utilised to enhance the performance of FFT/IFFT in terms of total time required to complete a FFT/IFFT of a given size. If we look at the basic butterfly structure of <b>figure 1</b>, it is evident that the computations i.e. the multiplications, additions/subtractions are dependent on the loading of inputs and loading of the twiddle factor in the sense that computations cannot start unless these operands are loaded from the memory. The computations can finish fast because of the availability of multiple execution units which may function in parallel but there are requirements for faster loading and storing of operands and results. In many processors, multiple load/store units achieve this. Another solution to this problem is loading/storing operands/results for multiple consecutive butterflies and using multiple execution units to compute multiple butterflies almost simultaneously. This approach requires only augmentation of the data bus width. This is much more economical in terms of silicon area and complexity as compared to multiple load/store units. The necessary requirement for this is that the inputs/outputs of the consecutive butterflies be stored in consecutive locations in the memory. If we see the butterfly structure from top to bottom of any stage (except the first stage) for FFT/IFFT, as shown in <b>figure 4</b> for FFT/IFFT of order 16, it is clear that the consecutive butterflies cannot be computed for operands in consecutive memory locations.

0010<b>Figure 2</b> shows a block diagram for simultaneous loading of two n-bit operands. In this mechanism it is required to have two separate load/store units in the central processing unit (CPU) each having n-bit wide data bus connected to the memory block separately. This mechanism for simultaneous loading of two n-bit operands requires multiple load store units and hence is an expensive mechanism.

0011US patent 5,293,330 describes a pipelined processor for mixed size FFT. These and many more works have dealt with enhancement of the performance of FFT/IFFT. The performance can further be improved with the implementation of the present invention.

0012Our co-pending application reference number 127/Del/2003 describes an algorithm, which is suitable for use with the proposed architecture for loading/storing inputs/outputs of multiple consecutive butterflies with only one load/store instruction.

Objects and Summary of the invention:

0013The object of the present invention is to overcome the bottleneck of memory load/store and provide a device and method for implementing FFT/IFFT with improved performance using less silicon area and hence cost.

0014To achieve the said objective the present invention provides an improved FFT / IFFT processor comprising: <ul id="ul0001" list-style="dash" compact="compact"><li>computation means capable of processing butterfly operations, and;</li><li>storage means for storing the operands of butterfly operations,</li></ul> characterized in that it includes a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and the computation means is capable of simultaneously accessing and processing said multiple butterfly operations.

0015The said mechanism is an address generator that constructs the addresses of the operands of multiple consecutive butterfly operations by introducing a '0' and/or '1' at a predetermined bit location in the addresses of the operands of consecutive butterflies of the same stage.

0016The predetermined location for introducing a bit for constructing the addresses of the operands of multiple consecutive butterfly operation depends upon the number of the FFT / IFFT stage which is being computed.

0017The simultaneous accessing and processing of said multiple butterfly operations is achieved by providing augmentation of data buses and registers.

0018The twiddle factors of the butterfly are computed by initializing a counter and then incrementing it by a value corresponding to the number of contiguous butterflies which are to be computed simultaneously and appending the result with a specified number of "0"s.

0019The invention further provides an improved method for FFT / IFFT processing comprising steps of: <ul id="ul0002" list-style="dash" compact="compact"><li>providing computation means capable of processing butterfly operations;</li><li>storing the operands of multiple consecutive butterfly operations in contiguous storage locations, and;</li><li>simultaneously accessing and processing said multiple butterfly operations.</li></ul>

0020The operands of multiple consecutive butterfly operations are stored in contiguous memory locations by constructing the addresses of the operands of multiple consecutive butterfly operations by introducing a '0' and/or '1' at a predetermined bit location in the addresses of the operands of consecutive butterflies of the same stage.

0021The multiple consecutive butterfly operations are simultaneously processed by providing augmented data buses and registers in the computation unit.

Brief Description of the Drawings:

0022The present invention will now be explained with reference to the accompanying drawings. <dl id="dl0001"><dt><b>Figure 1</b></dt><dd>shows the basic structure of the signal flow in a radix-2 butterfly computation for a discrete Fourier transform.</dd><dt><b>Figure 2</b></dt><dd>shows a block diagram for simultaneous loading of two n-bit operands according to prior art.</dd><dt><b>Figure 3</b></dt><dd>shows a block diagram for simultaneous loading of 'm' number of n-bit operands in accordance with the present invention.</dd><dt><b>Figure 4</b></dt><dd>shows a 2-processor implementation of butterflies for a 16-point FFT, in accordance with the present invention for the multi-processor case.</dd><dt><b>Figure 5</b></dt><dd>shows a block diagram for address generator.</dd></dl>

Detailed Description of the invention:

0023<b>Figure 3</b> shows a block diagram for simultaneous loading of 'm' number of n-bit operands in accordance with the present invention. In this invention an area, cost effective and speedy solution for the FFT/IFFT computation is provided by providing an FFT/ IFFT processor that has an augmented data bus connects memory and CPU. The memory stores the operands of multiple consecutive butterflies in contiguous storage locations. The CPU has a load store unit connected to the augmented data buses that is capable of simultaneously accessing and processing said multiple butterfly operations thus providing above stated advantages. The operation of the processor is understood and described in the following discussion.

0024<b>Figure 4</b> shows the implementation for a 16-point FFT using the present invention for a single as well as 2-processors system. Solid lines are in one memory block, and dotted lines in the other. Each memory block is of size 8-points (N/2 in general terms). '0' represents the computational blocks. The left side of each computational block is its input (the time domain samples) while the right side is its output (transformed samples). The present invention uses a mixed radix approach with decimation in time. The first two stages of the radix-2 FFT/IFFT are computed as a single radix-4 stage. As these stages contain only load/stores and add/subtract operations there is no need for multiplication. This leads to reduced time for FFT/IFFT computation as compared to that with full radix-2 implementation. The next stages have been implemented as radix-2. The three main nested loops of conventional implementations have been fused into a single loop which iterates "N/2*(log₂ N-2))/2*(number of processor)" times. If we see any stage, it is evident that inputs/outputs of consecutive butterflies in any memory block are in consecutive memory locations. So with one load/store instruction inputs/outputs for multiple butterflies are loaded/stored. So a processor is used to compute multiple butterflies in one loop iteration. For single processor system one processor accesses the different memory blocks. For a two processors system, two different processors access the two different memory blocks. This is because there is no data dependency between different butterflies of different memory blocks in this algorithm, both during and between stages.

0025In the present implementation (in two processors system) of the invention each processor comprises of one or more ALUs (Arithmetic Logic unit), multiplier units, data cache, and load/store units. Each processor has an autnomous memory and the distribution of butterflies is such that there is no inter-processor communication required after the distribution of data. The distributions of data into different memory blocks take place after "log₂P" stages where "P" is the number of processors.

0026According to the invention the addresses of inputs to the multiple contiguous butterflies in a stage (i^th stage) of an FFT/IFFT of size N having number of stages (Log₂N) K is generated by initiating a counter that counts from '0' to 'N/2-1' and then constructing input address of fist input of each butterfly by introducing '0' at (i+1)^th location from the Least Significant Bit (LSB) of the counter value and the second input addresses are constructed by introducing '1' at (i+1)^th location from the Least Significant Bit (LSB) of the counter value. As shown in <b>figure 5</b>

0027Further for generating addresses of the twiddle factor in a stage 'i', for each processor j (where j = 0,1,2,...(P-1)) another counter is initiated with values from '0' to 'P-1' wherein 'P' is the total number of the processor in the system, then the address of twiddle factor is constructed by appending {(K-1) - (i+2)} number of zeroes to the additional counter value. For generating twiddle factor address of the next butterfly in same stage 'i' the additional counter value is incremented by number of contiguous butterflies which are to be computed simultaneously and subsequently appending {(K-1) - (i+2)} zeroes to get the new additional counter value.

0028Inter-processor communication takes place only before and after all the computations have been completed. The amount of data communication overhead does not increase with an increase in the number of processors.

0029It will be apparent to those with ordinary skill in the art that the foregoing is merely illustrative intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the above invention.

0030Accordingly, this invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims.