Event driven dynamic logic for reducing power consumption

BACKGROUND OF THE INVENTION

1.

Field of the Invention

0001This invention pertains generally to digital logic circuitry, and more particularly to reducing power consumption using event driven logic wherein the clock signal is only propagated within the circuit after a true logic operation is performed.

2.

Description of the Background Art

0002Conventional logic circuitry often utilizes a clock signal which is received by various levels of gating within the circuitry for synchronizing the state changes within the circuitry so as to eliminate race conditions and other similar problems. As a result, the clock signal is applied to a number of gates within each logic block or section. A predetermined gate capacitance exists for each gate which is subject to repeated charge and discharge cycles following clock activity. Consequently, circuit power consumption is increased by repetitive charging and discharging, even when no net circuit activity results. Furthermore, clock signal loading can be substantially increased which requires higher power clock sources and additional dissipation.

0003For example, <figref idref="f0001">FIG. 1</figref> depicts a conventional four-input AND gate 10 implemented in CMOS static logic having data inputs 12 and a data output 14. All four inputs 12 (<i>IN1 - IN4</i>) must be retained "high" to allow the voltage at node <i>A</i> to discharge to <i>V_SS</i> (logic state = <i>"low"</i>) through transistors 16a, 18a, 20a, 22a, while transistors 16b, 18b, 20b, 22b, are retained in an off state. With node <i>A</i> driven <i>low</i> at the input of inverter 24, signal output <i>OUT</i> 14 transitions to <i>V_DD</i> (logic state = <i>"high"</i>). It should be noted that CMOS static logic is considered extremely stable and is in widespread use within conventional circuit designs, particularly within integrated circuits. One drawback of this static topology is that each input signal is gated to both PMOS and NMOS transistors, thereby subjecting the inputs to large gate load capacitances and their associated charge delays.

0004To improve the speed of CMOS static logic, various kinds of dynamic logic have been proposed. The purpose of these proposed designs is to minimize gate loading and to control circuit operation in response to a clock signal. Dynamic logic circuits also provide a ready means of synchronizing signal state changes between various logic stages within a digital logic section or device.

0005<figref idref="f0002">FIG. 2</figref> depicts a conventional four-input AND gate 30 implemented with dynamic logic which is generally referred to as "domino" logic. Inputs 32 (<i>IN1 - IN4</i>) are connected to transistors 36, 38, 40, 42 respectively. A clock signal <i>CLK</i> 44 is connected to complementary transistors 46, 48. The output inverter 50, with a keeper circuit 52, drives output signal <i>OUT</i> 34. In response to <i>CLK</i> going <i>low</i>, node <i>A</i> and output signal <i>OUT</i> 34 are precharged at <i>V_DD (high)</i> and <i>V_SS (low)</i> levels, respectively. It will be noted that since transistor 48 is held inactive during precharging, the state of the inputs does not affect precharging of node A.

0006The precharging is performed during a clock phase referred to as a "precharge phase" which occurs in the depicted circuit while the clock is held in a low state. It should be appreciated, however, that the precharge clock phase may be of either polarity and subject to other conditions, depending upon circuit implementation.

0007Circuit element 52 is implemented as a "keeper" circuit to maintain the voltage of node <i>A</i>. The "keeper" shown is preferably implemented using a small transistor 52 that exhibits a higher on-state resistance than the other transistors driving node <i>A</i>, thereby allowing its state to be over-ridden.

0008Upon clock signal <i>CLK</i> 44 transitioning to a <i>high state,</i> an evaluation phase is entered within which the state of the inputs is readily reflected in data output 34. Consider the case of satisfying the AND logic configuration with all inputs 32 being held <i>high</i> as the evaluation phase is entered. Node <i>A</i> is discharged to <i>low</i> through transistors 36-42, 48 whereupon output signal <i>OUT</i> 34 switches to <i>high.</i> If any inputs 32 are held <i>low</i> as the evaluation phase commences, then node A is retained <i>high</i> and output signal <i>OUT</i> 34 remains <i>low</i>.

0009Each input is gated to a single NMOS transistor, wherein the resultant gate load capacitance is smaller than that provided by conventional CMOS static logic as depicted in <figref idref="f0001">FIG. 1</figref>. As the mobility of electrons is typically faster than that of holes by more than a factor of two, the size of NMOS transistors is also typically less than half the size of their PMOS transistor counterparts. Therefore, the effective gate load capacitance of dynamic logic can be approximately one-third of that exhibited by static logic. As a consequence of reducing gate load capacitance, dynamic logic can operate at significantly higher clock rates than similar CMOS static logic. A typical dynamic circuit can operate approximately thirty percent (30%) faster than a substantially equivalent static circuit. However, dynamic logic circuits are subject to high power consumption levels.

0010Considering the operation of dynamic circuit 30 of <figref idref="f0002">FIG. 2</figref>, it will be noted that at the falling edge of clock signal <i>CLK</i> 44, the gate of transistor 46 is discharged by clock signal <i>CLK</i> 44, thereby activating transistor 46 to precharge node <i>A</i>. Similarly, the gate of transistor 48 is discharged to deactivate transistor 48, wherein charge current is driven to node A regardless of the state of output <i>OUT</i> 34. Consider the case where inputs <i>IN1, IN2</i> and <i>IN3</i> are being held <i>high</i> while input <i>IN4</i> is held <i>low</i> during the evaluation phase (i.e. <i>CLK</i> is <i>high</i>). As a result of transistor 42 remaining in an off state, a non-satisfied AND condition exists, wherein the voltage of node <i>A</i> is not discharged and remains at the precharge level <i>V_DD (high).</i> However, upon clock signal <i>CLK</i> 44 transitioning <i>low</i>, transistor 46 is switched-on to charge node A toward <i>V_DD</i> while the gate capacitance of transistor 48 is discharged. This circuit illustrates that even without circuit activity, the capacitance associated with transistors 46 and 48 are being charged or discharged when clock input <i>CLK</i> 44 transitions either <i>low</i> or <i>high.</i>

0011It should therefore be appreciated that in conventional dynamic logic circuitry, as described, the clock signal <i>(CLK)</i> repeatedly charges and discharges a number of gate capacitances whether or not the state of the logic circuit is subject to change. As a result, power is always consumed within a dynamic logic stage subject to receipt of an active clock. It should be appreciated that with regard to the four input AND gate shown in <figref idref="f0002">FIG. 2</figref>, the probability of circuit activity that may result in a change of the output signal is one out of sixteen (assuming equal input probabilities). As a result, power is consumed unnecessarily by the clock without any circuit operation for fifteen out of the sixteen possible input combinations. It should be appreciated that this "inactive" mode power consumption may be larger or smaller than in the four input AND gate example and is dependent upon the circuit configuration (i.e. number of inputs, gating, use of additional combinatorial circuits and sequential circuits, and so forth) and signal activity within the given application.

0012<figref idref="f0003">FIG. 3</figref> exemplifies a sequential logic circuit 70 to illustrate that clock signal related power losses are also common problems within sequential logic circuits. A conventional flop-flop device 70 (D-FF) is depicted in the figure having a data input <i>D</i> 72 and a clock signal input <i>CLK</i> 74, while complementary outputs <i>Q</i> 76 and <i>Q-bar 78</i> are provided.

0013During flip-flop operation, as clock signal <i>CLK</i> 74 goes <i>low</i>, node <i>X</i> is precharged to <i>V_DD (high)</i> through transistor 80. An inverted clock signal is also generated from clock signal <i>CLK</i> 74 propagating through an odd number of inverters 82, 84, 86. An OR'ed grouping of transistors 80, 88 and 90 can provide for charging of node <i>X</i>, while an AND'ed series of transistors 92, 94 and 96 can operate to control the discharging of node <i>X</i>. A latching section is shown comprising four transistors 98, 100, 102, 104 that operate in response to clock signal <i>CLK</i> 74 and the state of charge of node X to drive an output stage having inverters 106, 108.

0014After clock signal <i>CLK</i> 74 transitions to <i>low</i>, the inverted clock signal <i>CLKD-</i>bar transitions to <i>high</i> following the inverter propagation delay, whereupon transistor 96 and transistor 104 switch to an on state. Output data is driven by transistor 98 in conjunction with inverter 106 and 108 preferably implemented as a "keeper".

0015First, the situation is considered in which the latched data at node Q 76 is <i>low,</i> as set by a previous cycle, while the input signal <i>D</i> is held <i>high.</i> In response, transistor 94 is retained in an on state, whereupon as clock signal <i>CLK</i> 74 transitions <i>high</i> entering the evaluation phase, transistor 92 and transistor 100 are switched-on and node <i>X</i> is discharged toward <i>V_SS (low)</i> through transistors 92, 94 and 96 until transistor 96 is switched-off following the propagation delays associated with inverters 82, 84, 86. As node <i>X</i> is discharged, transistor 98 is switched-on and node <i>Q</i> 76 and <i>Q-bar</i> 78 transition to <i>high</i> and <i>low</i>, respectively. When the latched data output is being held <i>high</i> as data input D 72 is retained low, node <i>X</i> remains at the precharged <i>high</i> level (<i>V_DD</i>) because transistor 88 is switched-on and transistor 94 is switched-off. When clock signal <i>CLK</i> 74 transitions to a <i>high,</i> then node <i>Q</i> 76 is discharged to <i>V_SS (low)</i> through transistors 100, 102, 104 until <i>CLKD-bar</i> transitions to <i>low</i> following the inverter propagation delays. Consequently, the latched data at node Q 76 is switched <i>high</i> to <i>low</i> and <i>Q-bar</i> transitions to <i>high.</i>

0016This D flip-flop circuit would be operable at sufficiently high frequencies to allow implementation of high frequency pipeline architectures. Unfortunately, the substantial power losses which arise within the dynamic logic circuits as a consequence of repetitive charging and discharging make the circuit generally less desirable for these applications.

0017It will be appreciated that in the case where clock signal <i>CLK</i> 74 transitions to <i>high</i> (evaluation phase), when the latched data is <i>high</i> and data input <i>D</i> is also <i>high,</i> then node <i>X</i> is discharged to <i>V_SS (low)</i> and node <i>Q</i> is connected to <i>V_DD (high)</i> through transistor 98. However, as the latched data is already <i>high,</i> no net circuit activity is occurring as a result of the operation of transistor 98, and yet the clock signal <i>CLK 74</i> must still charge the gate capacitances of transistors 92, 100. In addition, when clock signal <i>CLK</i> 74 transitions to low, the gate capacitances of transistor 92 and transistor 100 are discharged and the delay pulse circuit is activated to charge the gate capacitance of transistors 96, 104. These operations are repeated even though the output data remains unchanged <i>(high)</i> while the clock signal <i>CLK 74</i> is running. As a result, a substantial percentage of the operating power is unnecessarily consumed by the unproductive activity of clock signal <i>CLK</i> 74, which is subject to loading even when no desired circuit state changes occur.

0018It has been shown that both combinatorial and sequential logic circuits are similarly subject to capacitive loading of the clock signal, wherein circuit power is consumed even when no net (productive) circuit activity is occurring.

0019<patcit id="pcit0001" dnum="US5831452A"><text>US 5,831,452 to Nowak </text></patcit>discloses a precharge circuit provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.

0020<patcit id="pcit0002" dnum="US6040716A"><text>US 6,040,716 to Bosshart</text></patcit> discloses a logic circuit (18) comprising a first phase domino logic circuit (20) and a second phase domino logic circuit (22). Each of the domino logic circuits comprises a precharge node (20.sub.PN, 22.sub.PN), a coupling device (20.sub.PT, 22.sub.PT) which when conducting couples the precharge node to a precharge voltage (V.sub.DD) during a precharge phase, and a discharge path (20.sub.L and 20.sub.DT, 22.sub.L and 22.sub.DT) connected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase. Further, each of the domino logic circuits comprises an inverter (20.sub.IN, 22.sub.IN) coupled to the precharge node and providing an output responsive to a voltage at the precharge node. The output of the inverter of the first phase domino logic circuit is connected to control the conduction of the discharge path of the second phase domino logic circuit. The logic circuit further comprises a conductor for providing a clock signal (CLOCK), and circuitry for commencing the evaluate phase of the first phase domino logic circuit at a first time (t1) in response to the clock signal transitioning from a first state to a second state. Still further, the logic circuit comprises circuitry for commencing the evaluate phase of the second phase domino logic circuit at a second time (t2) following the first time, and circuitry (26, 28) for commencing the precharge phase of the first phase domino logic circuit at a third time (t2.sub.b) following the second time. The third time corresponds to the latest of a plurality of events. A first of the plurality of events is the clock signal transitioning from the second state to the first state. A second of the plurality of events is the discharge path of the second phase domino logic circuit having sufficient time following a beginning of the evaluate phase of the second domino logic circuit to conduct to cause the voltage at the precharge node of the second phase domino logic circuit to transition to a level sufficient to trigger the output of the inverter of the second phase domino logic circuit. sequential elements from which at least one output is generated. The true logic evaluation comprises a logic evaluation of the current states and nodes of the circuit including inputs, intermediary sections, and outputs. The logic evaluation determines whether transferring the clock signal in response to its current state can lead to a desired change of state for the digital logic circuit.

0021Therefore, a need exists for a logic circuit that exhibits lower gate capacitance losses in response to the activity of a dynamic clock signal, wherein overall circuit operating power may be reduced. The present invention satisfies those needs, as well as others, and overcomes the deficiencies of previously developed dynamic clocking methods and circuits.

BRIEF SUMMARY OF THE INVENTION

0022The present invention comprises an apparatus for reducing power consumption within digital logic circuits which may be utilized in combinatorial and/or sequential logic circuits. By way of example, and not of limitation, by reducing the relative activity of the clock input signal as applied to the clock inputs of the digital logic circuits, the capacitive loading is thereby reduced with attendant reductions in power consumption. The invention recognizes that logic drcuits are typically only subject to changing output conditions for a small number of the given input and intermediary conditions for which a clock signal transition may be received.

0023It will be appreciated that a number of prior art circuits (i.e. dynamic combinatorial circuits) use the receipt of a clock signal to reduce the gate loading and associated propagation delays for each data input according to the present invention, a level shifter circuit, such as a transistor with a limited bias, is utilized to reduce the signal levels of the clock signal passed through the first logic circuit to the second, wherein power dissipation and clock signal loading may be further reduced. By way of example, level shifting may be accomplished by using a transistor configured with a predetermined bias voltage (i.e. for FET devices) or current (i.e. for Bipolar devices) to limit the clock signal current flow. Additionaly, the present invention modulates when the clock signal is subject to the loading imposed by input and intermediate circuit elements which are driven by the clock Clock signal availability is modulated by a clock path control circuit based on whether transferring the clock signal through the clock path control circuit to the logic circuit would lead to a desired (productive) change of state. In particular, the clock signal js blocked by the clock path control circuit if a true logic evaluation of the states within the digital logic circuit indicate that transferring the clock signal through the clock path control circuit would not produce a desired change of state, such as an output state change, or advancing the internal state of a sequential logic circuit (i.e. multi-stage counter).

0024It will be appreciated that a digital logic circuit as defined herein comprises at least one input connected to intermediary circuitry that inludes combinatorial and/or sequential elements from which at least one output is generated. The true logic evaluation comprises a logic evaluation of the current states and nodes of the circuit including inputs, intermediary sections, and outputs. The logic evaluation determines whether transferring the clock signal in response to its current state can lead to a desired change of state for the digital logic circuit.

0025More specifically, in considering an example of a combinatorial digital logic circuit, the clock signal is blocked, such as by a pass transistor, if the current combination of input states would not alter the current output state upon receipt of a clock transition. With regard to a sequential logic circuit, the clock signal is blocked if receipt of the clock signal could not contribute to the advancement of the state of the sequential circuit from its current input and intermediary states toward a new output state. The phrase "toward a new output state" as used herein means that the data output states may not necessarily change, but that internal state changes may arise that subsequently may lead to a new output state. In considering the case of a simple data flip-flop implemented with event driven logic according to the present invention, the clock signal would only be transferred to the flip-flop circuit from the clock path control circuit when the data input differs from the latched output.

0026Evaluation within the circuit may be performed in a number of alternative ways according to the present invention and can often be implemented with minor circuit overhead. It should also be appreciated that effective power reductions may be achieved even if the clock is blocked for only a portion of the circuit states for which receipt of the clock signal would prove unproductive, and thereby not lead to a desired change of circuit state.

0027According to an aspect of the present invention, the clock input of a circuit is blocked for a portion of the states to which the circuit is subject, such as in response to conditions at the circuit input, output, or intermediate nodes therein. As a result the circuit, or circuit stage, operates at a lower power dissipation because a number of gates tied to the clock input signal are no longer subject to capacitive charge and discharge cycling for each clock transition being received. It should also be appreciated that power savings can also accrue from eliminating state changes within intermediate circuits that do not advance the state of the circuit toward an output transition. An example of such intermediary state changes being the inverted and delayed clock signal <i>CLKD-bar</i> described in relation to <figref idref="f0003">FIG. 3</figref>, in addition with other associated intermediary charging and discharging that do not result in an output transition.

0028The invention may be generally described in terms of an apparatus for reducing power consumption in a clocked digital logic circuit wherein a clock path control circuit is configured for blocking the passage of a clock signal to the clocked digital logic circuit as a function of the feedback received. For example, the clock may be passed only when the feedback received indicates that a desired change in state in the data output will arise in response to the receipt of the clock signal for a given data input of the clocked digital logic circuit. The clock path control circuit generally comprises a switching circuit for selectively blocking the clock signal following modulation provided by a detection circuit that is responsive to conditions at the inputs of the clocked digital logic circuit. In this way the clock signal is blocked upon detecting that a change of state within the clocked digital logic circuit could not arise in response to the receipt of the clock signal, whereby blocking of the clock signal has no effect on circuit state while it lowers power dissipation and loading of the clock signal.

0029According to another aspect of the invention, the invention may be implemented within a dynamic logic circuit comprising a first logic circuit, a second logic circuit receiving a clock signal through the first logic circuit, and a means for blocking passage of a clock signal within the first logic circuit to the second logic circuit as a function of feedback received from the second logic circuit. The clock signal typically controls the selection of precharge and evaluation phases within the second logic circuit using complementary circuits, which may be considered a gating circuit connected to data inputs. The clock signal being only passed to the second logic circuit if it can effect a desired change of state within the second logic circuit. The second logic circuit may comprise a combinatorial and/or sequential logic circuit. Both the first and second logic circuit may comprise a plurality of interconnected switching elements configured for executing a logic function. The means for blocking the clock signal may comprise a switching circuit and a detection circuit. The switching circuit enters a high impedance mode to block the clock signal when its state is modulated by the detection circuit which determines that receipt of the clock would not alter the output of the second logic circuit. Switching elements and switching circuits are typically implemented as one or more transistors, such as within an integrated circuit in which the transistors are fabricated using one or more predetermined device fabrication processes (i.e. NMOS, CMOS, and so forth). The clock signal is preferably blocked by isolating the clock signal by a pass transistor which enters a high impedance mode while pulling the clock input of the second logic circuit to a given nominal state to prevent sensing a false clock signal from a floating clock input.

0030A level shifter circuit, such as a transistor with a limited bias, is utilized to reduce the signal levels of the clock signal passed through the first logic circuit to the second, wherein power dissipation and clock signal loading may be further reduced. By way of example, level shifting may be accomplished by using a transistor configured with a predetermined bias voltage (i.e. for FET devices ) or current (i.e. for Bipolar devices) to limit the clock signal current flow.

0031The detector which modulates the state of clock signal blocking determines whether to block, or pass, the clock signal based on the condition of one or more intermediate or output states found within the second logic circuit, or a comparison between inputs, outputs, and intermediate states. A switching circuit may be activated by the detector in view of the circuit states, comparisons, or relationships therein, to pass the clock signal, such as through a low impedance active state of a transistor, to the second logic circuit.

0032In considering a generally combinatorial dynamic logic circuit, the invention can be implemented as a circuit comprising: (1) at least one transistor for receiving a data signal from at least one data input; (2) a gating circuit coupled to the output of the transistor which is configured for receiving a clock signal on a clock input to trigger a change of state in a data output based on the data input; and (3) a clock blocking circuit configured to selectively prevent the passage of the clock signal to the gating circuit in response to the state of the data output. The device may be configured with a single data input, such as to a single transistor for implementing inverting and non-inverting buffers, or may utilize multiple data inputs according to a logic function relating the multiple inputs. It will be appreciated that a number of different combinatorial logic functions may be implemented according to the present invention including AND gate, NAND gate, OR gate, NOR gate, XOR gate, coincidence gate, and combinations thereof in response to the relationships between the data inputs.

0033It should be appreciated that the invention may be utilized with combinatorial circuits, sequential circuits, or combinations thereof. In considering the case of a sequential circuit, a dynamic logic circuit according to the invention may generally comprise: (1) a bistable circuit having at least one data output responsive to a data signal received on a data input when triggered by a clock signal transition on a clock input; wherein the bistable circuit is configured for retaining and generating a logic state as previously set in response to the state of the data input as triggered (loaded) in response to the previous receipt of a clock input transition; and (3) a clock path control circuit coupled to the bistable circuit and configured to block the receipt of the clock signal transition in response to the relationship between the signals at the data input and the data output. One relationship is that of equivalence, such as found within a D flip-flop, wherein the clock is not passed to the bistable circuit if the input matches the output. Similar flip-flops, or other forms of latches, may be implemented using event driven logic as described herein which provides power savings and reduces clock signal loading.

0034It should also be appreciated that clock path control circuits according to the invention may be utilized with complex combinatorial and sequential circuit sections. In these cases feedback may be received from data inputs, intermediary states, data outputs, and relationships between various inputs, outputs and intermediary states, for selecting the modulation of the clock signal received by the complex combinatorial and sequential circuit section.

0035The inventive circuits described herein may be implemented on circuits fabricated by a number of different process technologies, and within a variety of circuit types including discrete logic elements, gate arrays, programmable logic, microprocessors, memories, digital signal processors, and other circuits utilizing digital logic circuitry, including digital circuits incorporated within power circuitry, analog devices, MEMs devices, and so forth.

0036An aspect of the invention is to provide a logic circuit architecture exhibiting reduced levels of power dissipation.

0037Another aspect of the invention is to provide a logic circuit power reduction method that may be readily implemented within conventionally fabricated circuits.

0038Further aspects and advantages of the invention will be brought out in the following portions of the specification and claims, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.

BRIEF DESCRIPTION OF THE DRAWINGS

0039The invention will be more fully understood by reference to the following drawings which are for illustrative purposes only: <ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">FIG. 1</figref> is a schematic diagram of a conventional four input AND gate implemented in static CMOS logic.</li><li><figref idref="f0002">FIG. 2</figref> is a schematic diagram of a conventional four input AND gate implemented in dynamic logic.</li><li><figref idref="f0003">FIG. 3</figref> is a schematic diagram of a conventional flip-flop structure (D-FF) implemented in dynamic logic.</li><li><figref idref="f0004">FIG. 4</figref> is a schematic diagram of a single input logic circuit stage, shown utilizing a clock path control circuit to reduce losses associated with the charging and discharging of gate capacitances.</li><li><figref idref="f0005">FIG. 5</figref> is a schematic diagram of a single input circuit stage according to an embodiment of the present invention, shown utilizing a clock path control circuit as depicted in <figref idref="f0004">FIG. 4</figref> with additional circuitry for controlling clock signal amplitude.</li><li><figref idref="f0006">FIG. 6</figref> is a schematic diagram of a four input AND gate , shown utilizing a clock path control circuit to reduce losses associated with the charging and discharging of gate capacitances.</li><li><figref idref="f0007">FIG. 7</figref> is a schematic diagram of an event driven flip-flop circuit shown utilizing a first type of clock path control circuits to reduce losses associated with the charging and discharging of gate capacitances.</li><li><figref idref="f0008">FIG. 8</figref> is a timing diagram for the flip-flop circuit depicted in <figref idref="f0007">FIG. 7</figref>.</li><li><figref idref="f0009">FIG. 9</figref> is a schematic diagram of an event driven flip-flop circuit shown utilizing an alternative clock path control circuit to reduce losses associated with the charging and discharging of gate capacitances.</li></ul>

DETAILED DESCRIPTION OF THE INVENTION

0040Referring more specifically to the drawings, for illustrative purposes the present invention is embodied in the apparatus generally shown in <figref idref="f0005">FIG. 5</figref> . It will be appreciated that the apparatus may vary as to configuration and as to details of the parts, without departing from the basic concepts as disclosed herein.

0041<figref idref="f0004">FIG. 4</figref> exemplifies a one input event driven logic circuit 110, similar to the four input AND domino combinatorial logic circuit shown in <figref idref="f0002">FIG. 2</figref>. Logic circuit 110 has a logic input 112, clock input 114, and output 116. A clock path control circuit 118 is shown for selectively blocking clock signal 114 from a generally conventional dynamic logic circuit 120 in response to a true logic evaluation.

0042The general operation of the present device involves cycling the logic circuit through clock phases which include precharge and evaluation phases while an active clock signal is being received. The clock signal is preferably received by complementary circuits, typically complementary transistors, that charge a circuit node from a first circuit during precharge, and then allow the charge to be dissipated or held on the node during said evaluation phase through a second circuit in response to the received clock signal.

0043Considering the case in which output 116 is held <i>high</i> as clock 114 transitions <i>low</i> to commence a precharge phase. Transistor 126 switches on while transistor 128 switches off, causing charge buildup on node A regardless of the state of input 112. Node <i>A</i> charges up to the logic threshold of inverter 132 (overcoming the opposing current provided by inverter 134), whereupon inverter 132 switches states to drive output 116 to low, thereby switching off pass transistor 122 to block clock signal transfer and switching-on pull up transistor 124 to hold the clock input of the logic circuit high. The evaluation phase has therefore been entered automatically regardless of the true state of clock signal <i>CLK</i> 114.

0044Within the evaluation phase, transistor 128 is switched-on and transistor 126 is switched-off, wherein the setting of input 112 determines the output 116 in response to the precharge. Specifically, a <i>high</i> on input 112 discharges node <i>A</i> resulting in a <i>high</i> on output 116, while a <i>low</i> on input 112 allows node A to remain at a <i>high</i> level of precharge, as retained by inverter 134 ("keeper"), wherein the output 116 remains <i>low</i> holding clock pass transistor 122 in an off state.

0045It will be appreciated that logic circuit 120 is isolated from transitions of clock signal 114 for as long as input 112 remains low, thereby matching output 116. Within this state, if input 112 should transition to <i>high</i> then node <i>A</i> will be discharged causing a transition of output 116 to <i>high,</i> thereby unblocking clock signal 114 allowing a subsequent precharge phase. It will be appreciated that reduced power consumption has been achieved in a number of ways from using the selective blocking of the clock signal.

0046<figref idref="f0005">FIG. 5</figref> depicts, according to the invention, a clock path control circuit 118 including means for reducing the signal amplitude of clock signal 114, to reduce capacitive power losses when the clock is active. By way of example, the means for reducing clock amplitude is depicted as transistor 152 whose gate is connected to reference voltage V_ref. It should be appreciated that any convenient level shifting circuit may be utilized within the invention for reducing the signal amplitude of clock signal 114.

0047<figref idref="f0006">FIG. 6</figref> exemplifies an implementation of event-driven dynamic digital logic circuit 170, in which at least a portion of the unnecessary power consumption associated with unproductive clock activity is eliminated. The dynamic logic portion of this circuit is the same as that described for <figref idref="f0002">FIG. 2</figref>, however, it has been modified by adding a clock path control circuit according to the present invention. The resultant event driven digital logic circuit 170 has logic inputs 172, a clock signal <i>CLK</i> 174, and an output 176. A clock path control circuit 178 regulates the communication of clock signal <i>CLK</i> 174 to logic circuit 180. Clock path control circuit 178 is depicted with a clock pass transistor 182 and pull up transistors 184, 186. Clock signal <i>CLK</i> 174 is received within logic circuit 180 by complementary transistors 188, 190. Input signals 172 are received by transistors 192, 194, 196, 198 in a series "AND" function configuration. Circuit output 176 is driven by inverter 200 with a keeper circuit 202.

0048In the precharge phase (when <i>CLK</i> is <i>low</i>) node A and output <i>OUT</i> 176 are precharged at <i>V_DD(high)</i> and <i>V_SS (low),</i> respectively. Therefore, node <i>B</i> is precharged high through transistor 186. When all inputs are <i>high</i> at the rising edge of clock signal 174, then node A is discharged to <i>low</i> and output <i>OUT</i> 176 goes to <i>high</i> as in a conventional dynamic logic circuit. After node A is discharged to <i>low,</i> node <i>B</i> is maintained <i>high</i> by transistor 184 to eliminate a floating condition at node <i>B</i>. Transistor 184 provides limited conductance (i.e. such as by virtue of reduced transistor width) allowing sufficient current to flow for retaining the voltage at node <i>B</i> without hindering precharge operations. As clock signal <i>CLK</i> 174 transitions low into precharge mode, node <i>B</i> is discharged to a <i>low</i> state because transistor 182 is switched-on. Therefore, in relation to the evaluation phase of the clock, the operation of this event driven circuit is the same as that of conventional dynamic logic, with no speed penalty being incurred.

0049When any one of the inputs 172 are held <i>low</i> upon entry into the evaluation phase (clock transitioning back to <i>high)</i> node <i>A</i> will not be discharged and will remain <i>high</i> at the precharge voltage <i>(V_DD)</i>, while the output <i>OUT</i> 176 will be driven <i>low.</i> Consequently, the clock input is blocked and node B is maintained high. Therefore, transistor 186 is held active while transistors 182, 184 are off.

0050Under these conditions with pass transistor 182 off, as clock signal <i>CLK</i> 174 transitions to <i>low,</i> no discharging and charging of gate capacitances will occur as a result of the clock transitions, thereby saving power over a conventional implementation of dynamic logic. It should be appreciated that clock signal <i>CLK</i> 174 is only communicated to the dynamic logic after all inputs of the combination are satisfied (for the depicted "AND" function) and true logic evaluation is performed. The true logic evaluation determines whether a true change in state can arise in response to a clock transition. A true change in state is a change in state that is necessary for the functioning of the circuit, precluding incidental changes of state that occur in response to the clock that are otherwise unproductive. As a result of limiting communication of the clock signal, precharge cycles only occur in response to logic inputs 172 satisfying the functional condition. It should be appreciated that the circuit is not subject to the unproductive charging and discharging of gate capacitances tied to clock signal <i>CLK</i> 174 which wastes device power. For the remaining input combinations, the clock path to node <i>B</i> remains blocked (isolated) with no power being consumed by clock signal <i>CLK</i> 174 as it transitions between precharge and evaluation cycles.

0051By eliminating unnecessary clock power consumption, overall power consumption is reduced within this dynamic circuit 170 modified for being event driven according to the invention. The amount of power savings for the event driven circuit depends on the depth of stacking within the circuit. For example, more power may be saved on a four input AND circuit than with a three input AND circuit. It should also be appreciated that power is saved not only in a single logic stage but also in a logic block. For example, only about twenty percent (20%) of the logic stages are activated in a typical 32-bit adder for a typical input combination. In the adder implemented with conventional dynamic logic, all logic stages consume clock power. By contrast, an adder implemented with the event-driven dynamic logic according to the invention operates at reduced power levels because only the active twenty percent (20%) of the logic stages consume clock power. Therefore, overall power consumption can be reduced by implementing logic circuits with the event driven logic of the present invention. For the example case of a 32-bit adder, approximately eighty percent (80%) of the clock power is saved using event driven logic. Because clock power consumption accounts for about half of the total operating power consumption within a circuit, it follows that about a forty percent (40%) total reduction in operating power consumption can be provided by utilizing event driven logic circuits according to the present invention.

0052The event driven logic of the present invention may be applied to sequential logic circuits in addition to the combinatorial logic described. By way of example, the event driven logic of the invention may be applied to create an event driven flip-flop, in which unnecessary clock power consumption is eliminated. The basic premise, as applied to the flip-flop circuit, eliminates unnecessary clock power consumption when the data held at the input is identical with the latched data within the flip-flop from a previous cycle. Selective clock blocking within the present invention may be generalized wherein if the conditions of the digital logic circuit indicate that a desired state change will not arise as a result of clock transitions, then the clock signal may be blocked from the digital logic circuit to save power.

0053<figref idref="f0007">FIG. 7</figref> exemplifies a flip-flop circuit 210 that captures data at the falling or rising edge of the clock. The data flip-flop is but one example of a sequential logic circuit that may be implemented using event driven logic to reduce power consumption and the method may be generally applied to most or all forms of sequential logic circuitry.

0054The circuit blocks transitions of the clock signal to a logic circuit unless evaluation of the states in that logic circuit indicate that a state change within the circuit is pending in response to circuit conditions. Typically, the clock signal blocking is performed in response to the relationship between the inputs and/or outputs within a simple combinatorial or sequential logic circuit, while more complex circuits could require intermediary state evaluation. In the case of a data "D" flip-flop, the evaluation determines if latched data is the same as incoming data.

0055Consider the situation in which the latched data differs from data input <i>D</i> 214, for example the latched data is <i>low</i> and the data input <i>D</i> 214 is held <i>high.</i> In this case transistor 224 is off while transistor 228 is on. Receiving the inverted data is transistor 236 in an on-state while transistor 234 is switched-off. Since the latched data is <i>low, Q</i> is low and <i>Q-bar</i> is <i>high,</i> respectively. Since <i>Q-bar</i> is <i>high,</i> transistor 226 is off while transistor 230 is switched-on. Since <i>Q</i> is <i>low,</i> transistor 238 is switched-on and transistor 232 is switched-off. Therefore, Y1 is held <i>high</i> while transistor 240 is switched-off, with transistor 242 being on.

0056When CLK 212 is <i>low</i> (precharge phase), node <i>X1</i> is discharged to <i>low</i> through transistors 228 and 230, while transistor 244 is switched-on. After the previous circuit operation, node <i>X2</i> and <i>Y2</i> are set <i>low</i> by transistor 246 and transistor 242, respectively, with <i>X2-bar</i> being set <i>high.</i> Therefore, through inverters 248, 250 the transistor 256 is switched-off. The output of transistor 240 is directed to transistor 258 which is switched-off. It will be appreciated that inverter pairs 248 and 250 along with 252, 254 prevent nodes X2 and Y2 from floating, and retain those nodes low. The latched data at <i>Q</i> and <i>Q-bar</i> are isolated from the evaluation circuit (left part). With transistor 244 switched-on, as clock signal CLK 212 goes <i>high</i> node <i>X2</i> and <i>X2-bar</i> transition to <i>high</i> and <i>low</i>, respectively, and transistor 256 is switched-on. Therefore, the data at node <i>Q</i> is changed from <i>low</i> (previous data) to <i>high</i> (new data).

0057Since transistor 240 is switched-off and node Y2 is maintained <i>low</i> through pull-down transistor 242, then transistor 258 is switched-off and there is no static current. After the output data is changed to <i>high,</i> transistor 238 is switched-off and transistor 232 is switched-on. Since <i>Q-bar</i> is changed to <i>low</i>, transistor 226 becomes switched-on while transistor 230 is switched-off. It should be noted, however, that <i>CLK</i> is still high and node <i>Y1</i> is floating when input <i>D</i> is changed to low (an "invalid" data transition) so a latch (inverter 252 and 254) is necessary to keep node <i>Y2</i> low. Therefore, node <i>X1</i> goes to <i>high</i> and transistor 244 is switched-off while pull down transistor 246 is switched-on. Hence, node <i>X2</i> is de-coupled from clock signal CLK 212 and discharged to <i>V_SS (low)</i> through transistor 246. Node <i>X2-bar</i> is set <i>high</i> to turn off transistor 256. As a result, the latched outputs at <i>Q</i> and <i>Q-bar</i> are isolated from the remainder of the circuit.

0058Subsequent to output <i>Q</i> 264 assuming a <i>high</i> state, if data input <i>D</i> 214 is still in the same state as in the previous cycle, node <i>Y1</i> remains <i>high</i> in response to transistor 236 while transistor 240 is switched-off. Node <i>Y2</i> is maintained <i>low</i> by transistor 242 wherein transistor 258 is switched-off. Node <i>X1</i> is set <i>high</i> by transistor 226 since <i>Q-bar</i> is <i>low</i> and transistor 244 is switched-off. Nodes <i>X2</i> and <i>X2-bar</i> remain <i>low</i> and <i>high,</i> respectively and transistor 256 is switched-off. Since transistors 244 and 240 are switched-off even after <i>CLK</i> 212 goes to <i>high,</i> it will be appreciated that charging and discharging of the gate capacitance, as shown in the conventional flip-flop, does not occur within the event-driven flip-flops.

0059A timing diagram for the event driven data flip-flop when input D is high is depicted in <figref idref="f0008">FIG. 8</figref>. Relationships are highlighted as the clock enters the evaluation phase with the X and Y nodes and the associated <i>Q</i> and <i>Q-bar</i> outputs.

0060Unnecessary clock power consumption within the present event driven D flip-flop is eliminated when the latched data is the same as the input data, thereby reducing overall power consumption. Compared to the conventional flip-flop, circuit operating speed can be improved by virtue of using a non-stacked circuit structure. In the conventional flip-flop of <figref idref="f0003">FIG. 3</figref>, node <i>X</i> is discharged through three stacked transistors (92, 94 and 96, or 100, 102 and 104). Typically, data is set up earlier than the clock to meet a predetermined minimum set-up time. Therefore, referring once again to <figref idref="f0007">FIG. 7</figref>, before <i>CLK</i> goes to <i>high,</i> either transistor 244 or transistor 240 is switched-on. When <i>CLK</i> goes <i>high,</i> the CLK signal rapidly propagates through non-stacked logic, inverter 248 and transistor 256 or 258. Therefore, the data latching speed can be improved by a factor of about thirty percent (30%).

0061When data input <i>D</i> 214 is held <i>low</i> after <i>Q</i> and Q-<i>bar</i> have changed to <i>high</i> and <i>low</i>, respectively, then node <i>Y1</i> is discharged to <i>V_SS (low)</i> through transistor 232 and transistor 234, when <i>CLK</i> is <i>low</i> and transistor 240 is switched-on. Node <i>X1</i> is set <i>high</i> through transistor 224, and transistor 244 is switched-off. When clock signal <i>CLK</i> 212 transitions to <i>high,</i> node <i>Y2</i> transitions to <i>high</i> and transistor 258 switches on. Node <i>Q</i> is thereby discharged to <i>V_SS</i> (low) and <i>Q</i>-bar becomes <i>high.</i> Upon <i>Q</i> going <i>low,</i> node <i>Y1</i> transitions to <i>high</i> and transistor 240 is switched-off. Node <i>Y2</i> is discharged to <i>V_SS</i> and transistor 258 is switched-off. When Q-bar goes <i>high,</i> transistor 230 goes <i>high</i> and node <i>X1</i> goes <i>low</i> when clock input <i>CLK</i> 212 goes to <i>low</i> when the data input D 214 is <i>high.</i> In this case, transistor 244 is switched-on and the output is changed at the rising edge during the following cycle.

0062In summary, the event driven data flip-flop is composed of a data latch portion (inverters 260 and 262), the driver portion (transistors 256 and 258), the clock path control portion (transistors 224, 226, 228 and 230 for input data <i>D</i> 214 being <i>high</i> and transistors 236, 238, 232 and 234 for input data <i>D</i> 214 being <i>low</i>), and the driver control portion. The clock path control portion receives information of the latched data (<i>Q</i> or <i>Q-bar</i>) and input data <i>D</i> 214 and is activated only when the latched data and input data are different from one another so as to eliminate unnecessary clock power consumption.

0063Following a <i>low</i> data input <i>D</i> 214 being latched at <i>Q</i>, only a transition of data input <i>D</i> 214 to <i>high</i> causes the clock path control circuit to respond by allowing clock transitions to pass, and thereby enabling the driver to change the output <i>Q</i> 264 from <i>low</i> to <i>high</i>.

0064<figref idref="f0009">FIG. 9</figref> is a further example of event-driven flip-flops 270. This circuit of event driven sequential devices utilizes different clock path control circuits 280, 282 to increase the set-up time margin. In the previous event driven flip-flop of <figref idref="f0007">FIG. 7</figref> the data needed to be set up earlier than the clock, as in a typical design, to assure safe circuit operation. However, in the flip-flop shown in <figref idref="f0009">FIG. 9</figref>, the data input <i>D</i> 274 may be set up later than the clock signal <i>CLK</i> 272 by an amount given as one NOR-gate delay. This circuit can therefore operate safely despite a negative set-up time condition. This feature is particularly beneficial in speed critical applications, such as constructing faster pipeline architectures using what is generally referred to as a "time-borrowing" technique.

0065A significant benefit of event-driven (ED) logic is the elimination of unnecessary circuit and clock power consumption by using clock path control circuits as described herein. When clock path control circuits are applied to dynamic logic, the clock signal is only utilized for precharging internal nodes in response to a positive evaluation of the logic states in anticipation of a useful (productive) state change. In applying event-driven (ED) logic to flip-flops, the clock path control circuits enable a path to change the output data only when the data input does not correspond with the data latched from a prior cycle. In general, the clocking is only passed through to the logic circuit when a change of state of the logic circuit may arise, as determined during the evaluation phase. The determination performed during the evaluation phase may take into account any of the relationships between the input signals and both the intermediate and output states of the logic circuit.

0066The present claims define the invention.