Plasma display device, driving method and address electrode driving circuit for the same with energy recovery circuit

<u>BACKGROUND OF THE INVENTION</u>

(a) Field of the Invention

The present invention relates to a driving method of a plasma display panel (PDP) and a plasma display device. More specifically, the present invention relates to an address driving circuit for applying address voltages.

(b) Description of the Related Art

The PDP is a flat display that uses plasma generated via a gas discharge process to display characters or images, and, depending on its size, tens to millions of pixels are provided thereon in a matrix format PDPs are categorized as DC PDPs and AC PDPs, according to the supplied driving voltage waveforms and discharge cell structures.

DC PDPs have electrodes exposed in the discharge space, and they allow a current to flow in the discharge space while the voltage is supplied. Therefore they problematically require resistors for current restriction. AC PDPs, on the other hand, have electrodes covered by a dielectric layer, and capacitances are naturally formed to restrict the current. Furthermore, in AC PDPs the electrodes are protected from ion shocks during discharge. As a result, AC PDPs have a longer lifespan than DC PDPs.

Fig. 1 shows a perspective view of an AC PDP.

As shown, a scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, are provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 are installed on a second glass substrate 6. Barrier ribs 9 are formed in parallel with the address electrodes 8 on the insulation layer 7 between the address electrodes 8, and phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first and second glass substrates 1 and 6 having a discharge space 11 between them are provided facing each other so that the scan electrode 4 and the sustain electrode 5 may respectively cross the address electrode 8. The address electrode 8 and discharge space 11 formed at a crossing part of the scan electrode 4 and the sustain electrode 5 form a discharge cell 12.

Fig. 2 shows a PDP electrode arrangement diagram.

As shown, the PDP electrode has an m x n matrix configuration, and in detail, it has address electrodes A₁ to A_m in the column direction, and scan electrodes Y₁ to Y_n and sustain electrodes X₁ to X_n in the row direction, alternately. The discharge cell 12 shown in Fig. 2 corresponds to the discharge cell 12 shown in Fig. 1.

In general, a method for driving the AC PDP includes a reset period, an address period, and a sustain period.

In the reset period, the states of the respective cells are reset to address the cells smoothly. In the addressing period, the cells to be turned on and the cells not to be turned on in a panel are selected, and wall charges are accumulated in the cells to be turned on (i.e., the addressed cells). In the sustain period, discharge is performed to turn on the addressed cells and actually display pictures.

Because a discharge space between a scan electrode and a sustain electrode, as well as a discharge space between a surface on which an address electrode is formed and a surface on which scan and sustain electrodes are formed, each operates as a capacitive load (referred to as panel capacitors hereinafter), capacitance exists on the panel. Hence, in addition to power for addressing, reactive power is also needed to apply waveforms for addressing. An address driving circuit of the PDP therefore includes a power recovery circuit for recovering the reactive power and re-using the same, as disclosed from the power recovery circuit by L.F. Weber in U.S. Patent Nos. 4,866,349 and 5,081,400.

A conventional power recovery circuit can restrict power consumption within a predetermined level when images that need high power consumption are displayed. However, the conventional power recovery circuit is also operated when images that need low power consumption are displayed. As a result, the power consumption of the conventional power recovery circuit is higher than the power consumption of a circuit that does not recover power when images that need only low power consumption are displayed. For example, in the display pattern in which all discharge cells are on, the addressing voltage is continuously applied to the address electrodes. Therefore, the power recovery operation need not be performed in this display pattern. However, power consumption is higher than necessary because the conventional power recovery circuit performs power recovery in this display pattern.

The conventional power recovery circuits fail to recover 100% of the reactive power during the power recovery process because of switching losses of the transistors or parasitic components of the circuit. Accordingly, the power recovery operation cannot adjust the voltage of the panel capacitor to a desired voltage. Hence, the switch performs hard switching.

<u>SUMMARY OF THE INVENTION</u>

The present invention provides an address driving circuit for reducing power consumption.

The present invention provides an address driving circuit for varying a power recovery operation according to the switching variation of an address selecting circuit.

In one aspect of the present invention, a plasma display device comprises: a panel including a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction intersecting the first direction; a first driving circuit sequentially applying a first voltage to the first electrodes; a selecting circuit coupled to the second electrodes for selecting second electrodes to which a second voltage will be applied from among the second electrodes; a second driving circuit including at least one inductor having a first terminal coupled to the selecting circuit and a capacitor coupled to a second terminal of the inductor for applying the second voltage to the second electrode selected by the selecting circuit; and a controller selecting an operating mode of the second driving circuit in response to a video signal. When the operating mode is a first mode, the second driving circuit applies the second voltage to the selected second electrode after charging a capacitive load formed by the first electrode and the selected second electrode through the capacitor and the inductor, and discharges the capacitive load through the capacitor and the inductor, thereby reducing the voltage of the selected second electrode, and a residual voltage after the capacitive load is discharged is reduced by an operation of the selecting circuit. When the operating mode is a second mode, the second driving circuit directly applies the second voltage to the selected second electrode.

In one exemplary embodiment, the controller selects the operating mode to be the first mode when the number of first discharge cells is more than a predetermined value in at least one subfield. The on/off state of the first discharge cell is different from that of the discharge cell adjacent to the first discharge cell in the first direction.

In another exemplary embodiment, the controller selects the operating mode to be the first mode when a summation of the number of first discharge cells and the number of second discharge cells is more than a predetermined value in at least one subfield. The on/off state of the first discharge cell is different from that of the adjacent discharge cell in the first direction, and the on/off state of the second discharge cell is different from that of the adjacent discharge cell in the second direction.

In still another exemplary embodiment, the second driving circuit supplies a current to the capacitor before discharging the capacitive load in the first mode. The current supplied to the capacitor may be supplied from the voltage source supplying the second voltage.

In a further exemplary embodiment, in the first mode, the second driving circuit operates in the following order: a first period during which the capacitive load is charged through the inductor and the voltage charged in the capacitor; a second period during which the selected second electrode of the capacitive load is substantially maintained at the second voltage through the voltage source supplying the second voltage; a third period during which a current is supplied to the inductor and the capacitor by using the voltage source; and a fourth period during which the capacitive load is discharged by using the voltage charged in the capacitor and the inductor.

In yet a further exemplary embodiment, the second driving circuit further includes a first switch and a second switch coupled between the second terminal of the inductor and the capacitor or between the first terminal of the inductor and the selecting circuit in parallel; and a third switch coupled between a voltage source supplying the second voltage and the selecting circuit. The first switch, the second switch and the third switch may be transistors respectively including a body diode, and the second driving circuit may further include a first diode formed in the opposite direction of the body diode of the first switch in the path formed by the capacitor, the first switch, and the inductor; and a second diode formed in the opposite direction of the body diode of the second switch in the path formed by the capacitor, the second switch, and the inductor.

In a still further exemplary embodiment, in the first mode, the second driving circuit operates in the following order: a first period during which the first switch is turned on, a second period during which the third switch is turned on, a third period during which the second switch and the third switch are turned on, and a fourth period during which the second switch is turned on. In addition, in the second mode, the first switch is turned on, and the second switch and the third switch are turned off.

Yet another exemplary embodiment includes a first inductor and a second inductor, and the second driving circuit charges the capacitive load through the first inductor and discharges the capacitive load through the second inductor.

In still another exemplary embodiment, the inductor on the path of charging the capacitive load is the same as the inductor on the path of discharging the capacitive load.

In a further exemplary embodiment, the selecting circuit includes a plurality of first switches respectively coupled between the second electrodes and the first terminal of the inductor, and a plurality of second switches respectively coupled between the second electrodes and a voltage source for supplying a third voltage. The discharge cells to be turned on may be selected by the second electrode coupled to the turned-on first switch and the first electrode to which the first voltage is applied. The second driving circuit may operate in the second mode when the first switches of the selecting circuit are continuously turned on while the first voltage is sequentially applied to the first electrodes.

In another aspect of the present invention, a driving method of a PDP on which a plurality of first electrodes and second electrodes are formed is provided, and a capacitive load is formed by the first and second electrodes. The driving method includes: selecting operating modes in the respective subfields from a video signal; selecting the first electrodes to which a first voltage will be applied among the first electrodes; and applying a second voltage to the first electrodes that are not selected. When the operating mode is a first mode, the driving method further includes: increasing a voltage of the selected first electrode through a first inductor having a first terminal coupled to the first electrode; substantially maintaining a voltage of the selected first electrode at the first voltage through a first voltage source supplying the first voltage; supplying a current to a second inductor having a first terminal coupled to the first electrode while substantially maintaining a voltage of the selected first electrode at the first voltage; and reducing the voltage of the selected first electrode through the second inductor. When the operating mode is a second mode, the driving method further includes applying the first voltage to the first electrode selected through the first voltage source.

In one exemplary embodiment, in the first mode, a capacitor is coupled to a second terminal of the first inductor and a second terminal of the second inductor when the voltage of the first electrode is increased and reduced.

In another exemplary embodiment, the first and second inductors are the same.

In still another exemplary embodiment, the first and second inductors are different.

In a further exemplary embodiment, a third voltage is sequentially applied to the second electrodes. In addition, in the first mode, increasing a voltage of the first electrode selected through a first inductor having a first terminal coupled to the first electrode, substantially maintaining a voltage of the selected first electrode at the first voltage through a first voltage source supplying the first voltage, supplying a current to a second inductor coupled to the first electrode while substantially maintaining a voltage of the selected first electrode at the first voltage, and reducing the voltage of the selected first electrode through the second inductor are repeated each time the third voltage is applied to the second electrode. Furthermore, the voltage of the capacitor is varied according to a combination of a previously selected first electrode and a currently selected first electrode.

In still another aspect of the present invention, a plasma display device includes: a panel including a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction intersecting the first direction; a first driving circuit sequentially applying a first voltage to the first electrodes; a selecting circuit coupled to the second electrodes for selecting second electrodes to which data will be applied among the second electrodes; and a second driving circuit including at least one inductor coupled to the selecting circuit and a capacitor coupled to the inductor. The second driving circuit electrically intercepts between the inductor and the capacitor and applies a second voltage to the second electrodes selected by the selecting circuit when a total summation in a predetermined number of discharge cells of the data difference between two discharge cells adjacent in the second direction is less than a predetermined value. The second driving circuit charges and discharges a capacitive load formed by the second electrode selected by the selecting circuit and the first electrode by using the inductor and the capacitor, and applies the second voltage to the second electrode selected after charging the capacitive load when the total summation is more than the predetermined value.

In a further aspect of the present invention, a plasma display device comprises: a panel including a plurality of scan electrodes extending in a first direction and a plurality of address electrodes extending in a second direction intersecting the first direction; a first driving circuit sequentially applying a first voltage to the scan electrodes; a selecting circuit coupled to the address electrodes for selecting address electrodes to which data will be applied among the address electrodes; a second driving circuit coupled to the address electrodes selected through the selecting circuit; and a controller selecting an operating mode of the second driving circuit in response to a video signal. The second driving circuit comprises: at least one inductor having a first terminal coupled to the address electrodes; a first switch coupled between a voltage source supplying an address voltage and the address electrodes; a capacitor coupled to a second terminal of the inductor; and at least one second switch coupled between the second terminal of the inductor and the capacitor or between the inductor and the selecting circuit. When the operating mode is the first mode, the second driving circuit increases and reduces a voltage of the address electrode by on/off operation of the second switch, and a residual voltage after the voltage of the address electrode is reduced to a predetermined voltage by an operation of the selecting circuit. When the operating mode is the second mode, the second driving circuit electrically intercepts between the capacitor and the inductor by turning off the second switch.

In yet a further aspect of the present invention, a plasma display device comprises: a panel including a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction intersecting the first direction; a first driving circuit sequentially applying a first voltage to the first electrodes; a selecting circuit coupled to the second electrodes for selecting second electrodes to which data will be applied among the second electrodes; and a second driving circuit including at least one inductor coupled to the selecting circuit and a capacitor coupled to the inductor. The inductor and the capacitor are electrically intercepted in a first operating mode, and the voltage of the capacitor is variable according to the display pattern in a second operating mode.

In a still further aspect of the present invention, a plasma display device comprises: a panel including a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction intersecting the first direction; a first driving circuit sequentially applying a first voltage to the first electrodes; a selecting circuit coupled to the second electrodes for selecting second electrodes to which data will be applied among the second electrodes; and a second driving circuit including at least one inductor coupled to the selecting circuit and a capacitor coupled to the inductor. In a first operating mode, resonance between the inductor and the capacitor is not generated. In a second mode, resonance between the inductor and the capacitor is generated, and the voltage of the capacitor is variable according to the display pattern.

<u>BRIEF DESCRIPTION OF THE DRAWINGS</u>

Fig. 1 shows a partial perspective view of an AC PDP.

Fig. 2 shows a PDP electrode arrangement diagram.

Fig. 3 shows a diagram of a plasma display device according to an exemplary embodiment of the present invention.

Fig. 4 shows an address driving circuit according to a first exemplary embodiment of the present invention.

Fig. 5 shows a reduced diagram of the address driving circuit of Fig. 4.

Fig. 6 shows a diagram of a dot on/off pattern.

Fig. 7 shows a diagram of a line on/off pattern.

Fig. 8 shows a diagram of a full white pattern.

Fig. 9 shows a timing diagram of a power recovery circuit of Fig. 5 for showing the dot on/off pattern.

<b>F</b>igs. 10A to 10H show current paths for respective modes of the address driving circuit of Fig. 5 following the timing of Fig. 9.

Fig. 11 shows a timing diagram of the power recovery circuit of Fig. 5 for showing the full white pattern.

Figs. 12A to 12D show current paths for respective modes of the address driving circuit of Fig. 5 following the timing of Fig. 11.

Fig. 13 shows an address driving circuit according to a second exemplary embodiment of the present invention.

Fig. 14 shows the power consumption in the address driving circuit according to the first exemplary embodiment of the present invention.

Fig. 15 shows a controller of a plasma display device according to a third exemplary embodiment of the present invention.

Fig. 16 shows the power consumption of the driving circuit according to the third exemplary embodiment of the present invention.

<u>DETAILED DESCRIPTION</u>

In the following detailed description, only an exemplary embodiment of the invention has been shown and described, simply by way of illustration of the best mode contemplated by the inventor(s) of carrying out the invention. As will be realized, the invention is capable of modification in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.

A plasma display device and a driving method of a PDP will be described in detail with reference to drawings.

Fig. 3 shows a brief diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in Fig. 3, the plasma display device includes a PDP 100, an address driver 200, a scan and sustain driver 300, and a controller 400. The scan and sustain driver 300 is illustrated as a single block in Fig. 3, but generally can be separated into a scan driver and a sustain driver.

The PDP 100 includes a plurality of address electrodes A₁ to A_m extending in the column direction, and a plurality of scan electrodes Y₁ to Y_n and a plurality of sustain electrodes X₁ to X_n extending in pairs in the row direction. The address driver 200 receives an address drive control signal from the controller 400, and applies address signals to the respective address electrodes A₁ to A_m for selecting discharge cells to be displayed. The scan and sustain driver 300 receives a sustain control signal from the controller 400, and alternately inputs sustain pulses to the scan electrodes Y₁ to Y_n and sustain electrodes X₁ to X_n to sustain the selected discharge cells. The controller 400 receives external video signals, generates an address drive control signal and a sustain control signal, and applies them to the address driver 200 and the scan and sustain driver 300.

In general, a single frame is divided into a plurality of subfields, the subfields are driven in the PDP, and the discharge cells to be discharged are selected from among the discharge cells. In order to select the discharge cells, a scan voltage is sequentially applied to the scan electrodes, and the scan electrodes to which no scan voltage is applied are biased with a positive voltage during the address period. The voltage for addressing (referred to as an address voltage hereinafter) is applied to the address electrodes that are passed through the discharge cells to be selected from among a plurality of discharge cells formed by the scan electrodes to which the scan voltage is applied, and a reference voltage is applied to the address electrodes that are not selected. In general, the address voltage uses a positive voltage and the scan voltage uses a ground voltage or a negative voltage so that the discharge is generated at the address electrodes to which the address voltage is applied and the scan electrodes to which the scan voltage is applied, and the corresponding discharge cells are selected. The ground voltage is frequently used as the reference voltage.

An address driving circuit in the address driver 200 will be described with reference to Fig. 4 with the assumption that the scan voltage is applied to the scan electrodes and the reference voltage is applied to the address electrodes as the ground voltage.

Fig. 4 shows an address driving circuit according to a first exemplary embodiment of the present invention.

As shown in Fig. 4, the address driving circuit includes a power recovery circuit 210 and a plurality of address selecting circuits 220₁ to 220_m. The address selecting circuits 220₁ to 220_m are respectively connected to a plurality of address electrodes A₁ to A_m, and each address selecting circuit has two switches A_H and A_L as a driving switch and a grounding switch, respectively. The switches A_H and A_L may be composed of a field-effect transistor (FET) having a body diode, or other types of switches that perform the same or similar functions as the FET. In Fig. 4, each of the switches A_H and A_L comprises an N-channel MOSFET. A first terminal (drain) of switch A_H is connected to the power recovery circuit 210 and a second terminal (source) of switch A_H is connected to the address electrodes A₁ to A_m, and when switch A_H is turned on, an address voltage V_a supplied by the power recovery circuit 210 is transmitted to the address electrodes A₁ to A_m. Switch A_L has a first terminal (drain) connected to the address electrodes A₁ to A_m and a second terminal (source) connected to the reference voltage (ground voltage), and when switch A_L is turned on, the ground voltage is transmitted to the address electrodes A₁ to A_m. In addition, switches A_H and A_L are not simultaneously turned on.

The address voltage V_a or the ground voltage is applied to the address electrodes A₁ to A_m when switches A_H and A_L of the address selecting circuits 220₁ to 220_m respectively connected to the address electrodes A₁ to A_m are turned on or off by a control signal as described above. In the address period, the address electrode to which the address voltage V_a is applied when switch A_H is turned on is selected, and the address electrode to which the ground voltage is applied when switch A_L is turned on is not selected.

The power recovery circuit 210 includes switches A_a, A_r, and A_f, inductors L₁ and L₂, diodes D₁ and D₂, and capacitors C₁ and C₂. Switches A_a, A_r, and A_f respectfully may be composed of an FET having a body diode or other types of switches that perform the same or similar functions as the FET. In Fig. 4, each of the switches A_a, A_r, and A_f is composed of an N-channel MOSFET. A first terminal (drain) of switch A_a is connected to a voltage source for supplying the address voltage V_a and a second terminal (source) of switch A_a is connected to the first terminal of switch A_H of the address selecting circuits 220₁ to 220_m. Capacitors C₁ and C₂ are connected in series between the voltage source for supplying the address voltage V_a and the ground voltage. The first terminal of switch A_H of the address selecting circuits 220_l to 220_m is connected to the first terminals of the inductors L₁ and L₂. Switch A_r and diode D₁ are connected in series between a common node of capacitors C₁ and C₂ and the second terminal of inductor L₁. Diode D₂ and switch A_r are connected in series between the second terminal of inductor L₂ and the common node of capacitors C₁ and C₂.

The connection sequence of inductor L₁, diode D₁, and switch A_r can be changed, and the connection sequence of inductor L₂, diode D₂, and switch A_f can be changed. Diodes D₁ and D₂ prevent current paths that may be caused by a body diode at the respective switches A_r and A_f, and diodes D₁ and D₂ can be eliminated if no body diode exists. A clamping diode D₃ can be connected between the second terminal of inductor L₁ and the voltage source for supplying the address voltage V_a so that the voltage applied to the address electrodes A₁ to A_m may not exceed the address voltage V_a during operation of the power recovery circuit 210. In the same manner, a clamping diode D₄ can be connected between the ground voltage and the second terminal of inductor L₂ so that the voltage applied to the address electrodes A₁ to A_m may not be less than the ground voltage.

A single power recovery circuit 210 is illustrated as connected to the address selecting circuits 220₁ to 220_m in Fig. 4. In addition, the address selecting circuits 220₁ to 220_m can be divided into a plurality of groups with a power recovery circuit 210 connected to each group. Capacitors C₁ and C₂ are connected in series between the voltage source for supplying the address voltage V_a and the ground voltage in Fig. 4, and capacitor C₁ can further be eliminated.

Referring to Figs. 5 through 12D, an operation of the address driving circuit according to the first exemplary embodiment of the present invention will be described. The threshold voltage of semiconductor elements (switch or diode) is assumed to be at 0V as the threshold voltage is very much lower than the discharging voltage.

Fig. 5 shows a brief diagram of the address driving circuit of Fig. 4. For ease of description, only two adjacent address selecting circuits 220_2i-1 and 220_2i are illustrated. A capacitive component formed by the address electrode and the scan electrode is illustrated as a panel capacitor, and the ground voltage is applied to the scan electrode part of the panel capacitor.

As shown in Fig. 5, the power recovery circuit 210 is connected to panel capacitors C_p1 and C_p2 through switches A_H1 and A_H2 of the address selecting circuits 220_2i-l and 220_2i, and switches A_L1 and A_L2 of the address selecting circuits 220_2i-1 and 220_2i are connected to the ground voltage. The panel capacitor C_p1 is a capacitive component formed by the address electrode A_2i-1 and the scan electrode, and the panel capacitor C_p2 is a capacitive component formed by the address electrode A_2i and the scan electrode.

An operation of the address driving circuit will be described by using representative patterns of Figs. 6 through 8 displayed on a screen in a single subfield. The representative patterns include the dot on/off pattern and the line on/off pattern having many switching variations of the address selecting circuits 220₁ to 220_m, and the full white pattern having less switching variations of the address selecting circuits 220₁ to 220_m.

Figs. 6 through 8 respectively show concept diagrams of the dot on/off pattern, the line on/off pattern, and the full white pattern.

These patterns are determined by a switching operation of the address selecting circuits 220₁ to 220_m; the timing of switches A_a, A_r, and A_f of the power recovery circuit 210 is the same in any case of realizing the patterns. Switching variation of the address selecting circuit results when turn-on and turn-off operations of the switches A_H and A_L of the address selecting circuit are repeated as the scan electrodes are sequentially selected.

Referring to Fig. 6, the dot on/off pattern is a display pattern generated when the address voltage is alternately applied to the odd and even address electrodes as the scan electrodes are sequentially selected. For example, the address voltage is applied to the odd address electrodes A₁ and A₃ to select odd columns of the first row when the first scan electrode Y₁ is selected, and the address voltage is applied to the even address electrodes A₂ and A₄ to select emission in the even columns of the second row when the second scan electrode Y₂ is selected. To accomplish this addressing, switch A_H of the odd address selecting circuit is turned on and switch A_L of the even address selecting circuit is turned on when the scan electrode Y₁ is selected, whereas switch A_H of the even address selecting circuit is turned on and switch A_L of the odd address selecting circuit is turned on when the scan electrode Y₂ is selected.

Referring to Fig. 7, the line on/off pattern is a pattern in which the address voltage is applied to all the address electrodes A₁ to A₄ when the first scan electrode Y₁ is selected, and ground voltage is applied to the address electrodes A₁ to A₄ when the second scan electrode Y₂ is selected. To accomplish this addressing, switches A_H of all the address selecting circuits are turned on when the scan electrode Y₁ is selected, and switches A_L of all the address selecting circuits are turned on when the scan electrode Y₂ is selected.

Referring to Fig. 8, the full white pattern is a display pattern generated when the address voltage is continuously applied to all the address electrodes as the scan electrodes are sequentially selected. That is, switches A_H of all the address selecting circuits are always turned on.

Switches A_L of the address selecting circuits are periodically turned on in the dot on/off pattern and the line on/off pattern, but are not turned on in the full white pattern. Turn-on states of the switch A_L determine the voltage at capacitor C₂ in the power recovery circuit of Fig. 5.

An operation of the address driving circuit of Fig. 5 will be described in detail by exemplifying the dot on/off pattern and the full white pattern since the dot on/off pattern and the line on/off pattern perform similar functions regarding switches A_L being periodically turned on.

1. Dot on/off pattern (Refer to Figs. 9, and 10A to 10H)

First, the temporal operation of the address driving circuit for displaying a pattern with many switching variations of the address selecting circuits 220₁ to 220_m in the case of the dot on/off pattern will be described with reference to Figs. 9 and 10A to 10H. The operation variation has eight sequential modes, and the modes are varied by a manipulation of the switches. A resonance phenomenon arises, but it is not a continuous oscillation. Instead it is a voltage and current variation caused by combination of an inductor L₁ or L₂ and a panel capacitor C_p1 or C_p2 when the switches A_r and A_f are turned on.

Fig. 9 shows a timing diagram of a power recovery circuit of Fig. 5 for showing the dot on/off pattern, and Figs. 10A to 10H show current paths for respective modes of the address driving circuit of Fig. 5 following the timing of Fig. 9.

In the case that the dot on/off pattern is displayed in the circuit of Fig. 5, switch A_H1 of the address selecting circuit 220_2i-1 connected to the odd address electrode A_2i-1 and switch A_L2 of the address selecting circuit 220_2i connected to the even address electrode A_2i are turned on, and switch A_H2 of the address selecting circuit 220_2i and switch A_L1 of the address selecting circuit 220_2i-1 are turned off when a single scan electrode is selected. Switches A_H1 and A_L2 are turned off and switches A_H2 and A_L1 are turned on when the next scan electrode is selected. These operations are repeated. When the dot on/off pattern is displayed as described above, switches A_H1 and A_H2 and switches A_L1 and A_L2 of the address selecting circuits 220_2i-1 and 220_2i are continuously turned on and off by synchronizing with the scan voltage sequentially applied to the scan electrodes.

It is assumed in Fig. 9 that switches A_H1, A_L2, and A_a are turned on and switches A_H2 and A_L1 are turned off before mode 1 starts so that the voltage V_a is applied to panel capacitor C_p1 and the voltage 0V is applied to panel capacitor C_p2. Thus, it is assumed that the voltage V_a is applied to the odd address electrode A_2i-1 and the voltage 0V is applied to the even address electrode A_2i.

In mode 1, switch A_f is turned on while switches A_H1, A_L2, and A_a are turned on and switches A_H2 and A_L1 are turned off. Then, as shown in Fig. 10A, current is injected into inductor L₂ and capacitor C₂ through the path of the voltage source V_a, switch A_a, inductor L₂, diode D₂, switch A_f, and capacitor C₂, and capacitor C₂ is charged with a voltage.

In mode 2, switch A_a is turned off to form a resonance path through panel capacitor C_p1, the body diode of switch A_H1, inductor L₂, diode D₂, switch A_f, and capacitor C₂ as shown in Fig. 10B. Voltage V_p1 of panel capacitor C_p1 is reduced by the resonance path, and voltage V_p2 of panel capacitor C_p2 is maintained at 0V because switch A_L2 is turned on. The current (energy) discharged from panel capacitor C_p1 is supplied to capacitor C₂, and capacitor C₂ is charged with a voltage.

In mode 3, switches A_H1 and A_L2 are turned off and switches A_H2 and A_L1 are turned on to apply the voltage 0V to panel capacitor C_p1. Switch A_f is turned off and switch A_r is turned on to form a resonance path through capacitor C₂, switch A_r, diode D₁, inductor L₁, switch A_H2, and panel capacitor C_p2 as shown in Fig. 10C. The current is supplied from capacitor C₂ by the resonance path to increase the voltage V_p2 of panel capacitor C_p2 and discharge capacitor C₂. In this instance, voltage V_p2 of panel capacitor C_p2 does not exceed voltage V_a because the body diode of switch A_a is turned on when voltage V_p2 of panel capacitor C_p2 exceeds voltage V_a. The current remaining in inductor L₁ when the voltage of panel capacitor C_p2 reaches V_a is recovered to the voltage source V_a through the body diode of switch A_a.

In mode 4, switch A_a is turned on and switch A_r is turned off to maintain voltage V_p2 of panel capacitor C_p2 at V_a as shown in Fig. 10D.

As described above, the power recovery circuit 210 supplies the voltage V_a to the address electrode A_2i through switch A_H2 of the address selecting circuit 220_2i during modes 1 to 4. The address electrode A_2i-1 is maintained at 0V through switch A_L1 of the address selecting circuit 220_2i-1.

In modes 5 to 8, the operation of the switches of the power recovery circuit is the same as that described above except for the operation of the switches of the address selecting circuit.

In mode 5, switch A_f is turned on while switches A_H2, A_L1, and A_a are turned on and switches A_H1 and A_H2 are turned off. Hence, current is injected into inductor L₂ and capacitor C₂ through the path of the voltage source V_a, switch A_a, inductor L₂, diode D₂, switch A_f and capacitor C₂ as shown in Fig. 10E, and capacitor C₂ is charged with a voltage.

In mode 6, switch A_a is turned off to form a resonance path through panel capacitor C_p2, the body diode of switch A_H2, inductor L₂, diode D₂, switch A_f, and capacitor C₂ as shown in Fig. 10F. Voltage V_p2 of panel capacitor C_p2 is reduced by the resonance path, and voltage V_p1 of panel capacitor C_p1 is maintained at 0V because switch A_L1 is turned on. The current (energy) discharged from panel capacitor C_p2 is supplied to capacitor C₂, and capacitor C₂ is charged with a voltage.

In mode 7, switches A_H2 and A_L1 are turned off and switches A_H1 and A_L2 are turned off to apply the voltage 0V to panel capacitor C_p2. Switch A_f is turned off and switch A_r is turned on to form a resonance path through capacitor C₂, switch A_r, diode D₁, inductor L₁, switch A_H2, and panel capacitor C_p1 as shown in Fig. 10G. Current is supplied from capacitor C₂ by the resonance path to increase voltage V_p1 of panel capacitor C_p1 and discharge the capacitor C₂. Voltage V_p1 of panel capacitor C_p1 does not exceed V_a because the body diode of switch A_a is turned on when voltage V_p1 of panel capacitor C_p1 exceeds V_a. The current remaining in inductor L₁ after the voltage of panel capacitor C_p1 reaches V_a is freewheeled through the body diode of switch A_a.

In mode 8, switch A_r is turned off and switch A_a is turned on to maintain voltage V_p1 of panel capacitor C_p1 at V_a as shown in Fig. 10H.

During modes 5 through 8 as described, the power recovery circuit 210 supplies the voltage V_a to the address electrode A_2i-1 through switch A_H1 of the address selecting circuit 220_2i-1. The address electrode A_2i is maintained at 0V through switch A_L2 of the address selecting circuit 220_2i. The dot on/off pattern is realized by repeating the operation of modes 1 to 8.

When capacitor C₂ is charged with a voltage V_a/2, and the capacitance of capacitor C₂ is large enough to function as a voltage source for supplying the voltage V_a/2 to capacitor C₂, panel capacitor C_p1 or C_p2 charged with the voltage V_a in mode 2 or 6 can be discharged to 0V by the LC resonance principle, and panel capacitor C_p1 or C_p2 discharged 0V in mode 3 or 7 can be charged to voltage V_a.

First, current (energy) is supplied to capacitor C₂ through inductor L₂ from the voltage source in mode 1, and panel capacitor C_p1 is discharged to supply the current (energy) to capacitor C₂ in mode 2. In this way, capacitor C₂ is charged with energy to raise the voltage of capacitor C₂ by an amount <img file="EP1536401A2_D0001.tif" />V1 in modes 1 and 2. Current is supplied from capacitor C₂ through inductor L₁ to increase the voltage of panel capacitor C_p2, and the residual current is recovered to the voltage source in mode 3. In this way, energy is discharged from capacitor C₂ to reduce the voltage of capacitor C₂ by the amount <img file="EP1536401A2_D0002.tif" />V2. Assuming that capacitor C₂ is charged with the voltage V_a/2 in the earlier stage, the charge energy of capacitor C₂ is greater than discharge energy of capacitor C₂ because energy is further supplied through the voltage source in mode 1 at the time of charging capacitor C₂. Hence, <img file="EP1536401A2_D0003.tif" />V1 is greater than <img file="EP1536401A2_D0004.tif" />V2. The charge and discharge energy to and from the capacitor C₂ in modes 5 to 8 corresponds to the charge and discharge energy in modes 1 to 4. Because the panel capacitor C_p1 or C_p2 is discharged so that its residual voltage reaches 0V, and because the panel capacitor is charged again in mode 3 or 7, the energy discharged from the capacitor C₂ for charging the panel capacitor C_p1 or C_p2 is substantially constant when modes 1 to 8 are repeated.

When the charge energy of capacitor C₂ is greater than discharge energy thereof, and the voltage at capacitor C₂ increases, the energy charged into capacitor C₂ is reduced in modes 1 and 2 or modes 5 and 6. Thus, when the operations of modes 1 to 8 are repeatedly performed, the charge energy of capacitor C₂ is reduced, and the charge energy of capacitor C₂ and the discharge energy thereof finally become the same and thus reach an equilibrium state. The voltage charged in capacitor C₂ is greater than V_a/2 and less than V_a.

When the voltage charged in panel capacitor C₂ is greater than V_a/2, a voltage equal to twice the voltage of the capacitor C₂, which therefore is greater than V_a, can be charged in panel capacitors C_p1 and C_p2 by the resonance principle in modes 3 and 7. Therefore, the voltages of panel capacitors C_p1 and C_p2 can rise to the voltage V_a by the resonance principle when a parasitic component is provided in the address driving circuit, and switch A_a can perform a zero-voltage switching operation.

2. Full white pattern (Refer to Figs. 11, and 12A to 12D)

A temporal operation of the address driving circuit for displaying a pattern with less switching variations of the address selecting circuits 220₁ to 220_m than in the line on/off pattern case will be described with reference to Figs. 11 and 12A to 12D. The operation has four sequential modes, and the modes are varied by a manipulation of the switches. A resonance phenomenon arises but is not a continuous oscillation. Instead, it is a voltage and current variation caused by combination of an inductor L₁ or L₂ and a panel capacitor C_p1 or C_p2 when switches A_r and A_f are turned on.

Fig. 11 shows a timing diagram of a power recovery circuit of Fig. 5 for showing the full white pattern, and Figs. 12A to 12D show current paths for respective modes of the address driving circuit of Fig. 5 following the timing of Fig. 11.

In the case of displaying the full white pattern in the circuit of Fig. 5, switches A_H1 and A_H2 of the address selecting circuits 220_2i-1 and 220_2i are always turned on as the scan electrodes are sequentially selected.

It is assumed in Fig. 11 that switches A_H1, A_H2, and A_a are turned on before mode 1 begins so that the voltage V_a is applied to panel capacitors C_p1 and C_p2.

In mode 1, switch Ar is turned on while switches AH1, AH2, and Aa are turned on. As shown in Fig. 12A, current is injected into inductor L2 and capacitor C2 to charge capacitor C2 with a voltage in the same manner as mode 1 Fig. 9.

In mode 2, switch A_a is turned off to form a resonance path through panel capacitors C_p1 and C_p2, the body diodes of switches A_H1 and A_H2, inductor L₂, diode D₂, switch A_f, and capacitor C₂ as shown in Fig. 12B. Voltages V_p1 and V_p2 of panel capacitors C_p1 and C_p2 are reduced by the resonance path, and capacitor C₂ is charged with a voltage in the same manner as in mode 2 of Fig. 9.

In mode 3, switch A_f is turned off and switch A_r is turned on to form a resonance path through capacitor C₂, switch A_r, diode D₁, inductor L₁, switch A_H2, and panel capacitors C_p1 and C_p2 as shown in Fig. 12C. Voltages V_p1 and V_p2 of panel capacitors C_p1, and C_p2 are increased by the resonance path, and capacitor C₂ is discharged. Voltages V_p1 and V_p2 of panel capacitors C_p1 and C_p2 do not exceed the voltage V_a because the body diode of switch A_a is turned on when voltages V_p1 and V_p2 exceed V_a.

In mode 4, switch A_r is turned off and switch A_a is turned on to maintain voltages V_p1 and V_p2 of panel capacitors C_p1 and C_p2 at V_a as shown in Fig. 12D.

During the modes 1 through 4, the power recovery circuit 210 supplies the voltage V_a to the address electrodes A_2i-1 and A_2i through switches A_H1 and A_H2 of the address selecting circuits 220_2i-1 and 220_2i as described. In the case of displaying the full white pattern of Fig. 9, modes 1 to 4 are repeated while switches A_H1 and A_H2 are turned on.

Because switches A_L1 and A_L2 of the address electrodes A_2i-1 and A_2i are not turned on in the full white pattern of Fig. 8, the residual voltages in panel capacitors C_p1 and C_p2 are not discharged. However, panel capacitors C_p1 and C_p2 are charged in mode 3 while the residual voltage is not discharged after panel capacitors C_p1 and C_p2 are discharged in mode 2. Therefore, assuming that 100% of the energy is recovered and used, the energy of charging capacitor C₂ in mode 2 and the energy discharged from capacitor C₂ in mode 3 are substantially the same. The voltage <img file="EP1536401A2_D0005.tif" />V1 charged in capacitor C₂ is always greater than the voltage <img file="EP1536401A2_D0006.tif" />V2 discharged from capacitor C₂ in the case of displaying the full white pattern of Fig. 8 because the operation of supplying current to capacitor C₂ to charge capacitor C₂ in mode 1 is further performed.

The voltage of capacitor C₂ is increased when the processes of modes 1 through 4 are repeated in the case where the voltage <img file="EP1536401A2_D0007.tif" />V1 charged in capacitor C₂ is always greater than the voltage <img file="EP1536401A2_D0008.tif" />V2 discharged from capacitor C₂. When the voltage of capacitor C₂ is increased, the current discharged from panel capacitors C_p1 and C_p2 to capacitor C₂ is reduced in mode 2 to reduce the discharged amount from panel capacitors C_p1 and C_p2. That is, the reducing amounts of voltages V_p1 and V_p2 of the panel capacitors C_p1 and C_p2 decrease as modes 1 to 4 are repeated as shown in Fig. 11.

When the voltage of capacitor C₂ is continuously increased to substantially correspond to the voltage V_a, panel capacitors C_p1 and C_p2 are not discharged in mode 2 because voltages V_p1 and V_p2 of panel capacitors C_p1 and C_p2 correspond to the voltage at capacitor C₂. Panel capacitors C_p1 and C_p2 are not charged in mode 3 because voltages V_p1 and V_p2 of panel capacitors C_p1 and C_p2 are not reduced in mode 2. When the voltage at capacitor C₂ reaches V_a, substantial current movement almost disappears in modes 2 and 3, and thus the power recovery circuit 210 essentially does not operate in the case of displaying the full white pattern.

As described above, the operation of the power recovery circuit according to the first exemplary embodiment of the present invention is established when the voltage level of capacitor C₂ is varied by the switching operation of the address selecting circuit. The voltage of capacitor C₂ is determined by the energy charged in and discharged from capacitor C₂. Because the charge energy of capacitor C₂ includes the energy supplied by the voltage source through an inductor and the discharge energy of the panel capacitor, and because the discharge energy of capacitor C₂ includes the charge energy of the panel capacitor, the charge energy of capacitor C₂ is greater than the discharge energy thereof when capacitor C₂ is charged with a voltage equal to V_a/2, which is half of the address voltage.

In the case of the dot on/off pattern, because the panel capacitor charged up to the address voltage is completely discharged down to the ground voltage and charged again up to the address voltage by the turn-on of switch A_L of the address selecting circuit, the charge energy of the panel capacitor, which is the discharge energy of capacitor C₂, is almost constant. In addition, the voltage at capacitor C₂ is increased, and the charge energy of capacitor C₂ is accordingly reduced because the charge energy of capacitor C₂ is greater than the discharge energy thereof while the capacitor C₂ is charged with a voltage V_a/2. Therefore, when the above operation is repeated, the charge energy of capacitor C₂ is reduced to correspond substantially to the discharge energy of capacitor C₂, thereby performing the power recovery operation.

Because of many switching variations of the address selecting circuits 220₁ to 220_m, capacitor C₂ is charged with a voltage between V_a/2 and V_a to thus perform the power recovery operation when many panel capacitors that are charged up to the address voltage after being completely discharged down to the ground voltage are provided from among a plurality of panel capacitors connected to the address selecting circuits 220₁ to 220_m.

In the case of the full white pattern, switch A_L, which is connected to the panel capacitor charged up to the address voltage, is not turned on. When the charge energy of capacitor C₂ is greater than its discharge energy so that the voltage at capacitor C₂ exceeds V_a/2, the voltage of the panel capacitor is not discharged down to the ground voltage by the resonance of the inductor and the panel capacitor. A residual voltage is generated because the switch A_L connected to the panel capacitor charged up to the address voltage is not turned on. The charge energy and the discharge energy of the panel capacitor are reduced in the same manner by the residual voltage, and accordingly, the voltage at capacitor C₂ is continuously increased. When the voltage at capacitor C₂ is increased, the residual voltage of the panel capacitor is also increased, almost no energy is charged in the panel capacitor and discharged from the same, and almost no energy is exhausted in the power recovery circuit.

In addition to the full white pattern, the above-noted power recovery operation is rarely performed for a pattern wherein only one color is displayed on the whole screen or a pattern wherein the address voltage is continuously applied to a predetermined number of address electrodes.

In the above-described first exemplary embodiment of the present invention, the power recovery operation is performed in a pattern that, due to many switching variations of the address selecting circuit, requires the power recovery operation and no power recovery operation is automatically performed in a pattern that, due to few switching variations of the address selecting circuit, requires no power recovery operation.

As an example, it may be assumed for purposes of this description that in the driving circuit shown in Fig. 4, the whole panel capacitances in the dot on/off pattern, the line on/off pattern, and the full white pattern are about 169nF, 217nF, and 288nF, respectively. With that panel capacitance, if the capacitor C1 has a capacitance of 10µF, the capacitor C2 has a capacitance of 10 µF, the inductor L1 has an inductance of 0.1 µH, the inductor L2 has an inductance of 0.1µH, the address voltage V_a is 60-65V. As those of skill in the art will realize, the above is only one example of the characteristics of the components and the lengths of the periods in embodiments of the invention; components with other characteristics and periods of different lengths may be used.

In the first exemplary embodiment, inductor L₁ used for discharging capacitor C₂ is different from inductor L₂ used for charging the capacitor C₂, . However, the same inductor L can be used as shown in Fig. 13. A first terminal of inductor L is connected to a second terminal of switch A_H of the address selecting circuit 220₁ to 220_m, and a second terminal of inductor L is connected in parallel to diodes D₁ and D₂. Accordingly, the current charged in capacitor C₂ and the current therefrom flow through inductor L.

Fig. 14 shows the power consumption in the address driving circuit according to the first exemplary embodiment of the present invention. As shown in Fig. 14, in a pattern having many switching variations, such as the dot on/off pattern and the line on/off pattern, the power consumption G3 of the address driving circuit according to the first exemplary embodiment is lower than that G1 of a driving circuit that does not have the power recovery circuit, and is the same as that G2 of the conventional power recovery circuit (disclosed in U.S. Patent Nos. 4,866,349 and 5,081,400). In addition, in a pattern having less switching variations such as the full white pattern, the full red pattern, the full green pattern and the full blue pattern, the power consumption G3 of the address driving circuit according to the first exemplary embodiment is lower than that G2 of the conventional power recovery circuit. However, in a pattern having less switching variations, the power consumption G3 of the address driving circuit according to the first exemplary embodiment is higher than that G1 of a driving circuit that does not have the power recovery circuit because it performs a power recovery operation in this pattern.

An exemplary embodiment having lower power consumption than that of the first exemplary embodiment will now be described with reference to Figs. 15 and 16.

Fig. 15 shows a controller of a plasma display device according to a third exemplary embodiment of the present invention, and Fig. 16 shows the power consumption of the driving circuit according to the third exemplary embodiment of the present invention.

The plasma display device according to the third exemplary embodiment of the present invention has the controller 400 that is different from that of the plasma display device according to the first embodiment. Referring to Fig. 15, controller 400 of the plasma display device according to the third exemplary embodiment includes a data processor 410, an address power consumption estimator 420, an address power recovery decider 430, and an address power recovery controller 440.

The data processor 410 converts the inputted video signal to the on/off data in the respective subfields. Assuming that one frame (i.e., one TV field) is divided into eight subfields that have weights of 1, 2, 4, 8, 16, 32, 64 and 128 as the lengths of the sustain periods, respectively, the data processor 410 converts (for example) a video signal of 100 gray levels to 8 bits data of "00100110". The bits "0" and "1" in the "00100110" respectively correspond to on and off states of the eight subfields 1SF to 8SF in the discharge cell (dot). A "0" indicates that the discharge cell will be not discharged (off) in the corresponding subfield, and a "1" indicates that the discharge cell (dot) will be discharged (on) in the corresponding subfield.

The address power consumption estimator 420 estimates the address power consumption in respective subfields from the video signal converted to on/off data. The address power consumption is determined by the switching variations of the address select circuits 220₁ to 220_m. Switching variation occurs when one of the two adjacent discharge cells in the column direction is on and the other is off. Therefore, as described in Equation 1, the address power consumption AP can be estimated from the total summation of the difference between the on/off data of two adjacent discharge cells in the column direction.<maths id="math0001" num=""><img file="EP1536401A2_D0009.tif" /></maths>

where R_ij, G_ij and B_ij are the on/off data of the R (red), G (green) and B (blue) discharge cell in i-th row and j-th column, respectively.

Generally, because the video signal is serially inputted in the order of rows, the address power consumption estimator 420 includes a line memory (not shown) for storing the video signal of one row in order to calculate the difference between the on/off data of two adjacent discharge cells in the column direction. When the on/off data of the respective subfields for the video signal of one row are inputted, the address power consumption estimator 420 stores these on/off data to the line memory, reads the on/off data for the previous row from the line memory, and calculates the difference between the on/off data of two adjacent discharge cells in the respective subfields. The address power consumption estimator 420 performs this calculation with respect to all discharge cells and estimates the address power consumption AP from the summation of the calculation results. In addition, the address power consumption estimator 420 may perform an XOR (exclusive OR) operation between the on/off data of two adjacent discharge cells in the respective subfields instead of calculating the difference between the on/off data.

The address power recovery decider 430 uses the address power consumption AP calculated through Equation 1 to decide whether the power recovery operation is performed and outputs a control signal that indicates whether the power recovery operation should be performed. The address power recovery decider 430 outputs the control signal that indicates that the power recovery operation should be performed when the address power consumption AP is higher than the critical value, and outputs the control signal that indicates the power recovery operation should be not performed when the address power consumption AP is lower than the critical value.

The address power recovery controller 440 allows the power recovery circuit 210 described in the first or the second exemplary embodiment to operate when the control signal indicates that the power recovery operation should be performed. The address power recovery controller 440 prevents the power recovery circuit 210 described in the first or the second exemplary embodiment from operating when the control signal indicates that the power recovery operation should be not performed. To stop the power recovery operation, the address power recovery controller 440 always turns off switches A_r and A_f and turns on switch A_a so that the voltage V_a is applied to the first terminals of switches A_H of the address selecting circuits 220₁ to 220_m. Then, the addressing voltage V_a is applied to the address electrodes A₁ to A_m by only turning on switch A_H. Therefore, the power consumption by the resonance generated when switch A_r or A_f is turned on is removed.

In the third exemplary embodiment of the present invention, because switches A_r and A_f of the power recovery circuit 210 are always turned on in a display pattern having less switching variations, switching loss from the operation of switches A_r and A_f and the power consumption by the resonance generated when switch A_r or A_f is turned on can be removed. Therefore, as shown in Fig. 16, the power consumption of the third exemplary embodiment is lower than that of the first exemplary embodiment in a pattern having less switching variations, such as the full white pattern, the full red pattern, the full green pattern and the full blue pattern.

In the third exemplary embodiment of the present invention, the address power consumption is determined by whether two adjacent discharge cells in the column direction are on or not. However, the address power consumption is also affected by the adjacent discharge cells in the row direction. A fourth exemplary embodiment for controlling the operation of the power recovery circuit 210 while accounting for the adjacent discharge cells in the row direction will be described.

As shown in Figs. 1 to 3, the capacitance component exists between the two adjacent address electrodes A_i and A_i+1 because the address electrodes A₁ to A_m are extended in a column direction. Therefore, power consumption in the case when the voltages applied to the two adjacent address electrodes A_i and A_i+1 are the same is lower than in of the case when the voltages applied to the two adjacent address electrodes A_i and A_i+1 are different. Hence, power consumption in the dot on/off pattern shown in Fig. 6 is higher than in the line on/off pattern shown in Fig. 7.

In detail, the capacitance between the two adjacent address electrodes A_{<sub2>i</sub2>} and A_i+1 in the row direction increases when the on/off states of the adjacent discharge cells in the row direction are different. Then, the reactive power for injecting charges in the capacitance increases since the total capacitances loaded on the power recovery circuit of the address driving circuit increase when the capacitance formed in the row direction increases. On the contrary, the capacitance between the two adjacent address electrodes A_i and A_i+1 decreases when the on/off states of the adjacent discharge cells in the row direction are the same. In this case, the total capacitances loaded on the power recovery circuit decrease so that the reactive power decreases.

In the third exemplary embodiment, the operation of the power recovery circuit is determined by the on/off states of the adjacent discharge cells in the row direction because the reactive power consumption is different according to the on/off states of the adjacent discharge cells in the row direction. As shown in Equation 2, the address power consumption AP is determined by the difference of the on/off data between adjacent discharge cells in the row direction as well as that between adjacent discharge cells in the column direction. In Equation 2, it is assumed that the discharge cells are repeated in order of R, G and B in the row direction.<maths id="math0002" num=""><img file="EP1536401A2_D0010.tif" /></maths>

As described above, in the third and fourth exemplary embodiments of the present invention, the power recovery operation does not occur for a pattern having less switching variations so that power consumption is reduced.

In addition, according to the present invention, the power recovery operation is performed for a pattern with many switching variations of the address selecting circuit, and the power recovery operation is automatically prevented in a pattern without switching variations of the address selecting circuit, thereby reducing the power consumption. Zero-voltage switching is performed when the address voltage is applied because an external capacitor is charged with a value greater than half of a predetermined voltage.

While this invention has been described in connection with what is presently considered to be the most practical and exemplary embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.