EP1525725B1

Switching architecture with packet encapsulation

Abstract

The invention includes, among other things, a system for passing TDM traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing FSDU packets between the plurality of data ports. A TDM encapsulation circuit process a TDM data flow that is incoming to the switch. A circuit demultiplexer processes the incoming data flow to buffer data associated with different TDM circuits into different buffer locations. A timer monitors the amount of time available to fill the FSDU, and when the time period reaches the frame boundary, an FSDU generator generates an FSDU that is filled with data associated with the TDM circuits. Header information is added for allowing the packet switch to route the generated FSDU to a port associated with the respective TDM circuit.

EP1525725B1, drawing sheet 1
Sheet 1 of 5

Term

Term ended

Expired 5 May 2023, 3.4 years ago.

  1. Priority
  2. Filed
  3. Granted
  4. Expired
  5. Today

17 claims: 4 independent, 13 dependent

  1. 1
    A system for passing time-division multiplexing, TDM, traffic through a packet switch, comprising:a packet switch (500) having a plurality of data ports (510) and being capable of routing fixed-sized data unit, FSDU, packets between the plurality of data ports;a TDM encapsulation circuit (512) coupled to a TDM data flow and having a circuit demultiplexer for processing an incoming TDM data flow to buffer data associated with different TDM circuits into different buffer locations, a timer for monitoring a frame boundary, and an FSDU generator (514) for generating an FSDU, filling the generated FSDU with data associated with a respective one of the TDM circuits;and for generating header information (620) representative of information for allowing the packet switch to route the generated FSDU to a port associated with the respective one of the TDM circuits;characterised in that said system further comprises: means for accessing and monitoring a connection table having information representative of the ports associated with a TDM circuit to determine the number of active TDM circuits within the TDM data flow and to identify a change in the number of active TDM circuits;and means for altering the contents of the generated FSDU as a function of a detected change in the number of active TDM circuits in the TDM data flow.
  2. 2
    A system according claim 1, wherein said means for altering said content of said generated FSDU comprises means for dropping from said generated FSDU, data associated with a TDM circuit dropped from said TDM data flow.
  3. 12
    A process for passing TDM traffic through a packet switch, comprising the steps of:providing a packet switch having a plurality of data ports and being capable of routing FSDU packets between the plurality of data ports;identifying (405) a TDM data flow;encapsulating (415) the TDM data flow by buffering data associated with different TDM circuits into different buffer locations;generating an FSDU that can pass through the packet switch;filling (420) the generated FSDU with data associated with a respective one of the TDM circuits;and generating (420) header information representative of information for routing the generated FSDU to a port associated with the respective one of the TDM circuits characterised by further comprising the steps of: accessing a connection table having information representative of the ports associated with a TDM circuit;monitoring the connection table to determine the number of active TDM circuits within the TDM data flow to identify a change in the number of active TDM circuits;and altering the contents of the generated FSDU as a function of a detected change in the number of active TDM circuits in the TDM data flow.
  4. 13
    A process according claim 12 wherein said step of altering said content of said generated FSDU comprises the step of dropping from said generated FSDU, data associated with a TDM circuit dropped from said TDM data flow.