Data encryption in an electronic apparatus with several symmetrical processors

The present invention relates generally to encryption or encryption of data to be used in one or more processors, where data must be stored in a memory external to the processors.

It finds applications in particular in apparatus electronic architecture with several symmetric processors and external shared memory (SMP architecture, standing for "Symmetric Multi-Processor"). More specifically, the present invention relates to applications where it is desired to prevent an unauthorized user accesses operably data, and in which said data is to, in least in part, can be accessed by more than one circuit.

This refers to the term "data" to refer indifferently any binary code whether executable programs, or binary data processed by these programs. In addition, it is reference to the term "circuit" to describe any unit indifferently Function of an electronic apparatus connected to other functional units via one or more communication bus, be it a processor, device controller (eg, a disk controller), a map network, etc.

Figure 1 schematically illustrates the SMP architecture of a device electronic, to which the present invention applies. multiple processors 2 (CPU) are coupled to an external memory 4 (EXT MEM), through one or more bus 3. We can define a zone 1, said safe area, inside of which there is one or more processors 2, and within which it is considered that the processed data are not likely to be pirated. In practice, the secure area 1 usually comprises one or several integrated circuit chips corresponding to respective processors, the memory 4 being another chip that does not belong to the secure area. In Additionally, other circuit 5 as a disk controller (CTRL DSK) or NIC (NET CARD), may be connected to processor 2 by via bus 3.

Encryption which applies the present invention more particularly that of data transmitted on the bus or 3, between 4 memory and the processor 2 in zone 1. In the jargon of Man the trade, we talk about memory encryption or encryption of bus. This encryption is to encode the data stored in the memory 4 by means of a bus encryption key known by the processors concerned.

Examples of solution to encrypt a memory external to a microprocessor are described in U.S. Patent 5,825,878, 5,982,887, and 6,041,449.

These solutions are not suited to the case of systems SMP architecture, in so far as they must use the same key bus encryption to encrypt and to decrypt the data while each processor uses a bus encryption key of its own. In Indeed, measures must be taken to allow another processor of the secure area to decipher, to use, encrypted data and stored in the shared external memory with another processor of said secure area. These measures must be compatible with the secret key character of the bus encryption keys.

Another constraint is associated with the encryption method used. In the prior art, are generally used block ciphers with type algorithms DES ( "Data Encryption System") or AES ( "Advanced Encryption System "), as a mode electronic coding book says fashion ECB ( "Electronic Code Book") or mode by chaining said blocks CBC mode ( "Cipher-Block Chaining"). The size of a block depends on the algorithm used encryption. In the ECB mode, two identical blocks are encrypted in the same way. Attacks are possible by the technique called "Dictionary", insofar as the redundancy of encrypted messages identically may allow the identification of clear messages. By opposition in the CBC mode, each block is encrypted function blocks precedents. This mode is more robust. Nevertheless, it requires access sequential memory, which makes it incompatible with the encryption data that is desired to randomly access the external memory.

The present invention is to provide, in the context of a device electronic SMP architecture, a new encryption technique, a processor, data to be stored in a memory external to the processor, when data needs to be processed by more than one processor.

To this end, a first aspect of the invention provides a method of encryption in a circuit of an electronic apparatus, of data to be stored in a memory external to said circuit, comprising the steps of:<ul><li>select a secret key from a secret key list respectively stored in a set of registers in circuit each combination with a key identifier, at least one of said key being a key shared with at least another unit circuit electronics;</li><li>cut data as a stream of size data words determined; and, continuously for each data word,</li><li>generating a pseudo random number determined by size a pseudorandom generator implementing an algorithm of generation based on said secret key and an initialization vector changing value to each data word;</li><li>combining the data word and the pseudo random number corresponding to generate an encrypted data word; then,</li><li>storing in said external memory each encrypted data word in association with the initialization vector and the key identifier associated with the secret key used to encrypt it.</li></ul>

A second aspect of the invention provides a method of decryption, in a circuit of an electronic apparatus, of data stored in the form of encrypted data words in a memory external audit circuit, comprising the steps of:<ul><li>said external memory read an encrypted data word and an initialization vector and a secret key identifier respectively associated with said data word; </li><li>select a secret key from a secret key list respectively stored in a set of system registers and including a at least is a key shared with at least another unit circuit electronics, and from further said identifier; and, continuously for each encrypted data word,</li><li>generating a pseudo random number determined by size a pseudorandom generator implementing an algorithm of generation based on said secret key and of said initialization vector; and</li><li>combining the data word and the pseudo random number corresponding to generate a decrypted data word.</li></ul>

A third aspect of the invention relates to a device for implementing an encryption method according to the first aspect, comprising:<ul><li>a set of registers storing respective secret keys, of which at least one is a shared key with another device circuit electronics, each in association with a key identifier;</li><li>a secret key selection unit adapted to select a secret key from the list of keys stored in said set of records;</li><li>a segmentation unit suitable for cutting data to form a stream of fixed sized data words;</li><li>an initialization vector generator adapted to generate a flow initialization vectors changing value to each data word;</li><li>a generator of pseudorandom numbers implementing a generating algorithm suitable for generating, for each data word, based on said secret key and of said vectors determined initialization, a pseudo random number of fixed size;</li><li>a combination unit suitable for continuously combining the word data and the corresponding pseudo-random number to generate a word encrypted data; and,</li><li>means for storing in said external memory each word Data encrypted in association with said determined and initialization vector the key identifier associated with the secret key used to encrypt it.</li></ul>

In addition, in a fourth aspect, the invention provides a device for the implementation of a decryption method according to the second aspect. This device comprises:<ul><li>a set of registers storing respective secret keys which at least one is a shared key, each in association with a key identifier;</li><li>reading means for reading from said external memory one word data and an initialization vector and with an identifier of a key secret associated respectively to said data word;</li><li>selection means for selecting, for each word data, a secret key from a list of keys stored in said registers and from further said key identifier;</li><li>a generator of pseudorandom numbers implementing a generating algorithm suitable for generating, for each data word, based on said secret key and of said initialization vector, a number pseudorandom fixed size; and,</li><li>a combination unit adapted to combine the data word and the corresponding pseudo-random number, so as to decrypt said data word of data.</li></ul>

A fifth aspect of the invention relates to a circuit comprising a encryption unit / decryption forming encryption device according to the third aspect and decryption device of the fourth aspect. The set of registers, the pseudo-random numbers and unity combination are then common to both devices.

According to a sixth and final aspect, the invention also provides a Electronic apparatus comprising at least two circuits according to the fifth aspect, wherein at least one of the secret keys is shared between said circuits so as to form a secure subsystem.

The keys are called shared in that other circuits the electronic device know, for example the circuits belonging to the secure area, that is to say to the secure subsystem. The invention thus provides a solution that allows to individualize encryption depending on the processor carries, while ensuring that all processors have the authorization to use data stored in external memory can decipher.

Encryption of the invention is the type of a stream cipher ( "Stream Cipher"), which is simpler and therefore faster than a cipher blocks. A stream cipher is also insensitive to attacks dictionary, because the same data word is encrypted with a different word each encryption.

In addition, the encryption according to the invention is compatible with an access random to the external memory.

Other features and advantages of the invention will still on reading the description which follows. This is purely illustrative and should be read with reference to the accompanying drawings in which:<ul><li>FIG 1 is a diagram of an electronic apparatus which can apply the various aspects of the invention;</li><li>Figure 2 is a block diagram of exemplary circuitry coupled to an external memory, according to an embodiment of a circuit according the invention.</li></ul>

In the drawings, the same elements are designated by the same references in the different figures. For clarity, only steps of the method and the elements that are necessary for the understanding of the invention have been shown and are described in the following. In particular, all the elements of a circuit has not been detailed, the invention operating components known for its implementation.

A feature of the present invention to encrypt data (programs, any binary data) to be stored in a shared external memory by several circuits of a device electronic. Data is encrypted using a secret key, clean the circuit performing the encryption, which may be different from the secret key used by other circuits for comparable encryption.

To allow the use of encrypted data over a circuit, at least some of secret keys may be used by a circuit are shared with one or more other circuits, that is to say, it is known of these circuits while secret vis-à-vis the rest of the system. A shared key defines a circuit subsystem can use common data stored in external memory. Typically, this subsystem may correspond to a secure area as shown in introduction in conjunction with the diagram of Figure 1.

In addition, data is stored in the external memory association with an identifier of the secret key used to encrypt them. This identifier allows authorized circuits to determine the secret key used to decrypt data. This identifier can match to an index into a set of internal registers in which the key Secret supported by a circuit are stored respectively. It is therefore not the secret key itself is stored with the data encrypted it, but the identifier of this secret key. The disclosure of the identifier by storage in external memory offers no weakness encryption, since only authorized circuits can know the key Secret to use from this identifier.

Another feature of the present invention is to provide a encryption and decryption continuously during transfers between a circuit and external memory. The stream cipher is obtained from a cutting fixed-size words of data which are then stored as encrypted in the external memory. It also provides encryption uses the combination of a data word with a pseudo random number, which is generated from the secret key and an initialization vector.

Advantageously, the initialization vector changing value for every word, preferably randomly, in order to strengthen security encryption. The initialization vector used to encrypt a password data is conveniently stored in external memory in association with the data codeword, as well as the identifier of the secret key as indicated above. Is thus avoided the problems related to stream cipher which are typically incompatible with access Direct random to a memory.

The diagram of Figure 2 shows the essential means of example embodiment of a circuit suitable for carrying out the method of encryption (shown by the solid arrows) and for the implementation decryption process (illustrated by the arrows in dotted lines).

The circuit here is a processor 2 (CPU) comprising a core processor 44 (CORE), cache memories 33 and 34 (CACHE), a unit 31 (KSEL) encryption key selection (K), and a unit 38 (BEU) to encryption / decryption.

The unit 38 includes a unit 22 (SEGM) segmentation data, a set 32 ​​(KREG) secret keys registers, a first pseudorandom generator 24 (IVGEN), a cache memory 25 (IVCACHE) an encryption key register 12 and an initialization vector register 13, a second pseudo random generator 10 (PRNG), and finally a unit 11 combination.

The segmentation unit 22 is operable to segment data encrypting (DATA) received from the processor core 44, data words (W) of predetermined size. A data word can thus comprise a single bit. Preferably, however, the size of a word is equal to one byte, that is to say qu'un mot comprend huit bits.

Each register of the assembly 32 is adapted to store so nonvolatile a secret key (K) to which is associated a key identifier Secret (KID). Or all of the secret keys can be provided to processor via a secure channel, for example during manufacture of the system. Some at least secret keys may, conversely, be internally generated by an ad hoc algorithm whose description is beyond the scope of this paper. In a preferred embodiment for its simplicity, the identifier is an index, such a record number, allowing access to the secret key corresponding one of the secret key list supported by the processor and stored in the assembly 32.

The random number generator 24 is adapted to generate vectors Boot to the rhythm of an initialization vector by data word encrypt, according to a pseudo random any algorithm.

The cache 25 is adapted to store pairs formed each of an initialization vector and a key identifier associated with a data word.

The register 12 is adapted to store an encryption key, namely one of the secret keys stored in the register file 32. This register shown here for the sake of clarity, but may be omitted if it is anticipated means for managing the set of registers 32 adapted.

The register 13 initialization vector has the function of storing the Initialization Vector continuously generated by the pseudo random generator 24. Preferably, the size of the initialization vectors is equal to the word size data to be encrypted.

The role of the pseudo-random generator 10 is to generate a continuous flow pseudo-random number (PN), by reason of such a number by word data to be encrypted. Each pseudo random number is generated from the encryption key stored in the register 12 and the initialization vector stored in the register 13, the latter changing value to each word data.

In one example, the combination unit is an Exclusive-OR gate (XOR). The pseudo-random generator 10 and XOR gate form a cryptosystem, in itself, is well known to the skilled person. The words of encrypted data it outputs the same size as the words of data (before encryption) being input. Such a cryptosystem present the advantage of a simple encryption algorithm, so fast, and whose vis-à-vis security attacks strength is determined by the details internal pseudo random generator 10. More flow generated number PN by the latter is random, the better the algorithm of the safety encryption. Another advantage of an encryption algorithm by XOR gate is that the deciphering is performed in the same way as encryption, which simplifies the hardware design of the cryptosystem.

The circuit in encryption mode, will now be explained by considering the solid arrows shown in Figure 2.

Encryption mode is typically activated by the processor core 44 when the data DATA stored in, or passing through the memory Cache 34 must be written in the external memory 23, and must for this purpose transit via the communication bus 3.

The core 44 controls the selection unit 31 so as to select one of the secret keys stored in the set of register 32. In one example, the unit 31 selects a key identifier secret kidi associated with a secret key determined. This identifier is provided by kidi the unit 31 to the encryption unit 38.

In the encryption unit 38, the key Ki associated with the identifier kidi is read from the set register 32 with said kidi identifier, used for example as an index into the path of the set of registers 32. The Ki key is then stored in the register 12.

Furthermore, the core 44 controls the cache memory 34 so that the data DATA are supplied to the encryption unit 38, and more particularly the input of the segmenting unit 22. The latter delivers a stream of binary words Wi, each corresponding to a segment of the stream DATA data. Meanwhile, the pseudo-random generator 24 generates a flow IVi initialization vectors, the pace of issuing words Wi data by the unit 22, the initialization vectors changing value each Wi words. In other words, each data word Wi is associated an initialization vector IVi whose value is different from the vector Initialization associated with the previous word in the data word stream. The initialization vectors IVi, which are continuously generated, are each stored in the register 13.

For each word of Wi data, the following operations are then carried out continuously.

On the one hand, the pseudo random number generator 10 generates a pseudorandom PNi depending on the secret key Ki stored in the register 12 and initialization vector IVi stored in the register 13. Each time, the PNi number is issued at a second input of the XOR gate 11.

Furthermore, the data word Wi and pseudo random PNi are combined by the corresponding XOR gate 11, so as to generate a The encrypted data word.

The encryption unit 38 then stores the password in the memory Ci external 23 and and in combination with the initialization vector IVi and kidi the secret key ID that was used to encrypt it. In this writing, the encrypted data word Ci, the initialization vector and the identifier of IVi secret key kidi transiting Intermed iaire the communication bus 3. This however, is not a weakness of security of the encryption method in the Since the word Ci is encrypted, where the IV is not enough to IVi alone to perform decryption, and which has no identifier kidi meaning for another circuit which does not have the secret key associated to this identifier.

The operation of the circuit in decryption mode is now exposed by considering the dotted line arrows shown in Figure 2.

Under control of the processor core 44, data words figures are read from the external memory 23 at given addresses. Every word Cj thus read is delivered to the first input of the XOR gate 11. For each word Cj, the initialization vector IVj and the key identifier KIDj secret associated with that word, are also read into memory External 23.

From the KIDj identifier, the decryption unit 38 selects the secret key Kj associated with this identifier by searching the list of secret keys stored in the register set 32. The key Kj and selected is stored in the register 12. In parallel, the vector is IVj stored in the register 13.

In fact, the IVj vector and KIDj identifier transiting memory Cache 25. This caching improves performance the decryption unit, in decryption speed term. The pseudo-random generator 10 generates a pseudo random number to PNI From the K key stored in the register 12 and stored in the vector IVj register 13. The PN number is issued on the second input of the gate XOR 11.

The XOR gate 11 combines the encrypted data Cj of word and number pseudorandom PNI and outputs a corresponding data word Wj the word Cj deciphered.

The decrypted data word Wj is then supplied to the processor core 44 through the cache 33.

Of course, the present invention is capable of various variations and modifications which will occur to the skilled person. In particular, the invention may be implemented with any algorithm known stream cipher, conditioning the pseudorandom generator 10 From the secret key and initialization vector. In addition, it is assumed that the practical embodiment of the invention is within the reach of the skilled person to From the functional indications given above. In this regard, note that, according to one embodiment of the invention described herein, the various tools Encryption and decryption are realized by hardware resources processor. However, implementation by software resources is of course conceivable.

In addition, the invention is not limited in any way to application in a processor. On the contrary, an encryption / decryption unit such as unit 38 described above may be provided in other circuits of a electronic apparatus as shown in Figure 1, particularly in the disk controller or network card.

Note also that all of the data stored in the external memory does not have to be encrypted. In this regard, one can provide that a key identifier with the value zero indicates no encryption of the corresponding data word, that is to say, said word Data is stored in the clear in the external memory.