Nova Patents
EP1517243A2

Memory interleave system

Abstract

A memory interleave system includes M (M is 2p0 where p is a natural number) memory banks, N (a natural number) CPUs, N address generating units, and M memory control units. Each memory bank includes a plurality of memories. The CPUs output memory requests as access requests to the memory banks. Each memory request contains the first bank address which is the address of the memory bank and the first intra-bank address which is the address of a memory in the memory bank. The address generating units respectively correspond to the CPUs. Each address generating unit receives a memory request from a corresponding CPU, and newly generates and outputs the second intra-bank address and the second bank address by using the first intra-bank address and the first bank address which are contained in the memory request. The memory control units respectively correspond to the memory banks. Each memory control unit performs memory bank access control on the basis of the second intra-bank address output from the address generating unit. A memory control unit which performs access control is selected on the basis of the second bank address output from the address generating unit.

EP1517243A2, drawing sheet 1
Sheet 1 of 7

Term

Term ended

Projected expiry passed 13 September 2024, 2 years ago.

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19 claims: 1 independent, 18 dependent

  1. 1
    A memory interleave system characterized by comprising:M (M is 2p0 where p is a natural number) memory banks (160 - 16M-1) each including a plurality of memories;N (a natural number) computing means (100 - 10N-1) for outputting memory requests as access requests to said memory banks, the memory request containing a first bank address which is an address of said memory bank and a first intra-bank address which is an address of a memory in said memory bank;N address generating means (120 - 12N-1) respectively corresponding to said computing means, said address generating means receiving a memory request from said computing means, and newly generating and outputting a second intra-bank address and a second bank address by using the first intra-bank address and the first bank address which are contained in the memory request;andM memory control means (150 - 15M-1) respectively corresponding to said memory banks, said memory control means performing memory bank access control on the basis of the second intra-bank address output from said address generating means, and said memory control means which is to perform access control being selected on the basis of the second bank address output from said address generating means.