X-ray and gamma-ray imaging device

Field of the Invention

The present invention is in the field of semiconductor devices for detecting and image analyzing x-ray and gamma ray radiant energy above 1 keV. More specifically, the present invention relates to such devices wherein image analysis occurs by way of incident radiant energy on the device producing current flow between two electrically accessible points on two different semiconductor substrates separated by an intermediate substrate.

Background of the Invention

Over the past ten years digital radiation imaging has gradually been replacing conventional radiation imaging where the recording means is film or an analog device such as an Image Intensifier. Currently, several such devices are available that can perform digital radiation imaging. In some cases, incident radiation is detected and converted locally into an electronic signal which is then collected at collection/pixel contacts and then further transmitted to readout circuits which perform various functions including digitization. In other cases, the radiation is detected and converted into light which is then converted to an electronic signal and subsequently is readout and digitized. The first cases we refer to as "direct radiation detection," and the second cases we refer to as "indirect radiation detection."

Direct radiation detection devices typically comprise a semiconductor detector substrate conductively bonded to a semiconductor readout substrate. The detector substrate is made of a photo-conductor material which converts incoming radiation into electronic signals. The readout substrate accumulates such electronic signals, processes them and reads them out. There are different kind of photo-conductor substrate technologies and different readout substrate technologies. Table I broadly summarizes various types of direct radiation digital imaging technologies, and lists typical cases in each technology group.

The following terms as used herein have their standard meaning in the electronics literature: CCD stands for Charge Coupled Device, ASIC stands for Application Specific Integrated Circuit, TFT stands for Thin Film Transistor array. Detectors are materials or devices whose response to X-ray energy is used to indicate the presence or amount of radiation incident on the detector. X-rays are electromagnetic radiation lying in a range between "cosmic rays" and "ultraviolet rays." This range is defined as lying between 0.001 and 100 angstrom units or 10^-11 and 10^-6 centimeters in wavelength. As used herein, the term "gamma ray" is considered to be synonymous with the term "X-ray." Gamma rays are usually considered to be produced by some natural phenomenon such as the decay of an atomic nucleus whereas X-rays are usually considered to be produced by an electronic tube or other manufactured device. <tables id="tabl0001" num="0001"><table frame="all"><title><b>TABLE I</b></title><tgroup cols="4"><colspec colnum="1" colname="col1" colwidth="22mm" /><colspec colnum="2" colname="col2" colwidth="47mm" /><colspec colnum="3" colname="col3" colwidth="54mm" /><colspec colnum="4" colname="col4" colwidth="43mm" /><thead><row><entry namest="col1" nameend="col4" align="center" valign="top"><b>Radiant Energy, Direct Digital Imaging Technologies</b></entry></row><row><entry align="center" valign="top">Technology</entry><entry align="center" valign="top">Detector Substrate</entry><entry align="center" valign="top">Readout Substrate</entry><entry align="center" valign="top">Substrate Interface</entry></row></thead><tbody><row><entry>SBBASIC</entry><entry>CdTe; CdZnTe; Si; Ge; GaAs; TIBr; PbI; MgI; etc.</entry><entry>CMOS; BiCMOS; HBIMOS; SiGe; Mixed Signal/RF; Logic; etc.</entry><entry>Bump-bonds</entry></row><row><entry>a-SGTFT</entry><entry>a-Se; a-CdZnTe; a-CdTe; etc.</entry><entry>a-Si:H TFT</entry><entry>Epitaxial growth; Evaporation; etc.</entry></row><row><entry>a-SGASIC</entry><entry>a-Se; a-CdZnTe; a-CdTe; a-PbI; etc.</entry><entry>CMOS; BiCMOS; HBIMOS; SiGe; Mixed Signal/RF; Logic; etc.;</entry><entry>Epitaxial growth; Evaporation; etc.</entry></row></tbody></tgroup><tgroup cols="4" rowsep="0"><colspec colnum="1" colname="col1" colwidth="22mm" /><colspec colnum="2" colname="col2" colwidth="47mm" /><colspec colnum="3" colname="col3" colwidth="54mm" /><colspec colnum="4" colname="col4" colwidth="43mm" /><tbody><row><entry namest="col1" nameend="col4" align="justify"><b>Abbreviations</b>: SBBASIC = Semiconductor Bump Bonded on ASIC; a-SGTFT = amorphous Semiconductor Grown on TFT; a-SGASIC = amorphous Semiconductor Grown on ASIC.</entry></row></tbody></tgroup></table></tables>

Digital radiation imaging devices utilizing SBBASIC technologies are known in the art, and typically comprise a crystalline detector semiconductor substrate (photo-conductor) and a semiconductor readout substrate incorporating integrally processed ASICs. The detector and readout substrates are joined together and electrically communicate by means of bump-bonds or other conductive means. The detector substrate has a continuous electrode on a first major face (where incident radiation impinges) and a two dimensional array of charge collecting/pixel contacts or electrodes on a second major face, opposite the first major face. Incident radiation is absorbed in the material of the detector substrate and electrical charge is generated in response to such absorption. Under the bias of an electric field between the first and second faces, the generated charge drifts toward and is collected at the charge collection/pixel contacts or electrodes. Each charge collection contact defines a separate "pixel" on the detector substrate and is conductively connected to a corresponding "pixel circuit" on the readout substrate by a bump-bond. Each pixel in combination with its corresponding pixel circuit comprises a "pixel cell." Each pixel circuit on the readout substrate may include various circuit features for amplifying, storing, digitizing, etc. the incoming charges. The bump-bonds may be accomplished using a variety of metals or compounds including various solder alloys and other conductive compositions.

Typically, at a perimeter edge of each readout substrate there is at least one region for routing input and output (I/O) signals to and from the readout substrate. These can be wire bonding pads or similar features for providing electrical connections to the ASICs of the readout substrate.

<patcit id="pcit0001" dnum="US5379336A"><text>Kramer et al., US Patent No. 5,379,336</text></patcit>, disclose a typical SBBASIC device, see <figref idref="f0001">Figs 1A and 1B</figref>. As shown in the figures, a semiconductor detector substrate <b>10</b> is bump bonded with an array of conductive bumps <b>13</b> to a readout/processing substrate <b>12.</b> Both the semiconductor detector substrate <b>10</b> and the semiconductor readout/processing substrate <b>12</b> are each integral and monolithic. Examples of detector and readout/processing substrate technologies is given in Table I. Radiation <b>hv</b> is incident on the top (first major face) of the detector semiconductor substrate <b>10.</b> A pixel array is formed by means of metal charge collection/pixel contacts on the exit face (second major face) of the detector semiconductor substrate <b>12.</b> Electrical charge created in the semiconductor detector substrate <b>10</b> in response to absorption of incident radiation <b>hv</b> is collected by the detector pixel contacts <b>14.</b> The collected charge is communicated through the conductive bumps <b>13</b> to corresponding pixel circuit contacts <b>15</b> on the readout/processing semiconductor substrate <b>12.</b> The pixel circuits are used to perform a variety of possible functions including accumulating the incoming charge and/or amplifying it, discriminating, digitizing, counting incomings radiation hits, etc.

<patcit id="pcit0002" dnum="US5812191A"><text>Orava et al., US Patent No. 5,812,191</text></patcit> and <patcit id="pcit0003" dnum="US5952646A"><text>Spartiotis et al., US Patent No. 5,952,646</text></patcit>, both disclose alternative embodiments of an SBBASIC-type digital radiation imaging devices. In these imaging devices as generally exemplified in <figref idref="f0002">Fig. 2</figref>, the detector semiconductor substrate <b>30</b> is electrically connected to the readout semiconductor substrate <b>32</b> with bump-bonds <b>35.</b> The photo-detector material <b>34</b> of the semiconductor substrate pixels <b>36</b> absorbs incoming radiation, and in response to the absorption generates electrical charges. The electrical charges are collected at collection/pixel contacts <b>38,</b> and electrically communicated through the bump-bonds <b>35</b> to the pixel circuit contacts <b>33</b> on the pixel circuit <b>31</b> of the readout semiconductor substrate <b>32.</b>

However, the above noted SBBASIC imaging devices are unitary devices with an imaging area that is limited by current semiconductor manufacturing and bump-bonding technologies. At present, some of the most sensitive photo-conductor materials, such as CdTe, CdZnTe, TlBr, PbI, and GaAs, can be used to manufacture single crystal semiconductor substrates without defects having dimensions of only about 3" or 4". Imaging area is even more limited with the CMOS technology typically used to create the semiconductor readout substrates. These technologies typically can produce radiation imaging devices having active imaging areas of at most a few square centimeters. Even if semiconductor substrate dimensions are increased, current bump-bonding technology would still limit the planar area of the detector and readout substrates that can be bonded together (e.g., a 10cm x 10cm monolithic detector substrate to its readout substrate). An additional concern for the bonding of the detector and readout substrates together is the flatness of the substrates and the uniformity of the conductive bump needed to accomplish the process.

Patent documents <patcit id="pcit0004" dnum="US5786597A"><text>US-A-5 786 597</text></patcit> and <patcit id="pcit0005" dnum="US5635718A"><text>US-A-5 635 718</text></patcit> also disclose radiation detecting devices comprising an intermediate substrate.

In view of these limitations, the field has been motivated to develop technologies that make it possible to industrially perform high density bump-bonding operations between single semiconductor substrate pairs. For example, "tiling" techniques have been developed in which a plurality of digital radiation imaging device units are "tiled" together in a one or two dimensional array to form a larger imaging device mosaic. Tiling of individual digital imaging devices allows production of digital radiation imaging devices having much larger imaging areas. However, tiling techniques have also introduced an amount of imaging dead area into the imaging area of the mosaic imaging device, which can adversely affect device's image quality. This imaging dead area is primarily resultant from the planar area of an individual digital imaging device tile that is required to provide the I/O connections to the individual device, e.g., the wire bonding area. Even though the depth of the wire bonding area is typically a few mm, it can create an imaging dead area that is unacceptably large for a particular radiation imaging application.

Therefore, the field has been further motivated to develop tiling techniques that reduce the amount of dead area in a mosaic or arrayed digital imaging device. <figref idref="f0003">Figures 3A and 3B</figref> illustrate an early attempt from <patcit id="pcit0006" dnum="EP0421869A"><text>Lemercier et al., EP 0421869</text></patcit>, to reduce the wire bonding area <b>61</b> and other possible edge-most inactive or imaging dead areas <b>61a</b> on one or two sides of an SBBASIC by overlapping some of the imaging dead areas <b>61</b> with active detector area <b>62</b> in a "stair case" arrangement of individual SBBASIC tiles. The whole "stair case" is mounted on a support <b>60.</b> Although this technique does reduce the total amount of imaging dead area of an imaging device array, some perimeter dead areas <b>61</b> still remain. Additionally, in order to maximize image quality, the surfaces of all the individual SBBASIC tiles must be parallel to each other. This is mechanically difficult in the production of imaging devices like the Lemercier device. Further, the "stair case" approach required that to achieve larger the imaging areas, the support substrate <b>60</b> must be made relatively thicker in two directions.

In order to overcome the limitation of needing a double-ramped support substrate as in the Lemercier device, the field has developed alternative tiling techniques. One example shown in <figref idref="f0004">Fig. 4</figref> is that of Schulman, <patcit id="pcit0007" dnum="EP1162833A"><text>EP 1162833</text></patcit>, whereby imaging device tiles <b>56</b> &amp; <b>58</b> are removably mounted on a support board. On one edge of the readout substrate <b>52</b> there is an imaging dead area <b>50</b> which extends beyond detector substrate <b>51</b> of the device tile <b>56</b> or <b>58</b> and is reserved for wire bonding. The wire bonding area is not sensitive to radiation and does not perform imaging. Each SBBASIC is mounted on a combination wedge <b>44</b> and platform <b>53,</b> which in turn is mounted on a PC board <b>54.</b> The wedge-platform combination allows the inactive area <b>50</b> of one imaging device tile <b>58</b> to at least partially go under the active imaging area another imaging device tile <b>56.</b> This technique is complicated in its execution because the wedge-platform requires careful control of the tilt angle and precise alignment of the tile devices relative to each other. Further more, the inactive area is never completely covered and the tile angle can introduce a parallax error depending on the angle of incidence of the incoming radiation.

While the SBBASIC technology is relatively the newest approach to direct radiation digital imaging and has advantages over the other prior radiation digital imaging technologies, it also currently has certain limitations: <ol id="ol0001" compact="compact"><li>a. In current devices, the detector and readout substrates are manufactured with a limited field of view. Field of views of single devices of only up to 2.5 cm² have been reported. This is insufficient for most commercial applications.</li><li>b. Due to this limitation, tiling techniques that combine a plurality of SBBASIC devices have been suggested to provide a larger field of view. However, such tiling techniques can be cumbersome and difficult to implement on an industrial production scale. This can adversely impact the quality of imaging and the cost of the complete camera head comprising a plurality of such SBBASICs.</li><li>c. In addition to the limitation of (a) and (b) above, in current SBBASIC imaging devices, the interconnection of the ASIC with wire bonding pads introduces an "inactive" area for each SBBASIC device. This is an area that is not useable to image incoming radiation. Such "dead" areas adversely impact image quality, especially when they are too large to cancel them out by software.</li></ol>

Although each of the above radiation imaging devices may be useful for their intended purposes, it would be beneficial in the field to have an alternative radiation imaging device that eliminates or further minimizes imaging dead area due to wire bonding requirements of the ASICs involved, without requiring a support ramp. Additionally, it would be beneficial to have the semiconductor tiles mounted in the same plane. It would be further beneficial if the device can be produced using current bump-bonding techniques in combination with the new high sensitivity semiconductor materials that can be mechanically brittle and susceptible to relatively high bumping temperatures.

Summary of the Invention

The present invention is a "Semiconductor Detector Via Connected to Application Specific Integrated Circuit" (SVCASIC) type radiation imaging device. Structurally, this means that a semiconductor/photo-conductor substrate is physically bonded to an intermediate or "via" substrate, which is in turn physically bonded to a processing/readout (ASIC) substrate. Functionally, the intermediate or via substrate provides electrical communication between the photo-detector substrate and the readout substrate. Additionally, the intermediate substrate provides electrical communication between the ASICs of the readout substrate and between the present imaging device and any circuits external to the imaging device.

The present invention is an SVCASIC type x-ray and gamma-ray radiation energy imaging device comprising a semiconductor detector substrate and a readout/processor substrate which are separated by and bound to an intermediate substrate in a laminate-like configuration. The semiconductor substrates and the intermediate substrate of the present invention generally have a planar configuration and are disposed adjacent each other with their planes in a parallel. In its simplest configuration, the present radiation imaging device comprises a single detector substrate, a single readout substrate and a single intermediate substrate. However, an object of the present invention is an imaging device comprising an array of detector substrates and a corresponding array of readout substrates which are separated by and bound to a single intermediate substrate, again, in a laminate-like configuration.

The semiconductor detector substrates practicable in the present invention are known in the art. Typically, the semiconductor detector substrate has a planar configuration and two major opposing planar surfaces: an electrode surface and a pixel surface. The detector semiconductor substrate also comprises a photo-conductor material disposed between the two major surfaces. The photo-conductor material converts radiation energy impinging on the electrode surface to electrical charges within the thickness of the photo-conductor material. The detector substrate has an electric field bias acting to cause an electric charge generated within the thickness of the photo-conductor in response to absorbed radiation to drift directly toward the pixel surface of the detector substrate. An electric field bias can be accomplished by having a charge biasing electrode disposed continuously across the electrode surface of the detector substrate.

On the pixel surface of a unitary detector substrate is a plurality of pixels. The total area and configuration of the pixels define the active imaging area of the detector substrate. Preferably, the plurality of pixels have a total surface area substantially equal to the total surface area of the pixel surface. In this situation, the shadow perimeter of the unitary detector substrate is a factor in determining the relationship between image size and image quality of the final imaging device (for a given detector substrate pixel density). Each pixel has an associated charge collector electrode and contact. The pixel collector contacts are disposed in a collector contact pattern on the pixel surface of the detector substrate. The pixel electrodes/contacts collect drifting electrical charges generated within the detector substrate.

The semiconductor readout/processing substrates practicable in the present invention are generally known in the art. Typically, a semiconductor readout substrate comprises at least one application specific integrated circuit (ASIC), and has a planar configuration and two major opposing planar surfaces. One of the major surfaces is a readout surface, which is disposed opposite the pixel surface of the detector substrate. The ASIC readout substrate further comprises a plurality of pixel circuits, each pixel circuit having an electrical transmission contact processed onto the readout surface of the ASIC semiconductor readout substrate. The transmission contacts are the inputs to the pixel circuits of the ASIC readout substrate. The electrical transmission contacts are disposed in a transmission contact pattern.

Additionally, the semiconductor ASIC readout/processing substrate of the present invention has a plurality of electrical I/O contacts processed onto the readout surface of the ASIC semiconductor substrate. The I/O contacts are the input and output electrical contacts for the ASIC(s) of the semiconductor readout substrate, and are disposed in an I/O contact pattern.

The intermediate substrate is disposed between the semiconductor detector substrate and the ASIC semiconductor readout substrate. Typically, the intermediate substrate has a planar configuration and two major opposing planar surfaces: an entry face disposed adjacent the pixel surface of the detector substrate, and an exit face disposed adjacent the readout surface of the ASIC readout substrate. A plurality of discrete conductive via passages provide discrete electrical communication paths between the entry and exit faces through the thickness of the intermediate substrate. The via passages have a first end at the entry face disposed in an entry passage pattern (corresponding to the pixel pattern of the detector substrate) and a second end at the exit face disposed in an exit passage pattern (corresponding to the transmission contact pattern of the readout substrate). Additionally, a plurality of wire contacts are disposed on the exit face in a wire contact pattern corresponding to the I/O contact pattern on the readout surface of the ASIC semiconductor readout substrate. The wire contacts are in electrical communication with wire bonding pads mounted on a peripheral edge of the intermediate substrate.

The conductive via passages are apertures or holes through the thickness of the material of the intermediate substrate. The via passages have a lining comprised of an electrically conductive material (e.g, Copper, Gold, Silver, Nickel, Aluminum, Platinum, Lead, Tin, Bismuth and Indium or combination thereof) to make the passage conductive. Alternatively, the via passages are filled with a conductive material (e.g., solder) to make the passages conductive. Optionally, the conductive via passages can each electrically communicate with a discrete conductive skirt at the end of passage on at least one of the faces of the intermediate substrate. The skirt can be separately processed on to the face of the intermediate substrate using circuit substrate technologies known in the art, and can be integral with the via passage conductive lining. The intermediate substrate itself can be make of any of a variety of materials known in the art, such as: a printed circuit board, a photo-resist material, an F4 material, and a ceramic material.

Optionally, the wire contacts of the intermediate substrate can be recessed into the exit face of the intermediate substrate, and the recesses lined or filled with a conductive material as are the via passages. This allows an electrical pathway communicating with a wire contact run through the thickness of the intermediate substrate and to be insulated from either entry face or the exit face.

The semiconductor substrates (i.e., the detector/photo-conductor substrate and the ASIC readout substrate) are each bonded to the appropriate face of the intermediate substrate - the detector substrate to the entry face and readout substrate to the exit face. This is accomplished by electrically conductive bonds discretely connecting each pixel contact in the pixel pattern of the detector substrate to the first end of the corresponding conductive via passage of the entry passage pattern on the entry face of the intermediate substrate. Similarly, electrically conductive bonds discretely connect each transmission contact in the transmission contact pattern of the readout substrate to the second end of the corresponding conductive via passage of the exit passage pattern on the exit face of the intermediate substrate. Additionally, electrically conductive bonds discretely connect each I/O contact in the I/O contact pattern of the readout surface of the readout substrate with the corresponding wire contact in the wire contact pattern on the exit face of the intermediate substrate.

Bonding techniques practicable in the present invention are known in the art. Conductive bonding of the various electrical contacts of the semiconductor substrates to the intermediate substrate is readily accomplishable in the present invention by one of ordinary skill in the art. For example, such bonding can be accomplished using bump-bonds or conductive adhesives, especially anisotropic conductive adhesives. See <nplcit id="ncit0001" npl-type="s"><text>Mescher et al., Application Specific Flip Chip Packages: Considerations and Options in Using FCIP, Proc. Pan Pacific Microelectronics Symp. Conf., Jan. 2000</text></nplcit>; <patcit id="pcit0008" dnum="US6356453B"><text>Juskey et al., U.S. Patent No. 6,356,453</text></patcit>; and <nplcit id="ncit0002" npl-type="s" url="http://www.btechcorp.com/aecfmain.htm"><text>Btechcorp., ATTA® Anisotropic Electrically Conductive Film, http://www.btechcorp.com/aecfmain.htm, May 2002</text></nplcit>.

The architecture of the present invention utilizing an intermediate substrate as a mounting platform for the semiconductor substrates accomplishes several benefits desirable in a radiation imaging device. One of the benefits is the potential for producing larger area imaging devices with improved image quality relative to some prior devices by reducing or minimizing the amount of imaging dead area in the device. This is accomplished by having an entire ASIC readout substrate, including its I/O contacts, disposed within the "perimeter shadow" of its associated detector substrate. In this configuration, the ASIC readout substrate has no perimeter edge extending beyond the perimeter shadow of the detector substrate. Therefore, unitary detector substrates may be close packed using tiling techniques to form a mosaic imaging device that has minimized imaging dead area, because the underlying unitary readout substrates themselves do not have an imaging dead area.

Another potential benefit is the facilitation of production of radiation energy imaging devices that utilize semiconductor substrates which are sensitive to the temperatures and pressures of certain prior semiconductor radiation imaging device manufacture methods and technologies. For example, in situations where the semiconductor substrate is brittle, or is comprised of temperature sensitive materials, such detector substrates comprises Cadmium and/or Tellurium. This is particularly the case where solder bump-bonding is to be used to bond the conductive contacts of the semiconductor substrates. By initially applying the solder bumps to the conductive contacts on the intermediate substrate, the semiconductor substrates are not exposed to the sometimes harsher conditions required to initially make bumped contacts. The intermediate substrate is not a semiconductor substrate, and may be made of relatively more rugged materials as selectable by one of skill in the art to withstand the initial bumping conditions. Once the conductive contacts on a face of the intermediate substrate are bumped, conductive bonding to the corresponding conductive contacts of a sensitive semiconductor substrate may be accomplished using the potentially less harsh conditions of solder reflow techniques.

The present invention includes a method of producing a radiation energy imaging device by providing an intermediate substrate of the type detailed above, and applying solder or other conductive bumps to the conductive contacts (i.e., the via passages and any wire contacts) on a face of the intermediate substrate to provide an intermediate substrate face with bumped contacts. Then the appropriate semiconductor (detector or readout) substrate is placed in juxtaposition with the intermediate substrate face with solder bumped contacts, with the solder bumped contacts closely proximate or touching the corresponding contacts on the semiconductor substrate. Next the intermediate and semiconductor substrates are bonded together by causing the solder of the solder bumped contacts to reflow under appropriate conditions of heat and pressure to form solder bump-bonds between the solder bumped contacts of the intermediate substrate and the corresponding contacts on the semiconductor substrate. If conductive bumps made of a material other than solder are used, then the appropriate application of temperature and pressure for that material is used to cause the formation of the bump-bonds. Alternatively, the conductive bumps may be initially applied to the semiconductor substrate, if the susceptibility of the semiconductor material is not controlling.

In an alternative method of bonding the semiconductor substrates to the intermediate substrate, conductive adhesives can be used. For example, an conductive adhesive can be applied to the conductive contacts on one or both faces of the intermediate substrate or to the conductive contacts on the semiconductor (detector and/or readout) substrates or to both, to provide conductive adhesive coated contacts. Optionally, an anisotropically conductive adhesive film can be applied between the surfaces and/or faces of the semiconductor and intermediate substrates, including all of the conductive contacts of the substrates. The semiconductor substrates can then be bound to the intermediate substrate in a manner similar to that detailed above for bump-bonding, or otherwise known to one of ordinary skill in the art.

Brief Description of the Drawings

<ul id="ul0001" list-style="none"><li><figref idref="f0001">Fig. 1A</figref> is a perspective illustration of a prior art SBBASIC-type radiation digital imaging device having bump-bonded detector and readout substrates.</li><li><figref idref="f0001">Fig. 1B</figref> is close up perspective view of a single pixel cell of <figref idref="f0001">Figure 1A</figref>.</li><li><figref idref="f0002">Fig. 2</figref> is a cross-sectional view of a prior art SBBASIC-type semiconductor radiation imaging device.</li><li><figref idref="f0003">Figs. 3A and 3B</figref> respectively are a perspective view (A) and a side view (B) representation of a prior art mosaic radiation imaging device where individual imaging devices (tiles) are arrayed in two dimensions in order to provide an increased image area imaging device.</li><li><figref idref="f0004">Fig. 4</figref> is a side view representation of a prior art mosaic radiation imaging device where individual imaging devices (tiles) are arranged to have the active imaging area of one imaging device or tile overlap the imaging dead area of another imaging device tile.</li><li><figref idref="f0005">Fig. 5</figref> is a schematic representation of a device of the present invention comprising unitary detector and readout semiconductor substrates, mounted in a laminate or layered configuration on a single intermediate or "via" substrate.</li><li><figref idref="f0006">Figs. 6A</figref> and <figref idref="f0007">6B</figref> are a side view schematic representation of a device of the present invention showing the relationship between the detector and readout substrates to the intermediate substrate. The intermediate substrate is in cross section to show the relationship of the various electrical contacts between the substrates.</li><li><figref idref="f0008">Fig. 7A</figref> is a schematic illustrating the pixel surface of an exemplary semiconductor detector substrate.</li><li><figref idref="f0009">Fig. 7B</figref> is a schematic illustrating the pixel contact pattern on the pixel surface of the exemplary semiconductor detector substrate of <figref idref="f0008">Fig. 7A</figref>.</li><li><figref idref="f0010">Fig. 8A</figref> is a schematic illustrating the readout surface of an exemplary semiconductor ASIC readout substrate.</li><li><figref idref="f0011">Fig. 8B</figref> is a schematic illustrating the transmission contact pattern on the readout surface of the exemplary semiconductor readout substrate of <figref idref="f0010">Fig. 8A</figref>.</li><li><figref idref="f0012">Fig. 8C</figref> is a schematic illustrating the I/O contact pattern on the readout surface of the exemplary semiconductor readout substrate of <figref idref="f0010">Fig. 8A</figref>.</li><li><figref idref="f0013">Fig.9A</figref> is a schematic illustrating the entry face of an exemplary intermediate substrate, and showing via passage first ends having conductive skirts.</li><li><figref idref="f0014">Fig. 9B</figref> is a schematic illustrating the exit face of an exemplary intermediate substrate, and showing via passage second ends without conductive skirts.</li><li><figref idref="f0015">Fig. 10</figref> is a cross sectional side view exemplifying of a portion of an intermediate substrate.</li><li><figref idref="f0016">Fig. 11</figref> is a side view schematic representation of a SVCASIC mosaic imaging device of the present invention showing the relationship between an array of detector and an array readout substrates to the single intermediate substrate. The intermediate substrate is in cross section to show the relationship of the various electrical contacts between the substrates.</li></ul>

Detailed Description of the Invention

Referring now to the drawings, the details of preferred embodiments of the present invention are graphically and schematically illustrated. Like elements in the drawings are represented by like numbers, and any similar elements are represented by like numbers with a different lower case letter suffix.

As exemplified in <figref idref="f0005">Fig. 5A</figref>, in a preferred embodiment, the present invention is a SVCASIC type digital imaging device <b>80</b> for imaging x-ray and gamma-ray radiation energy preferably in the energy range of 1 keV to 500 keV. The digital SVCASIC imaging device <b>80</b> comprises two semiconductor substrates, a detector substrate <b>90</b> and a readout/signal processing substrate <b>130,</b> separated by and bonded to an intermediate substrate <b>170.</b> The substrates <b>90, 130</b> &amp; <b>170</b> have a substantially planar configuration and are disposed adjacent each other with their planes in a parallel to form a laminate structure in the assembled imaging device <b>80.</b> In an alternative preferred embodiment exemplified in <figref idref="f0005">Fig. 5B</figref>, the radiation energy imaging device <b>80a</b> comprises a plurality of detector substrates <b>90</b> and a plurality of ASIC readout substrates <b>130</b> bonded to a single intermediate substrate <b>170.</b>

In a preferred embodiment as exemplified in <figref idref="f0006">Figs. 6A</figref> and <figref idref="f0007">6B</figref>, the semiconductor detector substrate <b>90</b> has a planar configuration and two major opposing planar surfaces: an electrode surface <b>92</b> and a pixel surface <b>94.</b> The thickness <b>T</b> of the detector substrate <b>90</b> is comprised of a photo-conductor <b>96,</b> such as are known in the art, including CdTe, CdZnTe, PbI, TlBr, HgI, Ge, GaAs, Si, and others. Radiation energy <b>hv</b> impinging on the electrode surface <b>92</b> is absorbed by the photo-conductor <b>96</b> and converted to electrical charges (not shown). Under the influence of an electric field bias (not shown), the electric charges generated within the thickness <b>T</b> of the photo-conductor <b>96</b> in response to absorption of the impinging radiation <b>hv</b> are caused to drift directly toward the pixel surface <b>94</b> of the detector substrate <b>90.</b> An electric bias field can be accomplished by any of a number of means known to one of ordinary skill in the art. However, in the embodiment illustrated, a charged biasing electrode <b>98</b> is disposed continuously across the electrode surface <b>92</b> of the detector substrate <b>90.</b> The electrical charge on the biasing electrode <b>98</b> creates the electric bias field which causes the drift of the electrical charges toward the pixel surface <b>94.</b> The biasing electrode <b>98</b> is substantially transparent to the impinging radiation <b>hv.</b>

As exemplified in <figref idref="f0008">Fig. 7A</figref>, a plurality of pixels <b>100</b> and associated pixel collector electrodes/contacts <b>102</b> are disposed on the pixel surface <b>94</b> of the detector substrate <b>90.</b> Each pixel collector electrode/contact <b>102</b> corresponds to an individual pixel <b>100.</b> The pixel collector electrodes/contacts <b>102</b> are electrically conductive contacts for collecting the electrical charges generated in their associated pixels <b>100</b> by the absorption of radiation <b>hv.</b> The pixel collector contacts <b>102</b> are arranged in a pixel contact pattern <b>104</b> (see <figref idref="f0009">Fig. 7B</figref>).

As exemplified in <figref idref="f0010">Fig. 8A</figref>, in the preferred embodiment, the semiconductor ASIC readout substrate <b>130</b> comprises a plurality of ASIC pixel circuits <b>132.</b> Additionally, the ASIC readout substrate <b>130</b> has a readout surface <b>134,</b> which in the assembled imaging device <b>80</b> is disposed opposite the pixel surface <b>94</b> of the detector substrate <b>90</b> (also see <figref idref="f0006">Fig. 6A</figref>). Each pixel circuit <b>132</b> includes an electrical transmission contact <b>136</b> processed on the readout surface <b>134</b> of the semiconductor readout substrate <b>130.</b> Each transmission contact <b>136</b> is the input to pixel circuit (processing/readout cell) <b>132.</b> The ASIC processing/readout substrate <b>130</b> comprise one or more ASICs, preferable created with CMOS or other available ASIC processes. The transmission contacts <b>136</b> are the electrical charge radiation signal inputs to their respective pixel circuit <b>132</b> of the ASIC readout substrate <b>130.</b> The transmission contacts <b>136</b> are arranged in a transmission contact pattern <b>150</b> (see <figref idref="f0011">Fig 8B</figref>).

Additionally, the ASIC readout substrate <b>130</b> comprises a plurality of electrical I/O contacts <b>140</b> processed on the readout surface <b>134</b> of the semiconductor readout substrate <b>130.</b> The I/O contacts <b>140</b> are the input and output electrical contacts for the ASIC readout substrate <b>130</b> by which control, processing and imaging signals are communicated to the ASIC(s) of the readout substrate <b>130.</b> The I/O contacts <b>140</b> are arranged in an I/O contact pattern <b>152</b> (see <figref idref="f0012">Fig 8C</figref>).

The intermediate substrate <b>170</b> is disposed between the detector substrate <b>90</b> and the ASIC readout substrate <b>130</b> (see <figref idref="f0005">Figs. 5</figref> and <figref idref="f0006 f0007">6</figref>). As shown in <figref idref="f0013">Figs. 9A</figref> and <figref idref="f0014">9B</figref>, the intermediate substrate <b>170</b> has an entry face <b>172</b> and an exit face <b>174</b> (also see <figref idref="f0006">Fig. 6A</figref>). In the assembled SVCASIC imaging device <b>80,</b> the entry face <b>172</b> is adjacent the pixel surface <b>94</b> of the detector substrate <b>90,</b> and an exit face <b>174</b> is adjacent the readout surface <b>134</b> of the ASIC readout substrate <b>130.</b> In a preferred embodiment, the intermediate substrate <b>170</b> is a printed circuit board (PC board). However, other embodiments of the intermediate substrate <b>170</b> are intended and are known to and practicable in the present imaging device <b>80</b> by one of skill in the art. These include: a photo-resist material, an FR4 material, and a ceramic material. Advantages of incorporating the intermediate substrate in the SVCASIC imaging device <b>80</b> include that it is easily produced, can be produced with several layers, and it provides a robust and mechanically stable platform on which to mount the semiconductor substrates <b>90</b> &amp; <b>130.</b>

The intermediate substrate <b>170</b> has a plurality of conductive via passages <b>178</b> which provide discrete, electrically conductive pathways between the entry and exit faces <b>172</b> &amp; <b>174</b> of the intermediate substrate <b>170.</b> Preferably, the via passages <b>178</b> are cylindrical. The via passages <b>178</b> have a first end <b>180</b> at the entry face <b>172</b> of the intermediate substrate <b>170,</b> and a second end <b>182</b> at the exit face <b>174.</b> The via passages <b>178</b> comprise a lining of an electrically conductive material to make the via passages <b>178</b> conductive. Preferably, the lining is made of Copper, but can be any electrically conductive material selectable by one of ordinary skill in the art from among such as: Gold, Silver, Nickel, Aluminum, Platinum, Lead, Tin, Bismuth and Indium. Alternatively, the via passages of the intermediate substrate <b>170</b> may be filled with an electrically conductive material (e.g., solder or a conductive adhesive, see below) to make the via passage conductive.

The via passage first ends <b>180</b> are arranged on the entry face <b>172</b> in an entry passage pattern (not shown) corresponding to the pixel contact pattern <b>104</b> (see <figref idref="f0009">Fig. 7B</figref>) on the pixel surface <b>94</b> of the detector substrate <b>90.</b> The via passage second ends <b>182</b> are arranged on the exit face <b>174</b> in an exit passage pattern (not shown) corresponding to the transmission contact pattern <b>150</b> (see <figref idref="f0011">Fig. 8B</figref>) on the readout surface <b>134</b> of the ASIC readout/processing substrate <b>130.</b> The via passage ends <b>180</b> &amp; <b>182</b> are the conductive contacts of the via passages <b>178.</b> Optionally, the via passages can include a discrete conductive skirt <b>184</b> at the via passage ends <b>180</b> &amp; <b>182</b> on one or both faces <b>172</b> &amp; <b>174</b> of the intermediate substrate <b>170</b> (see <figref idref="f0013">Fig. 9A</figref>). Additionally, the intermediate substrate <b>170</b> has a plurality of wire contacts <b>186</b> processed onto its exit face <b>174.</b> The wire contacts <b>186</b> are arranged in a wire contact pattern (not shown) corresponding to the I/O contact pattern <b>152</b> (see <figref idref="f0012">Fig. 8C</figref>) on the readout surface <b>134</b> of the ASIC readout/processing substrate <b>130.</b> The wire contacts <b>186</b> are in electrical communication with wire bonding pads <b>200</b> mounted or processed onto either or both of the faces <b>172</b> &amp; <b>174</b> of the intermediate substrate <b>170.</b>

In the preferred embodiment shown in <figref idref="f0015">Fig. 10</figref>, the wire contacts <b>186</b> (and the via passage skirt <b>184</b>) are recessed into the exit face <b>174</b> of the intermediate substrate <b>170,</b> but alternatively, the wire contacts <b>186</b> (and the via passage skirt <b>184</b>) could be on the exit face <b>174.</b> The wire contacts <b>186</b> each are in electrical communication with a separate or a common wire bonding pad <b>200</b> by means of a circuit path <b>188.</b> In the embodiment exemplified in <figref idref="f0015">Fig. 10</figref>, the circuit paths <b>188</b> are isolated from either face <b>172</b> &amp; <b>174</b> of the intermediate substrate <b>170,</b> and run within the layers of the intermediate substrate material (e.g., PC board). The circuit paths <b>188</b> do not have to all run at the same level within the layers of the intermediate substrate material, and can communicate with wire bonding pads <b>200</b> on either face of the intermediate substrate <b>130.</b> This feature can be particularly beneficial when a conductive adhesive film is used to bond a semiconductor substrate to the intermediate substrate <b>170.</b>

Electrically conductive bonds <b>220</b> discretely connect each conductive contact and with its corresponding conductive contact, i.e.: each pixel contact <b>102</b> in the pixel pattern <b>104</b> to the first end <b>180</b> of the corresponding conductive via passage <b>178</b> on the entry face <b>172</b> of the intermediate substrate <b>170,</b> and each transmission contact <b>136</b> in the transmission contact pattern <b>150</b> is discretely connected to the second end <b>182</b> of the corresponding conductive via passage <b>178</b> of the exit face <b>174</b> of the intermediate substrate <b>170.</b> Similarly, each I/O contact <b>140</b> in the I/O contact pattern <b>152</b> is conductively connected with the corresponding wire contact <b>186</b> on the intermediate substrate <b>170.</b> In the preferred embodiment shown in <figref idref="f0005">Fig. 5</figref>, the electrically conductive bonds <b>220</b> comprise solder bump-bonds of any of a variety of solder alloys known in the art and selectable by the ordinary skilled artisan, including bump technologies such as stud bumps made of Au or Ag.

Alternatively, as shown in <figref idref="f0006">Fig. 6A</figref>, the electrically conductive bonds may comprise discrete conductive adhesive bonds <b>224.</b> In this case, an appropriate conductive adhesive is discretely applied between the conductive contacts to be bonded to provide electrical continuity between the conductive contacts. A combination of conductive adhesive bonds <b>224</b> and solder bump-bonds <b>220</b> may be utilized to mount the semiconductor substrates <b>90</b> &amp; <b>130</b> to the intermediate substrate in a SVCASIC imaging device <b>80,</b> exemplified in <figref idref="f0006">Fig. 6A</figref>, where conductive adhesive bonds <b>224</b> join pixel contacts <b>102</b> to the via passages <b>178</b> of the intermediate substrate <b>170,</b> and solder bump-bonds <b>220</b> join the pixel circuit contacts <b>140</b> to the via passages <b>178.</b>

Also, anisotropically conductive adhesive films may be used to form conductive bonds <b>226</b> between the conductive contacts. The use of anisotropically conductive adhesives for forming conductive bonds is known in the art, as noted above. <figref idref="f0007">Fig. 6B</figref> exemplifies an embodiment of the present SVCASIC <b>80</b> practiced utilizing an anisotropically conductive film bond <b>226</b> to provide conductive bonds between pixel contacts on the pixel face <b>94</b> of the detector substrate <b>90,</b> and the corresponding first ends <b>180</b> of the via passages <b>178</b> on the entry face <b>172</b> of the intermediate substrate <b>170.</b> The anisotropically conductive film bond <b>226</b> also acts to mount the semiconductor detector substrate <b>90</b> to the intermediate substrate <b>170.</b> Of course, conductive adhesive bump-bonds <b>224</b> and/or anisotropically conductive film bond <b>226</b> may be practiced between the either face of the intermediate substrate <b>130</b> and its corresponding semiconductor substrate surface.

In another preferred embodiment shown in <figref idref="f0016">Fig. 11</figref>, the present SVCASIC imaging device <b>80a</b> comprising an array of a plurality of semiconductor detector substrates <b>90a</b> and a corresponding array of a plurality of semiconductor ASIC readout substrates <b>130a</b> which are separated by and bound to a single intermediate substrate <b>170</b> in a laminate-like configuration. Also see <figref idref="f0005">Fig. 5B</figref>. In the embodiment exemplified, the array of detector substrates <b>90a</b> and the array of ASIC readout substrates <b>130a</b> are mounted (bonded) to a single intermediate substrate <b>130</b> using an anisotropically conductive film <b>226.</b> However, other means of appropriately bonding the semiconductor substrates <b>90a</b> &amp; <b>130a</b> to the single intermediate substrate <b>130</b> are known to and practicable in the present invention by one of ordinary skill in the art, including such bonding means detailed above.

A method of producing a SVCASIC radiation energy imaging device <b>80/80a</b> of the present invention is discernable to and practicable by one of ordinary skill in the art in view of the disclosure and figures herein. Generally, an intermediate substrate <b>170</b> and semiconductor readout substrate(s) <b>130/130a</b> and detector substrate(s) <b>90/90a</b> as described herein are provided. Conductive bonding means as also described herein are applied between corresponding conductive contacts on the substrates <b>90, 130</b> &amp; <b>170,</b> under proper conditions of temperature and pressure are caused to form conductive bonds between the corresponding conductive contacts, and to bond the substrates together in a laminate-like configuration to produce a SVCASIC radiation energy imaging device <b>80/80a</b> of the present invention

Advantages of the SVCASIC mosaic imaging device of this embodiment include: an imaging device having an enlarged, continuous imaging area without certain limitations of the tiling techniques described in the above prior art; the assembled SVCASIC mosaic imaging device is substantially planar (flat) and can be utilized like a "flat panel;" and detector substrates are abutted in both x and y directions minimizing imaging dead area; and the via passages in the intermediate substrate can serve as a "self aligning" feature for mounting the semiconductor substrates to the intermediate substrate.

While the above description contains many specifics, these should not be construed as limitations on the scope of the invention, but rather as exemplifications of one or another preferred embodiment thereof. Many other variations are possible, which would be obvious to one skilled in the art. Accordingly, the scope of the invention should be determined by the scope of the appended claims and not just by the embodiments.