TDMA radio terminal capable of adjusting transmit timing by using measured delay time

BACKGROUND OF THE INVENTION

1. Field of the Invention

0001The invention generally relates to a radio terminal for use in a TDMA (time-division multiple access) communication system and more particularly to a radio terminal with a function of fine adjusting the transmit timing by compensating for the internal delay time.

2. Description of the Prior Art

0002In a TDMA communication system, a reference or base station communicates with a plurality of (N) secondary or mobile stations (i.e., radio terminals) once in a time period called a frame. Each frame comprises N time slots assigned to respective radio terminals. In response to a reception of a down link signal to each of the radio terminals, the radio terminal has to synchronize a transmit signal therefrom so that the transmit signal is received by the reference station in a time slot (Ts) assigned to the radio terminal as shown in FIG. 1.

0003Specifically, in FIG. 1, it is assumed that if the reference station transmits a down link signal (hereinafter, referred to as a "DL signal") in a time slot assigned to a specific radio station, the DL signal takes D/2 (sec) to reach the antenna of the radio station and further takes α (sec) to go through the receiver portion of the radio terminal. Here, D/2 is a propagation delay time between the reference station and the radio station and α is an internal delay time caused by components of the receiver portion of the radio station. It is also assumed that an up link (UL) signal transmitted from the radio station takes β + D/2 (sec) to reach the reference station, where β is an internal delay time caused by components of the transmitter portion of the radio station. A TDMA method requires each of the radio terminals served by a reference station to adjust the transmission wait time T (sec) so as to satisfy the following equation: <maths id="math0001"><math display="block"><mi>Tf</mi><mo mathvariant="normal">=</mo><mi mathvariant="normal">T</mi><mo mathvariant="normal">+</mo><mi mathvariant="normal">D</mi><mo mathvariant="normal">+</mo><mtable /><mi>α</mi><mo mathvariant="italic">+</mo><mi mathvariant="italic">β</mi><mo mathvariant="normal">,</mo></math><img file="EP1515458B1_D0001.tif" /></maths> where Tf is a frame period or an interval between time slots assigned to each radio station and T is a time from the recognition of a DL signal to the beginning of a transmission operation or a transmission wait time. In other words, each radio station has to start a transmit operation T (=Tf - D - α + β)) sec after recognizing a DL signal.

0004The present invention relates to a method and apparatus for correcting the transmission timing by using the total internal delay time (α + β) in a radio terminal used in a TDMA communication system and to a radio terminal incorporating such a method and apparatus.

0005European Patent Publication EP-A-0 690 593 describes a transmitter for use in a TDMA/TDD system which utilises an unassigned time slot for performing a loop-back test.

0006U.S. Patent 5,363,373 issued November 8, 1994 discloses a digital mobile station using presettable timeslot counter for compensating for propagation delay time. The mobile station receives a TDM signal from a cell site and detects a sync, a timeslot assignment signal and a signal indicating the propagation delay time (which corresponds to D in FIG. 1). From an assigned timeslot, a time interval from a detected frame sync to the time of transmission of a burst signal from the mobile station (Tf in FIG. 1) is determined. A pulse count corresponding to a subtraction (Tf - D) of the propagation delay time from the determined time interval is preset to a presettable counter. The counter starts counting when a frame sync is detected from the received TDM signal and generates a timing pulse when it reaches the preset pulse count to cause a burst signal to be transmitted. However, the delay time within the mobile station (i.e., α + β in FIG. 1) is not considered in deciding the transmit timing.

0007U.S. Patent 4,346,470 issued August 24, 1982 discloses a method and apparatus for acquiring transmit synchronization at a secondary station with the periodic frame reference bursts from a reference station in a TDMA network. A propagation delay factor is first measured and then a propagation delay correction factor is measured by using the propagation delay factor in satellite communication. Since the internal delay time (α + β) is relatively shorter than the propagation delay time (D) in satellite communication, the internal delay time may be measured in a lower precision. The measurement of propagation delay factor or correction factor requires a transmission of burst. The synchronization scheme can not cope with changes with time in the characteristics of circuit elements constituting a radio terminal.

0008In some prior art radio terminals, the total internal delay time (α + β) is estimated or measured in a design or development stage and stored in a memory of each product or each manufactured radio terminal. The stored total internal delay time α + β is used for calculation of the transmit timing in usual operation.

0009However, in such a radio communication system as requires a vary high precision of the transmit timing, the dispersion of the characteristics of circuit elements constituting each radio terminal can cause the internal delay times α and β to significantly vary with each radio terminal.

0010It is therefore an object of the invention to provide a radio terminal with the precision of transmit timing raised by actually measuring the total internal delay time (α+β) caused by the receiver and transmitter portions and fine adjusting the transmit timing with the measured total internal delay time.

SUMMARY OF THE INVENTION

0011According to an aspect of the invention, this object is achieved by a radio terminal as defined in claim 1.

0012According to another aspect of the invention, the above object is achieved by a radio terminal as defined in claim 2.

0013Providing an on/off switch between the antenna and the duplexer permit the radio terminal to measure the internal delay time without radiating radio waves.

0014The measurements of internal delay time regularly made permits the radio terminal to compensate for changes with time in the internal delay time due to the characteristics of circuit elements constituting the radio terminal.

BRIEF DESCRIPTION OF THE DRAWING

0015Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawing, in which: <ul id="ul0001" list-style="none" compact="compact"><li>FIG. 1 is a diagram showing the way a burst is transmitted in a TDMA communication system;</li><li>FIG. 2 is a schematic block diagram showing an arrangement of a part of a radio terminal with a transmit timing fine adjusting capability in accordance with a first illustrative embodiment of the invention;</li><li>FIG. 3 is a schematic diagram showing an exemplary arrangement of the receiver portion 105 of FIG. 2;</li><li>FIG. 4 is a schematic diagram showing an exemplary arrangement of the transmitter portion 107 of FIG. 2;</li><li>FIG. 5 is a schematic diagram showing an exemplary arrangement of the internal delay counter circuit 110 of FIG. 2;</li><li>FIGs. 6 and 7 are diagrams showing how the total internal delay time is measured and two examples of reference signals;</li><li>FIG. 8 is a partial block diagram showing a clock circuit of the radio terminal 100;</li><li>FIG. 9 is a partial block diagram showing an antenna circuit of the radio terminal 100;</li><li>FIG. 10 is a schematic block diagram showing an arrangement of a part of a radio terminal with a transmit timing fine adjusting capability in accordance with a second illustrative embodiment of the invention;</li><li>FIG. 11 is a schematic diagram showing an exemplary arrangement of the internal delay counter circuit 110a of FIG. 10;</li><li>FIG. 12 is a flowchart showing an operation executed by the not-shown CPU of the controller 240 under the control of a transmission wait time count setting subroutine;</li><li>FIG. 13 is a block diagram showing an arrangement of another embodiment of an internal delay counter circuit which is usable in place of the internal delay counter circuit 110 or 110a;</li><li>FIG. 14 is a schematic block diagram showing an arrangement of a part of a radio terminal with a transmit timing fine adjusting capability in accordance with a modification of the second illustrative embodiment of the invention;</li><li>FIG. 15 is a schematic block diagram showing an arrangement of a part of a radio terminal with a transmit timing fine adjusting capability in accordance with a third illustrative embodiment of the invention;</li><li>FIG. 16 is a block diagram showing an arrangement of an illustrative embodiment of an internal delay counter circuit which uses the transmit data generator 106 output as a reference signal;</li><li>FIG. 17 is a diagram showing an exemplary arrangement of a system 500 for measuring the total internal delay time of a radio terminal at the production site in accordance with principles of the invention;</li><li>FIG. 18 is a diagram showing an exemplary arrangement of another system 500 for measuring the total internal delay time of a radio terminal at the production site in accordance with principles of the invention;</li><li>Throughout the drawing, the same elements when shown in more than one figure are designated by the same reference numerals.</li></ul>

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment I

0016FIG. 2 shows an arrangement of a part of a radio terminal 100 with a transmit timing fine adjusting capability in accordance with a first illustrative embodiment of the invention. The radio terminal 100 at least comprises: <ul id="ul0002" list-style="none" compact="compact"><li>an antenna 101;</li><li>a duplexer 102 for enabling the antenna 101 to be used in common for both transmission and reception;</li><li>a clock generator 103 comprising, for example, a crystal oscillator for generating a clock signal;</li><li>a synthesizer 104 comprising PLL (phase-locked loop) synthesizers for transmission and reception for generating respective local oscillation signals by using the clock signal;</li><li>a receiver portion 105 for demodulating an RF (radio frequency) signal from a reception output terminal 102a of the duplexer 102 by using the local oscillation signal for reception into a demodulated signal;</li><li>a not-shown TDMA decoder for extracting data from a time slot in the demodulated signal which slot is assigned to the radio terminal;</li><li>a transmit data generator 106 for inserting transmission data into a time slot assigned to the radio terminal in response to a trigger signal; and a transmitter portion 107 for modulating the transmission data into a modulated signal and frequency converting the modulated signal with the local oscillation signal from the synthesizer 104 for feeding the duplexer 102 through a transmission input terminal 102b thereof. The radio terminal 100 further comprises: <ul id="ul0003" list-style="none" compact="compact"><li>a power supply 139 which is turned on and off by a power switch 137 and which supplies one or more voltage and a power-on (Pon) pulse signal in response to a turning on of the power switch 137;</li><li>an internal delay counter 110 for measuring the total internal delay time (α + β) by transmitting a reference signal, measuring the time the reference signal takes to return through the transmitter portion 107, the duplexer 102 and the receiver portion;</li><li>a 1-of-2 selector 120 for usually supplying the transmitter portion 107 with a transmit data generator 106 output and for supplying with the reference signal from the internal delay counter 110 only for a preset short time in response to the Pon pulse signal from the power supply 139;</li><li>a time slot timing controller 130 comprising a Nt register 131 for storing a pulse count Nt corresponding to the time Tf - D, a Nd register 132 for storing a pulse count corresponding to the total internal delay time α + β, and a not-shown counter for putting out the trigger signal to the transmit data generator 106 when it counts up to Nt - Nd after receiving the demodulated signal from the receiver portion 105; and</li><li>a Nd register setter 135 for transferring the pulse count Nd from the internal delay counter circuit 110 to the Nd register 132 of the time slot timing controller 135 in response to a stop signal from the internal delay counter circuit 110.</li></ul></li></ul>

0017It is noted that the time slot timing controller 130 also has a function of controlling the time slot reception timing. In other words, the transmit data generator 106 and the time slot timing controller 130 constitutes a TDMA codec.

0018It is assumed that the duplexer 102 is guaranteed the isolation of more than several tens dB between the reception output terminal 102a and the transmission input terminal 102b thereof.

0019The receiver portion 105 comprises, for example, an amplifier (AMP) 11 for amplifying the received RF signal, a frequency converter 12 for frequency converting the amplified RF signal with the local oscillation signal from the synthesizer 104 into a base band signal, and a base band demodulator 13 for demodulating the base band signal into a demodulated signal as shown in FIG. 3. The base band demodulator 13 comprises, for example, an analog-to-digital converter 14 for converting the (analog) base band signal into a digital signal, and a digital demodulator 15 for demodulating the digital signal into the demodulated signal.

0020The transmitter portion 107 comprises, for example, a base band modulator 16 for orthogonally modulating with the signal from the selector 120, a frequency converter 17 for frequency converting the orthogonally modulated signal by using the local oscillation signal for transmission into an RF signal, and an amplifier (AMP) 18 for amplifying and supplying the RF signal to the duplexer transmission input terminal 102b.

0021FIG. 5 is a schematic diagram showing an exemplary arrangement of the internal delay counter circuit 110 of FIG. 2. In FIG. 5, the circuit 110 comprises: <ul id="ul0004" list-style="none" compact="compact"><li>a reference signal generator 111 for generating a predetermined reference signal in response to the Pon signal from the power supply 139;</li><li>a signal detector 112 for generating a start signal when the level of the predetermined reference signal crosses a first threshold value;</li><li>a signal detector 113 for generating a stop signal when the level of the demodulated signal from the receiver portion 105 crosses a second threshold value; and</li><li>a counter 114 for starting a count operation on the clock signal from the clock 103 in response to the start signal from the signal detector 112 and stopping the count operation in response to the stop signal from the signal detector 113.</li></ul>

0022FIG. 6 is a diagram showing how the internal delay time (α + β) is measured in the internal delay counter circuit 110. It is assumed that the predetermined reference signal is a one like an impulse as shown in FIG. 6. In this specific example, the signal detectors 112 and 113 provide output signals when the input signals exceed the first and second threshold values, respectively. For example, the signal detectors 112 and 113 each comprise a comparator which makes its output signal "high" when the input signal becomes larger than the threshold value. The first threshold value for the signal detector 112 is set, for example, a half of the amplitude of the reference signal. The second threshold value for the signal detector 113 is set, for example, a half of the amplitude of the demodulated signal. The counter 114 counts the clock pulses from the clock 103 from the time of reception of a start signal from the signal detector 112 to the time of reception of a stop signal from the signal detector 113. If the number of the counted clock pulses is Nd and the time period between adjacent clock pulses is Tc, then the time between the start signal and the stop signal is equal to Nd × Tc, i.e., α+β =Nd×Tc. The counted value Nd of the counter 114 is stored in RAM 141 of the controller 140.

0023The operation of the radio terminal 100 is described in the following. If the power switch 137 is turned on causing the power supply 139 to assert the Pon signal, then the reference signal generator 111 responsively puts out a reference signal of an impulse shape, which is supplied to a b-terminal of the selector 120 and the signal detector 112 input.

0024Since the selector is so arranged as to connect the common terminal "c" with the b-terminal for a predetermined short time in response to a Pon pulse, the reference signal from the reference signal generator 111 is supplied to the transmitter portion 107 as a signal to be modulated. The reference signal is modulated and frequency converted into a transmission band signal, which is supplied to the antenna 101 via duplexer 102. Though the transmission input terminal 102b and the reception output terminal 102a are isolated by several tens dB, an attenuated transmission band signal is captured as an interference signal by a receiver portion 105 system. The interference signal includes the transmission band component and a plurality of spurious components caused by higher order distortions generated in the synthesizer 104. In response to the turning on of the radio station 100, the receiver portion 105 selects a channel identical to the transmission band to provide a demodulated signal, which has been subjected to a group delay due to various filters and accordingly appears the total internal delay time (α + β) after the generation of the reference signal.

0025On the other hand, the signal detector 112 has put out a start signal to the counter 114 on detecting, e.g., a rising edge of the reference signal from the reference signal generator 111. In response to the start signal, the counter 114 has started counting the clock pulses from the clock 103. If a rising edge of the demodulated signal from the receiver portion 105 is detected by the signal detector 113, the detector 113 puts out a stop signal, causing the counter 114 to stop counting. In this way, the counter 114 counts the clock pulses for the total internal delay time, i.e., α + β sec. In other words, the number of the clock pulse counted for α + β sec is Nd.

0026In response to the stop signal, the Nd register setter 135 transfers the count value Nd from the counter 114 to the Nd register 132 of the time slot timing controller 130. It is assumed that the controller 130 stores in the Nt register 131 a pulse count Nt equivalent to the time period from the reception, at the antenna 101, of a DL signal to the transmission, at the antenna 101, of an UL signal, i.e., the transmit timing after the reception at the antenna 101, (Tf - D). Then, the time slot timing controller 130 responsively sets the difference of the Nd register 132 contents from the Nt register 131, i.e., Nt - Nd to a not-shown register of the not-shown counter of the controller 130 as a preset value for the not-shown counter. Thus, a transmission wait time corrected with an actually measured total internal delay time is thereafter used for the transmit timing control.

0027In actual communication operation, if a demodulated DL signal of a time slot assigned to the radio terminal 100 is supplied to the time slot timing controller 130. The controller 130 responsively puts out a trigger signal after counting Nt - Nd, i.e., Tf - D - (α + β) sec after the reception of the demodulated DL signal.

0028According to the first embodiment of the invention, the transmit timing is controlled with a high precision without suffering any influence of variety in the total internal delay times of radio terminals.

Modifications

0029Though the above-described embodiment has used signal detectors 112 and 113 of a positive logic output type, the signal detectors each may be a combination of a negative-logic output signal detector and an inverter.

0030The demodulator 15 may be a demodulator of a type which also provides a demodulator output timing signal. In this case, instead of the demodulator output, the demodulator output timing signal is supplied to the signal detector 113.

0031In measuring the total internal delay time, the receiver portion 105 has selected a channel identical to the transmission band. However, the receiver portion 105 may select a channel of a band identical to one of the captured spurious components.

0032Though the reference signal is a pulse-like signal, the reference may be a signal with a predetermined duration as shown in FIG. 7.

0033Though the base band demodulator 13 has performed a digital demodulation, the demodulator 13 may perform an analog demodulation.

0034Instead of the clock signal, a multiplied version of the clock signal may be supplied to the internal delay counter circuit 110 and the time slot timing controller 130 by providing a frequency multiplier 136 as shown in FIG. 8. By doing this, the precision of the measurement of the total internal delay time can be raised.

0035The radio terminal 100 may further comprises an on/off switch 122 inserted between the antenna 101 and the duplexer 102. The switch 122 is controlled by the same control signal as supplied to the 1-of-2 switch 120 as shown in FIG. 9. The switch is so arranged as to be closed while the common terminal 120c is connected with terminal 120a and to be opened while the common terminal 120c is connected with terminal 120b. Doing this can prevent undesirable radio waves from being transmitted outside.

Embodiment II

0036FIG. 10 is a schematic block diagram showing an arrangement of a part of a radio terminal with a transmit timing fine adjusting capability in accordance with a second illustrative embodiment of the invention. The radio terminal 200 of FIG. 10 is identical to that of FIG. 2 except that the time slot timing controller 130 and the Nd register setter 135 has been replaced with a combination of a timing counter 230 and a controller 240 and a TDMA decoder 108 is inserted after the receiver portion 105. Also, the internal delay counter circuit 110 has been replaced with 110a.

0037The TDMA decoder 108 extracts data in a time slot in the demodulated signal from the receiver portion 105 which slot is assigned to the radio terminal 200.

0038The timing counter 230 has a register 231 for storing a preset number. The counter 230 is started by the TDMA decoder 108 output and puts out the above-described trigger signal to the transmit data generator 106 when it counts up to the preset number.

0039The controller 140 is not dedicated to the control of transmit timing adjustment but also used for the control of the whole terminal. The controller 140 preferably comprises a not-shown CPU (central processing unit), a not-shown ROM (read only memory), and RAM (random access memory) 241. The RAM stores above-described data Tf, D, α + β, Nt, Nd and Nt - Nd.

0040However, it should be noted that the output signal from the TDMA decoder 108 is used as the trigger signal to the timing counter 230. Therefore, the pulse count corresponding to the total internal delay time, Nd, equals Nd1 + Nd2, where Nd1 is a pulse count of the counter 114, and Nd2 is a pulse count corresponding to the delay time due to the TDMA decoder 108. For this reason, the delay times Nd1 and Nd2 are actually stored in the RAM 241 instead of Nd. The controller 240 controls the internal delay counter 110 and the selector 120 to measure the internal delay time count Nd1. The controller 240 reads the count value Nd1 from the counter 114 and sets the transmit timing count (Nt - Nd1 - Nd2) which corresponds to the transmission wait time T to the register 231 of the timing counter 230 as the preset number.

0041It is also noted that the transmit timing has to be corrected also with the propagation delay time D as (Tf - D) because the propagation delay time D due to the transmission path is not negligible in case of a satellite communication system. However, if the value of the propagation delay time D is sufficiently small as compared with the total internal delay time as is the case with a terrestrial communication system, there is no need of a correction with the propagation delay time D; accordingly the RAM 240 need not store the value D; and the pulse count Nt may be equal to Tf × Tc instead of (Tf - D) ×Tc (Tc is a period of the clock signal from the clock 103).

0042In the internal delay counter circuit 110a of FIG. 11, the stop signal is supplied only to the counter 114. The reference signal generator 111 is started by the measurement start (MS) signal from the controller 240.

0043The selector 120 is controlled by the measurement mode (MM) signal from the controller 240 instead the Pon signal.

0044As seen from the above description, the measurement of the delay time is controlled by the signals from the controller 240 instead of the Pon signal generated in response to a power on. For this reason, the measurement may be made not only at a power-on time but also at any desired time according to a program stored in the not-shown ROM.

0045FIG. 12 is a flowchart showing an operation executed by the not-shown CPU of the controller 240 under the control of a transmission wait time count setting subroutine 300. If the program calls the subroutine 300, then the CPU (not shown) first sets the MM signal to logical 1 to connect the common terminal 120c with the terminal 120b in the switch 120 in step 302. In step 304, the CPU outputs a pulse on the MS line to activate the reference signal generator 111.

0046This causes the generator 111 to generate a reference signal, which thereafter travels through the switch terminals 120b and c, the transmitter portion 107, the receiver portion 105 to become a demodulated signal as described in connection with the first embodiment. The demodulated signal causes the counter 114 to stop and hold a pulse count Nd1 corresponding to the internal delay time due to the transmitter portion 107 and the receiver portion 105. In order to ensure the completion of this process, the CPU waits for a predetermined period of time not shorter than the possible maximum total internal delay time in step 306.

0047In step 308, the CPU sets the MM signal to logical 0 to connect the common terminal 120c with the terminal 120a for normal communication operation. In step 310, the CPU reads the value Nd1 of the counter 114. In step 312, the CPU reads the pulse count Nt and Nd2 from the RAM 241 and stores Nt - Nd1 - Nd2 in the register 231 of the timing counter 230. Then the CPU returns to the program.

0048FIG. 13 is a block diagram showing an arrangement of another embodiment of an internal delay counter circuit which is usable in place of the internal delay counter circuit 110 or 110a. In FIG. 13, it is assumed that a reference signal generated by the reference signal generator (RSG) 111 is a pulse of a predetermined duration as shown in FIG. 7. Assuming that the signal detectors 112 and 113 are, for example, comparators of, say, a rising edge-sensitive type, then signal detectors 212 and 213 are, for example, comparators of a falling edge-sensitive type. The threshold value of the signal detectors 112 and 212 to which the reference signal is supplied is set to, say, a half of the amplitude of the reference signal. Similarly, the threshold value of the signal detectors 113 and 213 to which the demodulated signal from the receiver portion 105 is supplied is set to, say, a half of the amplitude of the demodulated signal.

0049As seen from the just above paragraph and FIG. 13, a first part comprising the elements 111 through 113 and a counter 114-1 constitute an internal delay counter circuit like 110 or 110a. The first part measures the time difference between the rising edges of the reference signal and the returned modulated signal, Td1, as shown in FIG. 7.

0050Similarly, a second part comprising the reference signal generator 111, the falling edge-sensitive signal detectors 212 and 213, and a counter through 113 and a counter 114-2 constitute another internal delay counter circuit like 110 or 110a. The second part measures the time difference between the falling edges of the reference signal and the returned modulated signal, Td2.

0051The value of the counter 114-1, Nd1, and the value of the counter 114-2, Nd2, are supplied to the two input terminals of an average calculator (CAL.) 215, where Nd1 = Td1/Tc and Nd2 = Td2/Tc (Tc is a period of the clock signal). The average calculator 215 calculates an arithmetic average of the total internal delay time counts Nd1 and Nd2 measured by the rising edges and the falling edges, respectively. That is, the calculator 215 finds (Nd1 + Nd2)/2 as the total internal delay time Nd.

0052Thus, the internal delay counter circuit 110b enables the measurement of the total internal delay time without errors due to changes in the threshold values.

Modification

0053In the first and second illustrative embodiments, the output signal from the receiver portion 105 has been used as the input signal to the signal detector 113 of the internal delay counter circuit 110a. However, the output signal from the frequency converter 12 may be used as the input signal to the signal detector 113 as shown in FIG. 14 for example.

0054In this case, the base band demodulator 13 is preferably a digital demodulator because the delay times which occurs in digital demodulators hardly vary and accordingly are easy to estimate before hand. Assuming that the pulse count of the counter 114 or the average calculator 215 is Nd1 and the delay times due to the base band demodulator 13 and the TDMA decoder 108 are Nd2 and Nd3, respectively, then the controller 240 stores Nt - Nd1 - Nd2 - Nd3 in the register 231 of the timing counter 230.

Embodiment III

0055FIG. 15 is a schematic block diagram showing an arrangement of a part of a radio terminal 400 with a transmit timing fine adjusting capability in accordance with a third illustrative embodiment of the invention. The radio terminal 400 of FIG. 15 is identical to that of FIG. 10 except that an internal delay counter 110c has been added in FIG. 400. It is assumed that the radio terminal 400 does not perform the up link transmission and the down link reception at the same time, i.e., the radio terminal is not full duplex.

0056FIG. 16 is a block diagram showing an arrangement of an illustrative embodiment of an internal delay counter circuit 110c which uses the transmit data generator 106 output as a reference signal. The internal delay counter circuit 110c of FIG. 16 is identical to that of FIG. 11 except that the reference signal generator 111 has been replaced with an on/off switch 411. A switch signal input 411a is connected with the transmit data generator 106 output. A switch signal output 411b is connected with the signal detector 112. A switch control terminal 411c is connected with an MS2 line from the controller 240. The switch 411 is so arranged as to pass the input pulses only when the MS2 signal from the controller is logical 1.

0057In response to a turning on of the radio terminal 400, the controller 240 makes a measurement of the internal delay time by using the internal delay counter circuit 110a. Since the operation of the measurement is identical to that of FIG. 10, the description of the measuring operation is omitted.

(Though the MS signal has been renamed MS1.)

0058Thereafter, the controller 240 regularly makes a measurement of the internal delay time by using the internal delay counter circuit 110c. In this measurement, the counter 114 is started by a series of data which is supplied from the generator 106 while the MS2 signal from the controller 240 is logical 1. The series of data also travels through the selector 120 and the transmitted portion 107 to reach the duplexer 102, where an attenuated transmission band signal is captured by a reception system. Since the control signals which are supplied from the controller 240 to the synthesizer 104 and the receiver portion 105 has caused the receiver portion 105 to select a channel identical to the transmission band by then, the captured signal is selected and demodulated into a demodulated signal, which causes the counter 114 to stop. Thereafter, the pulse count Nt - Nd1- Nd2 is set to the register 231 of the timing controller 230. Thus the register 231 value is updated.

0059According to the embodiment of the invention, the transmission wait time is regularly updated, which eliminates the influence of changes in the ambient temperature. The regular measurement of the internal relay time by the internal delay counter circuit 110c is performed by using up link transmissions, which prevents undesirable radio waves from radiating.

Embodiment IV

0060FIG. 17 is a diagram showing an exemplary arrangement of a system for measuring the total internal delay time of a radio terminal at the production site in accordance with principles of the invention. The radio terminal may be any of the above described ones 100, 200, 200a and 400. The measurement is performed before the antenna 101 is attached to the main body of the radio terminal. The antenna-side terminal of the duplexer 102 is connected to the common terminal of a 1-of-2 switch 420, 420c. The switch terminal 420a is connected with an antenna 101, and the switch terminal 420b is connected with an impedance matching element 430 which is impedance matched to the antenna 101. When the measurement is performed, the switch common terminal 420c is connected with the terminal 420b, i.e., the impedance matching element 430. The operation of the measurement is identical to a case of the measurement on a radio terminal alone. The resultant pulse count Nd is stored in the register 132 in case of a radio terminal 100. Similarly, the resultant value Nt - Nd is stored in the register 231 of the timing counter 230 incase of any of radio terminals 200, 200a and 400.

0061According to the embodiment, the measurement of the internal relay time can be performed without radiating undesirable radio waves.

0062FIG. 18 shows an exemplary arrangement of another system 500 for measuring the total internal delay time of a radio terminal at the production site in accordance with the principles of the invention. The system 500 comprises one of above-described radio terminals 100, 200, 200a and 400 which has not had its antenna 101 attached thereto, a 1-of-2 switch 420, an antenna 101 and a frequency converter 450. The switch common terminal 420c is detachably and electrically connected with the antenna-side terminal of the duplexer 102.

0063It is noted that the internal delay counter circuit 110a is not incorporated in the radio terminal but is detachably and electrically connected with the radio terminal, in which the internal delay counter circuit 110a is electrically connected in the same manner as in case where it is incorporated in the radio terminal. The frequency converter 450 is for converting the transmission band signal output from the duplexer 102 into a predetermined channel within a reception band and attenuating the frequency-converted transmission band signal by a predetermined amplitude and feeding the duplexer 102 with the attenuated transmission band signal. The predetermined attenuation amplitude is such that the attenuated transmission band signal is not distorted by the amplifier (AMP) 11 of the receiver portion 105 saturating and has a sufficient level to be demodulated in the receiver portion 105.

0064In measuring the total internal delay time, the transmitted reference signal is frequency converted and attenuated by the frequency converter to return through the receiver portion 105. The other operation is the same as that of the above-describe embodiments.

0065According to the system, the measurement of the internal relay time can be performed without radiating undesirable radio waves. Also, a radio terminal has no need of having the internal delay counter circuit 110a inside.

0066There may be a case where the delay (Dfc) due to the frequency converter 450 is not negligible. In such a case, a pulse count Δ N corresponding to the delay Dfc is subtracted from the pulse count of the counter Nd (Dfc = Tc × Δ N). In case of a radio terminal 100, the pulse count (Nd - Δ N) is stored in the register 132. In case of the other embodiments, the transmission wait time Nt - (Nd - Δ N) is stored in the register 231.

0067It is also noted that the frequency converter 450 has not necessarily to be used. Instead, the measurement may be done in the same way as in case of the first embodiment.

0068Many widely different embodiments of the present invention may be constructed without departing from the scope of the present claims. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

0069A TDMA radio terminal comprises a transmitter portion and a receiver portion. A reference signal is launched in the transmitter portion while tuning the receiver portion. At the same tine, an internal delay counter is started. The counter counts clock pulses till the reference signal returns through the receiver portion. Letting this pulse count be Nd, a transmission wait time is Nt - Nd. Nt is a transmit timing at the antenna. The Nd counting operation may be triggered by a power on or a signal from a controller. Method for determining the transmission wait time in the production site is also disclosed.