Digital filtering method

Translation of description of equivalent WO 03107533 A2

A method for digital filtering

The invention relates to a method for digital filtering of K input digital values ​​which i. Allg. representing neighboring values ​​of a one- or multi-dimensional digital signal, wherein the filter is non-linear and at baseline the R-largest value from the K input values ​​determined, wherein R and K are integers and K> R> 1. Such a filter is hereinafter referred to rank filter with R = 1 corresponds to the largest of the input values ​​and R = K corresponds to the lowest of the input values. A one-dimensional filter Rank is calculated at each time point m = L to R-largest value of K successive values ​​of an input signal x (n); for L = 1 there is a filter without decimation, ie a filter with decimation. without reducing the sampling rate, for L> 1 a multidimensional rank filter Similarly determines the R-largest value of K adjacent values ​​of a multi-dimensional signal. The R-largest input value corresponds to the course (KR) -kleinsten input value, so that the process synonymous includes determining an x-smallest input value, in which the R = Kx largest value wanted.

A special case of such a rank filter is a median filter. Under the median of an odd number K of input values ​​is defined as the average value, ie the (K + 1) / 2-smallest value, or what is the same, the (K + 1) / 2-largest value, i. Other , is different from the average value. For example, however, obtained for the five values ​​of 5, 3, 2, 79 and 1, the median 3, as the mean value of the eighteenth

Such digital filters are used to signal processing of obtained input values, for example. The processing of image data or distance measurement signals, particularly reflection signals reflected in a target area pulses, optical waves, preferably come into consideration in the infrared, radar waves or ultrasound waves. An implementation of such a non-linear filtering is only possible in the digital domain.

For the implementation of such filters algorithms are known, which are mostly based on sorting methods that are very computationally intensive, or histogram method, which have a high memory requirements, and i. Other. are more suitable for software than for hardware implementation.

The object of the invention is therefore to propose a novel method of digital filtering Rank, which is simple and particularly cost-effective manner. This object is achieved by the features of claim 1. Advantageous further developments are specified in the dependent claims.

The basic idea is for a use of a binary representation of the input values ​​in fixed-point format and the other a bit serial processing, with all the usual binary number representations can be used in fixed-point format, and only minor adjustments taking into account the peculiarities of the representation of numbers used are required. The claim 1 includes the filtering procedure taking into account all important binary representations of numbers in fixed-point format, and has a function of each present numerical representation corresponding step alternatives, but based on the same basic idea. A number of sub-claims points to thereby how the filter drain for certain number of representations of the input values ​​significantly simplified. In addition, advantageous further developments for technical hardware implementation of the digital filter z. B. in an FPGA or an ASIC are presented which allow a high processing speed, as is required for image processing or radar applications in motor vehicles. The invention is explained in detail with reference to exemplary embodiments and figures.

The figures show:

Fig 1 a). Amplitude or envelope of s (t) of the transmitted wave in the case of rectangular pulses

Fig 1 b). Amplitude or envelope E (t) of the received wave in the case of an object at the distance a, which results in a signal propagation time of .DELTA.t = 2a / c

Figure 1c):.. Disturbed received signal e (t), for example due to overreach or interference from another pulsed, working in the same frequency range system

Fig. 2a): sine wave which numerous high interfering pulses are superimposed in the discrete time domain; in the spectrum of the resulting signal of the spectral peak of the sinusoidal oscillation has disappeared in the noise generated by the noise pulses

Figure 2b). Output by two-stage median filtering with respective filter length K = 5, in which the sine wave almost completely reconstructed in the time domain again and clearly visible in the spectrum thus is

Figure 3 block diagram of a pulse Doppler radar system 4 simplified circuit diagram for explaining the principle of the Doppler method;

5, the signal-time diagrams for the diagram of Figure 4;

6, the transfer function of an ideal and a real optimum filter;

Figure 7 shows the circuit diagram of a first embodiment of a matched filter;

Figure 8 shows the circuit diagram of a second preferred embodiment of a matched filter; 9a algorithm to implement a median filter with a bit serial

Processing for binary data into unsigned binary

FIGURE 9b algorithm to implement a median filter with a bit serial

Processing for binary data in sign magnitude representation

9C algorithm for implementing a median filter with a bit serial processing for binary data in single or double-complement representation

10A, B, C respectively to the detail 9a, 9b, 9c

11, the transfer function of an ideal and a real Dezimationstiefpasses;

Figure 12, the impulse response h (n) of a sliding averaging unit and a

Signal flow diagram; Figure 13, an advantageous embodiment of a Dezimationstiefpasses. The method for digital filtering will be explained first with a simple example of a determination of the median of 5 input values. For this purpose the following five numbers in unsigned binary representation and the word length W are = 4 (4 binary digits) considered; it identifies bit 0 the höchststignifikante bit MSB (most significant bit) and bit 3 the niedersignifikanteste bit LSB (least significant bit):

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For the individual bits are starting with a most significant bit in descending bit significance (MSB) in succession to settle most significant bit (LSB) carried out the following steps:

- The bit each currently considered the average, ie 3- greatest bit value is seen on all 5 input values ​​to determine which one is, if seen at bit currently being watched all 5 input values ​​not less than 3 times the value 1 occurs, otherwise the R-largest bit value 0,

- Where the 3-bit value largest then represents the bit value for the currently viewed Bit of 3-greatest value and thus the output value, ie the median,

When bit values ​​of all subsequent, ie lower-order bits, one bit value of the input values ​​are considered and for those input values ​​at which the bit value of the currently considered bit does not correspond to the 3-bit value largest on the currently considered bit -.

The MSB (bit 0) of the median must be 1, since the majority of the five MSBs is equal to 1; four MSBs are 1 and the associated numbers a, b, c, and e thus greater than the number d with the MSB is 0, so that one of the numbers 1 with the MSB of the median has to be. The remaining bits 1 ... 3 of the median thus arise as the third largest of the bits 1 ... 3 shown values ​​of the four numbers with the MSB 1. Substituting in the number d with the MSB 0 bits 1 ... 3 by the minimum representable value 000 (see table below) and considers all five numbers, then the bits 1 ... 3 of the median result continues as the third largest of the values ​​represented by the bits 1 ... 3

- But all the numbers - and thus as the median of these values.

<img id="imgf000005_0002" he="40" wi="66" file="imgf000005_0002.tif" img-format="tif" img-content="table" orientation="portrait" inline="no" /> Thus, one has attributed the problem to the media form further five numbers, but with reduced by one word length 3 - these numbers are shown in the above, modified table (which is no longer under consideration MSB is crossed out). To determine the bit 1 of the median, is to examine again whether more zeros or ones occur when bit 1; Accordingly, the bit 1 of the median is equal to 0. One of the three figures b, d, and e with the bit 1 is equal to 0 must respect the bits 1 ... 3 represents the median, since the two numbers a and c equal to 1 bit 1 are larger. The remaining bits 2 ... 3 of the median thus arise as the third smallest of the values ​​of the three numbers b, d and e with the bit 1 is 0. represented by the bits 2 ... 3 Substituting in the numbers a and c with bit 1 = 1, bits 2 ... 3 by the maximum displayable value 11 (see table below) and considers all five numbers, then the bits 2 ... 3 of the median result continues as the third smallest of the bits 2 .. .3 values ​​shown - but now all the numbers - and thus as the median of these values.

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The media for the education to be considered word length has thus been further reduced by one - it is only the median shown above five numbers with word length 2 to form, which proceed analogous to the preceding steps. Since the bit 2 outweigh the ones, the bit 2 of the median results to 1. When the two numbers d and e with bit 2 is 0 bit 3 to be replaced by the minimum representable value 0 (see table below). If the number d would not be necessary that, since this bit was modified in a previous step.

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At this time, already 4 (a, c, d, c) modified the 5 input values ​​and thus not recognized as complying with the median, calculated as Median already recognized the value of b and the process could be already canceled. However, such a termination criterion is additional effort, so that it may be easier, the sequence of steps even for the subsequent bits, here the LSB carry. Since outweigh the zeros at bit 3 (LSB), the LSB gives the median to 0 (see table below). <img id="imgf000007_0001" he="40" wi="64" file="imgf000007_0001.tif" img-format="tif" img-content="table" orientation="portrait" inline="no" />

Thus the median is determined completely and correctly; the calculated value in 1010 is in line with the third largest number b of the output values.

The underlying algorithm for determining the median of K numbers will now be formulated for the case of unsigned binary representation in a general manner: The individual bits are starting from the MSB to the LSB up sequentially as follows to be processed. First is to investigate whether seen at the bit in b over all K numbers occur more ones or zeros; the more frequently occurring bit value represents the bit b of the median. For the figures, in which the bit b to the bit value less frequently occurring equivalent, are all subsequent, ie lower-order bits set equal to the bit b. For the other most commonly used binary representations only the importance of the first bit against the hitherto considered sign-less binary distinction; in the digit and two's complement is the first bit of the MSB further - but with different valency, wherein the sign-magnitude representation of the first bit is the sign bit (VZB), which is followed by the MSB of the sum. This results from the sequential processing of the bits only the first bit is a difference, while all subsequent bits are unchanged as described above to treat. The determination of the first bit of the median remains unchanged; it always corresponds to the bit value of more frequently occurring in the first bit of the K numbers. Only the modification of the numbers with the less frequently occurring first bit value is different; However, in the sign-magnitude representation regarding an interpretation with the median sign - depending on whether these figures do not lie above or below the median, always the representable with these bits minimum or maximum value for their subsequent bits to use.. In the case of the digit and two's all the subsequent bits are set to the inverse MSB value for the numbers with the less frequently occurring MSB value; in the case of sign-magnitude representation are to be set with the less frequently occurring VZB value all subsequent bits equal to 0 for the figures.

In the figures 9a, 9b, 9c, as well as 10A, 10b, 10c variants of the filter algorithm for the median calculation in the form of a one-dimensional filter are shown without decimation, wherein the 9a in connection with the construction of Figure 10A for input values ​​in unsigned binary notation show, while FIGURE 9b in conjunction with the modification 10B for a sign magnitude representation of the input values ​​and the 9C in connection with the Fig.10c

Modification of a single or double-complement representation of the input values ​​illustrate. To explain the following points are noted:

The input signal x (n) and the output signal consisting of the medians m (n) have the word length W, which is any value consists of W bits. The individual bits are with v numbe ert, starting at v = 0 for MSB (loose at sign binary in 9a, 10a and digit and twos in 9C, 10c) or the VZB (in of sign Amount shown in FIGURE 9b, 10b) and ending at V = W-1 for the LSB. The bit is denoted by x (n, v) and m (n, v) v x (n) or M (n).

The time at the level of input and output signals, ie word level is denoted by n, time at the bit level with μ = nW + v. The processing is bit-serially, ie one bit after another is processed, beginning with the MSB or VZB and ending at the LSB. The entire filter structure, ie memory and logic, ie clocked μ with the bit time.

The input values ​​required for calculating Media bitwise using K consecutive shift registers of length W; while K is the median filter length. The flag B0 (μ) denotes the processing of bit 0; it is 1 for v = 0, and otherwise 0. The flags

B1 (μ) and LSB (μ) denote the processing from the bit 1 and the LSB; they are defined in a similar way and can be generated by delay of B0 (μ) to a or W-1 clocks.

In the block "median of K bits" bitwise Media education takes place, ie the majority of zeros or ones among the K fed bits is determined.

In the k-th block "to be used bit value" (k = 0,1 K-1 is viewed from above), which is shown in detail respectively in Figures 10a, 10b and 10c, is used for one of the k-th bit value w ( nk, v) determined for the bit Media education: this is either the original value x (nk, v), ie the input value x (nk) bit looked v, or an appropriately modified value. Secondly, it is determined whether the next bit clock μ +1 the original value or an appropriately modified

is to use value, as indicated by the flag o_k(Μ) = 1 for the modification not been performed or o_k(Μ) = 0 in the modification already made. The following from the procedure described above is generally considered that after the first use of a modified value of this to be used also below n to the end of each time step. Subsequently, ie LSB (μ) = 1, the flag is reset, ie the unmodified input value is initially for the next baseline again considered.

The initialization of the memory (shift register and retarder) depends on the desired start-up behavior of the filter.

In following this new median filter structure its costs should be considered with respect at a hardware implementation (for example, on an ASIC or FPGA.).:

Bitwise Media Education, ie the determination of the majority of zeros or ones among the K bits fed, is the central block of this structure. One possible, particularly suitable for large filter lengths K strategy for realizing this block is based on the summation of the bit values ​​(0 or 1). If the bit sum&gt; = (K + 1) / 2, so the Bitmedian is 1, otherwise 0; the comparison there is a subtraction and subsequent testing of the

implement sign. The Bitsummenbildung can for example be realized in parallel stepped shape in which, step by step, the number of parallel Einzeladdierer off and their word length increases. thereby patting one hand the critical path and thus the processing time required to minimize and on the other hand hold the required word length and thus the expenditure as small as possible. The minimization of the critical path is particularly important when a high cycle life of the filter is required, since the bit-wise median formation in a recursive loop lies and therefore excretes pipelining. For small filter lengths there is the realization of the bitwise Media Education special, optimized for the used hardware solutions. Considered as an example, the filter length K = 5 and the implementation on a FPGA market, which has the basic building block look-up tables (LUTs) with four logical inputs and one output logic; three such LUTs for bitwise Media Education, it will then ben ötigt.

The K identical blocks "bit value to be used" need only two retarder (FIFOs) and a very simple logic (in the above example 2 LUTs).

The K shift register for storing the input values ​​need in many cases (especially when the word length W is relatively large) much more effort than the rest of the filter structure, which speaks for the efficiency of the filter logic. It should be noted that a storage independent of the structure of K input values ​​in each median filter is necessary.

The new median filter structure is scalable, if the bit median determination is realized via a summation; when changing the filter length K are only the number of shift registers used, the number of identical blocks "to be used bit value" and the number of bits be summed up and the bit sum adapt the value to be compared.

The new median filter structure has the property that the media education for each input value, ie each time step n, brand new touches, so unlike most existing structures does not rely on the results of previous time steps; For example, in sorting methods i. Allg. starting from the determined in the previous cycle sequence. Because of this characteristic, the new algorithm for median calculation is especially the case for filtering with decimation. Therefore only the shift register shall be supplied in a modified form in the filter structure. Thus, for a decimation by a factor of L = 2, the two uppermost shift register to be fed in parallel to two successive input values, and wherein the coupling of the shift register in each case one is skipped. In a decimation by the median filter length, ie L = K, the shift registers are no longer coupled, but are fed in parallel with K successive input values. By decimation of the maximum processable by the filter structure clock rate of the input signal x (n) can be increased by the decimation L.

For hardware implementations of the digital filter, the new algorithm for median calculation in many cases leads to a considerable reduction of the effort required; This is mainly dependent on the clock rate and the word length of the input signal, the degree of decimation, and the technology used or available logic.

So far, only the most commonly used binary fixed-point representations (sign-less binary, two's, Einerkomplement- or sign-magnitude representation) were considered. For other binary fixed-point representations, the new algorithm for Media Education can be formulated in an analogous manner and is also apparent from the following description for more general rank filters.

Instead under an odd number K of values ​​specifically to declare the (K + 1) / 2-largest value, can also be a value with a different rank, so in general the R-largest value, R = 1, 2, ... , K, consider and thereby allow for K is an arbitrary integer. The based on this filter is hereinafter referred to as a pipe filter; So it calculates each of K consecutive or neighboring values ​​of a one- or multi-dimensional Input signal to R-largest value and is used in a higher-level statistics (Ordered Statistic) z. B..

The above presented new filtering algorithm for Media Education can quite easily be extended to a more general rank formation leading to subsequent formulation; while all the binary representations of numbers in fixed-point format will be accepted, in which the amount of

Bit significances towards each halved from MSB to LSB, only the bit values ​​0 and 1 occur (ie, for example, not -1 as in the CSD code.) And optionally an additional sign bit (FTEs) are:

To determine the R-largest of K numbers, are the individual bits b, b = 0.1, ..., W-1, starting with the MSB or V ZB up to the LSB sequentially related. Magnitude descending bit significance as follows work off. First numbers is seen when viewed over all K bit b either the

to determine R-largest or smallest R-bit - the R-largest bit, if the value of the bit in question is positive or with value 1 is at the bit in a VZB for positive and value 0 for negative numbers, the R- smallest bit in the opposite case; at number representations with VZB is to be included the then-known sign of the R-largest number in the value of the VZB subsequent bits. The thus determined bit value (0 or 1), the bit b of the R-largest number. For the numbers which are related. Of b bits are different from the highest number R, for all subsequent bits b + 1 ... W -1 to always use the representable with these bits minimum or maximum value, depending on whether regarding the ... W-1 values ​​these numbers are represented by the bits b not above or below the R-largest number. at number representations with VZB is for to be included by the bits a ... W-1 values ​​in the case of a&gt; 0 shown the sign of R-largest number in the bit significances. "

This new algorithm for general rank formation itself has been implemented in a very simple realizable filter structure. In the event of a one-dimensional filter without decimation 9b + 10b, 9c + 10c median filter structure shown are produced compared to that in the 9a + 10a, only the following differences:

Instead the median of K bits is to determine the R-largest or R-smallest of K bits. There is also a block that determines whether it is to determine R-largest or the smallest R-bit, so there is a special case which. For this purpose, reference is made to the method steps in the claims describing the conditions and adjustment of the steps, respectively. The blocks "for use in bit value" must be modified accordingly. The output of

Filter is then the respective R-largest value.

The determination of the R-largest or smallest R-bits can be realized by means of a summation of the K bit values ​​again. Is the R-largest bit sought, then, for a bit sum&gt; = R, the R largest bit is 1, 0 otherwise; is the R-smallest bit sought, then, for a bit sum&gt; = K + 1-R, the R-smallest bit is 1, otherwise 0.

For digital signals in time or frequency domain, which have a useful level above the noise level only when individual discrete values, typically to determine a so-called noise threshold, over which the signal level is interpreted as a useful level and continue to be used; the noise threshold is therefore often referred to as detection threshold. To determine the noise threshold, a line filter can be used and determined in a preferred manner by means of the line filter method described above. In the example of a pulse Doppler radar can determine the spectral detection thresholds z. B. 128 formed by the 99- smallest value in the range of length.

The invention will be presented in its use in a radar system, in particular for a passenger motor vehicle. Modern motor vehicles are increasingly equipped with a radar-based distance control system, in which the distance, the speed and the relative angle of the preceding motor drive tool is determined.

Such a known radar system, for example, developed by the company Bosch FMCW (Frequency Modulated Continuous Wave), in which two physical quantities, the distance and relative speed of a moving or stationary body, be mapped to a physical quantity that frequency. For this purpose signals are continuously transmitted and received reflected from the moving body signals. From the frequency response of sent and received signal respectively from the frequency difference of these signals can be close to the size desired. A separation speed and distance is by evaluating a plurality of signals, called chirps, with different

Frequency slope possible. For a single target two chirps would suffice for multi-target situations at least three chirps are needed.

For operating such a radar system, especially an oscillator (VCO) with low phase noise is required, providing linear frequency ramps as possible, which readily is not possible and thus the RF portion of the radar system is very complicated. at

Traffic situations with many different goals, as is often the case with guard rails and in the downtown area, there are problems in the target detection and separation arise because all destinations are available in an antenna beam in each associated chirp spectrum. An accurate extraction of the different objectives is therefore not or not always satisfactory possible.

To circumvent these problems, the pulse Doppler method offers. In this method, a target is mapping each case one or more successive range gates. The received signal is sampled suitable. can then be closed at the exact distance from the amplitude ratio of the samples in consecutive distance gates.

However, the pulse Doppler system has a low signal-to-noise ratio (S / N) due to reduced average output power. Due to the broadband receiving path has this radar system at a higher Störbarkeit.

In the pulse Doppler method, a complex sample of the received signal to detect the sign of the velocity made. Radar system according to the pulse

Doppler method are characterized in that the speed and the distance represent direct measures. The RF portion can be realized much easier compared to the FMCW system mentioned, as there is a free-running oscillator (VCO) can be used with low demands on its phase and amplitude noise and no frequency ramps have to be generated. There are evaluated in such a radar system for a measurement cycle a plurality, for example, in 1024, sending pulses per reception antenna. Their spacing is then eg 2.5μs. The distance is also pseudo-noise-coded to avoid overshooting and interference.

When using a large number of transmission pulses a more accurate speed measurement and a high integration gain is possible and, moreover, the noise generated due to the pseudo noise code is small, so that a more optimal signal to noise ratio can be achieved.

In Fig.la) for a pulsed system, the amplitude or envelope of s (t) of the transmitted wave of the frequency f_s for the case of rectangular pulses. The time points at which to start the transmit pulses are hereinafter with t_P(N), the distance between two successive pulses is the pulse repetition time T_P (N).

If this wave is reflected with the propagation velocity c to an object in the distance a, the system receives after maturity At = 2a / c, the reflected and i. Other. evanescent wave s (t); in Figure 1 b), the amplitude or envelope E (t) is the received wave shown. Thus it can be concluded on the distance of the object from the running time .DELTA.t, as long as the duration .DELTA.t always smaller than the pulse repetition time T_PW(N); in another case arising ambiguity - one speaks of overreach. be captured by the wave object moves with respect. of the measuring system with the relative speed v, so the received from the system reflected wave shows a frequency shift by the Doppler frequency f_D = 2f_sv / c. Thus, from the Doppler frequency f_D are closed v the relative velocity.

In Fig.1c) the amplitude or envelope e (t) is the received wave exemplified for overreach or interference from another pulsed, working in the same frequency range system. The starting point for the suppression of overreach and interference is a pseudo noise

Coding of the pulse repetition T_PW(N), ie the pulse repetition time is not constant, but is designed a random process to variably. Received pulses which come from overreach or another pulsed system, then have to immediately previously transmitted pulse is not always the same, but a stochastically distributed distance. The received signal e (t) is preferably after appropriate treatment (z. B.

Mix sampled at an intermediate frequency or to baseband, IQ Education, filtering). In this case, the sampling are selected so that they transmit pulse to the previous time t_P(N) a delay t_A(M), m ε {0,1, ..., M -1} own; each time interval t_A(M), m = 0,1, ..., M -1, corresponds to a so called range gate. For each of the M range gates in total N (m) are formed per cycle samples; in what way this is done, whether such. as serial or parallel, is not relevant for future viewing.

In overreach and confusion from pulsed, working in the same frequency range systems are due to the pseudo noise code of the pulse repetition T_P (N) in each range i. Allg. only disturbed individual samples - one speaks of transient interferers. But this could be enough in the case of high interference already that the further signal processing

(Spectral Doppler to determine z. B. by FFT or performance analysis z. B. by power integration) delivers unusable results. Fig. 2a shows an example in discrete Time domain, a sine wave, which numerous high interfering pulses are superimposed; in the spectrum of the resulting signal of the spectral peak of the sinusoidal oscillation has disappeared in the noise generated by the noise pulses.

Here comes the median filtering is used. The median filter lengths are preferably to choose, the higher may be the more values ​​disturbed; at a power analysis can be the

Select Media filter lengths up to the number N (m) of samples, in the case of a spectral analysis of Doppler determination the median filter lengths are limited by the largest to be detected Doppler frequency (because of the low-pass characteristic of median filters), which oversampling presupposes. . Disturbed signal illustrated in Fig 2a for the results after a two-stage median filter with a respective filter length K = 5, the course shown in Fig. 2b; the useful signal, a sine wave is reconstructed almost completely back in the time domain and clearly visible in the spectrum thus.

Thus, when combining the pseudo-noise coding of pulse repetition and the median filtering as a suppression suitable transient interferers nonlinear filtering, so you can reduce the influence of overreach and confusion from pulsed, working in the same frequency range systems greatly or entirely eliminated. In addition, first an adequate pre-processing of samples such. B. is preferably in each range provided a value squaring for a power analysis. Figure 3 shows by means of a block diagram, the inventive pulse-Doppler radar system.

The individual elements of this system, in particular the matched filter and the elements of the FPGA will be explained in more detail.

The radar system includes an RF receiver section having a downstream amplifier, band-pass optimum filter and A / D converter. At the output of the A / D converter a complex output signal can be picked up, which is a downstream FPGA fed. The FPGA consists of a digital modulation device, the median filter to pulse interferences and a low-pass decimation filter formed as arranged in series with each other. The FPGA unit also includes a PN generator. Further, a noise filter is provided, which is arranged upstream of the A / D converter. The FPGA downstream is a digital signal processor (DSP), which in the present case a

comprising means for generating a window function, an FFT means (Fast Fourier Transformation) and a Störlinienkompensator. Subsequently, the detection threshold is determined on the basis of and a device for setting objectives, which produces a target list supplied. The DSP is connected downstream of a micro-controller unit (MCU), which generates control values ​​for the vehicle from the destination list, in case of need. For this purpose, a first

made "tracking" the destination list and determines a relevant object. The information about is fed to a series regulator, which then produces the desired manipulated variables. The DSP function and the MCU can of course also by a single program-controlled unit, for example, a microcomputer, are met. Below will be explained briefly with reference to figures 4 and 5, the Doppler method. In this case, figure 4 uses a simplified diagram of the principle of the Doppler method and figure 5, the signal-time diagrams for the diagram of figure 4. In the Doppler method, a complex sample of the received signal is performed in order to detect the sign of the speed. Radar system with the pulse Doppler method are characterized in that the speed and the distance represent direct measures. The RF section can be characterized in comparison to the FMCW system mentioned realize much easier, as there is a free-running oscillator (VCO) can be used with low demands on its phase and amplitude noise and no frequency ramps have to be generated.

A measurement cycle lasts for example. Each 50ms. The measurement result is a target list that is a snapshot of the traffic situation. Each measurement cycle are 5 measuring blocks, namely a Störlinienmessblock, an IF measurement block and three antenna measurement blocks allocated (for each antenna a). Each of these measurement blocks 2,76ms lasts. During this time, for example, 1024 + 64 transmitter pulses are generated, the first 64 transmit pulses serve the settling of the filter and are thus not recovered. After each transmission pulse 40 times is sampled at intervals of 25ns. This will ensure that each target is detected in at least one range gate.

The switches ANT0 to ANT2 one of three antennas is selected. By closing the transmit switch TX 25ns for the signal of the oscillator is applied to the selected antenna and radiated. After this transmission of a rectangular transmitted pulse the receiver switch RX is closed, and the frequency of the oscillator is changed by 200MHz. Thereby, the

Transformed received pulses through the mixer to an intermediate frequency of 200MHz. The Doppler shift of the frequency may be disregarded at this point. The thus resultant real signal m (t) is applied to one designed as a matched filter passive bandpass which has two mutually orthogonal outputs having the same amplitude and thus generates the complex signal k (t), ie, there is an IQ signal is implemented without complex mixture ,

The IQ signal at the output of the bandpass filter is sampled 40 times after each transmitter pulse at intervals of 25ns. The individual sampling instants corresponding to a respective distance range - they therefore called range gates are possessing and extend to a distance of 150m in width 3.75m. Since a rectangular reception of the pulse length is 25 ns smoothed by the band pass filter to a triangular pulse of twice the length, and thus i. Allg. is visible in two successive range gates, the exact distance can be interpolated by evaluating the amplitude ratios of these two range gates.

To determine the relative speed of the targets with respect to the own vehicle and to increase the signal-to-noise ratio, the complex received signals of 1024 successive transmission pulses are evaluated in each range E, without changing the selected antenna A. In the case of equidistant transmit pulses shows image 4 the real and imaginary d] (n, E, A) and d_Q(N, E, A) of the 1024 complex samples d (n, E, A) of a range in which there is a relatively moving target (during the short observation time of 2.56 ms for the 1024 sample, the relative velocity can always be considered constant ); from sample to sample, the phase changes uniformly as the distance of the target and thus the phase of the received pulse change uniformly - it results exactly the Doppler frequency including its sign (because the signal is complex).

The method just described is applied sequentially for each of the three antennas. One of the antennas is looking straight ahead, while the other two are slightly tilted to the left or right in order to determine as the position of the detected targets relative to the own lane can

The received signal always includes a noise amount, which manifests itself as noise. The disorder has approximated to the characteristics of white noise. To best possible filter out this noise, ie to achieve a maximum signal-to-noise ratio, a matched filter is used. Its transfer function corresponds to the

Spectrum of the received intermediate-frequency pulses (pulses IF), i.e., the spectrum of a modulated with the pulse width 25ns 200MHz rectangle. The optimum filter thus corresponds to a bandpass.

The matched filter used is advantageously realized as an embedded in ohmic resistances LC quadrupole. In the frequency range this is a particularly convenient and flexible technology, as required for this purpose inductors are available as SMD components. The filter circuit can thus very simple, small and thus also inexpensive to build.

In the design of such a matched filter according to the known method according to Bader two design strategies are possible: 1. First, a required pursuant matched lowpass is designed. a transformation of the low-pass filter is then made it into a bandpass. This variant, however, is of limited use, and only for special circuits, since it leads to the realization of the circuit unsuitable structures and components values.

2. Direct design a bandpass filter: This variant is particularly advantageous, although somewhat more expensive and the design, as they alternate at different

Structures leads that well required more or less depending on the requirements for the

Ratios are adjusted. In this method, an approximation of the ideal transfer function is performed.

Fig. 6 shows dashed the transfer function of an optimum filter produced in the direct design; the thin continuous curve belongs to the ideal matched filter, which is very well approximated or simulated by the real circuit.

7 shows a first circuit arrangement for the realization of an approximated by Bader matched filter: The values ​​of inductors, capacitors and resistors are rounded to real disposable values. Degrees of freedom in development were here so exploited that advantageously no transformer is needed. The structure shown in Figure 7 has the

Unlike its dual structure of almost every node capacitances to ground, in which the stray capacitances can be included in the calculation.

The output signals k | (t) and ko (t) of the circuit in Figure 7 are orthogonal to each other, ie, they have a phase difference of 90 ° to one another, and possess at the intermediate frequency fzp = 200MHz same amplitude, which is achievable through degrees of freedom in development , The complex output signal k | (t) + j^*ko (t), hereinafter referred to as IQ signal, thereby constitutes a complex oscillation of the real input vibration having the intermediate frequency fIF. This so-called IQ signal was realized advantageously without any mixing.

(T) and ko (t), are designed to ground | it if both of the real part and the imaginary part associated with the output signal, ie k is particularly advantageous. 6 shows using a circuit diagram a second, preferred embodiment of an approximated optimum filter in which this account receivable is worn. The output side of the filter circuit was thereby doubled substantially.

This illustrated in Figure modified output stage has the further advantage that despite resistive and capacitive load of the A / D converter of the I / Q character of the

Output signal is maintained. Only the filter characteristic changes slightly.

A according to the Figures 7 and 8 formed band-pass optimum filter thus comprises in summary the following advantageous functions:

The filter has an optimized signal-to-noise ratio. - The filter creates a simple, but very reliable way a largely accurate

IQ signal can be picked off at the output of the filter.

Since the triangular output signal is visible in two range gates and the amplitude ratio, the distance can be determined, a simple interpolation of the distance is possible in this way. The FPGA block in Figure 3 has a device for digital modulation 'of the

Optimal filter produced on complex output signal. Such a device is necessary because the velocity range of interest is not symmetrical and typically would lead to an unbalanced frequency range; in Application Example interest rates in the range of -88.2 to +264.7 km / h. By means of a frequency offset of -12.5kHz can it create a symmetric frequency range. By means of an appropriately dimensioned device for digital modulation can be realized that, for example, by multiplication of the sampled IQ-signal with a signal which is generated by a rotating complex phasor amplitude of 1 and the rotational frequency -12.5kHz.

Further, the FPGA block comprises a nonlinear filter against pulse interferences. Pulse-shaped disturbances originate eg overreach or pulse radar systems of other

Traffic participants. A pseudo-noise coding of the sampling pulse interferences are all distance gates (more or less uniformly) distributed. This only individual values ​​are disturbed in each range. By pseudo-noise coding and non-linear filtering, for example, by Media Filter, unwanted pulse interferences can be compensated.

For the realization of the filter against pulse interferences following issues should be considered:

A linear filter is here less advantageous because of the filter subsequent Dezimationstiefpass already represents a linear filter with minimal bandwidth. Conceivable are all non-linear filters, can compensate for that individual incorrect values; many of these filters, however, are problematic in terms of stability and implementation on a FPGA.

Here is advantageously to use a single- or multistage median filter. In a preferred embodiment, this filter has two stages, each with the length 5. Advantageously, by the upstream A / D converter oversampling performed.

The median of K values ​​is the middle value, ie the (K + 1) / 2 = smallest value (K + 1) / 2-largest value.

For example, the median of the five numbers 5, 3, 2, 79, 1 is equal to 3. A sliding median filter without reduction of the sampling rate calculated at each instant n the median of K successive values ​​of an input sequence x (n) and generates an output signal m (n). For

Median filters are many algorithms are known which are particularly suitable for a software implementation. These are based on sorting with concomitant high computation time or statistical analysis with concomitant high memory requirements of data. For a hardware implementation, these algorithms are very useful, since they typically require too many case differentiations and branches.

However, a new algorithm for a hardware realization of a median filter, it has now been developed: The operation is already reference to the Figures 9a, 9b, 9c, and has been shown 10a, 10b, 10c. With such a structure can be significantly reduced in many cases the cost of a median filter, especially if the maximum cycle time of the FPGA is substantially greater than the word clock of the input signal. A further advantage consists in the easy scalability

Structure.

The FPGA block in Figure 3 further includes a decimation. The decimation filter is advantageously designed as low-pass.

In the present embodiment, a decimation of the sampling frequency of 400kHz to 50 kHz, that is by a factor of 8, made. This is - in the case of an ideal

Dezimationstiefpasses - an improvement of the signal-to-noise ratio by up to 9dB possible.

A real Dezimationstiefpass must fulfill the requirements steepest possible flanks to the frequencies f = ± 25kHz around. It is not necessary I Hreal (j2πf) | = Const in the passband | f | &lt;25kHz, as in the evaluation only spectra to be recycled and thereby can be easily compensated for amplitude error. In Figure 11, the transfer function of an ideal and a real Dezimationstiefpasses shown. The lowpass used for this consists of two moving average formers, the second is already working with the halved input clock rate. The moving averaging of length N averaged over the current and the N-1 preceding values. Figure 12 shows the impulse response h (n) of such a sliding averaging unit and a signal flow diagram. The averaging can be implemented very efficiently in recursive form.

The overall structure of an advantageous embodiment of a Dezimationstiefpasses's

Figure 13 shown. A missing factor 64/40 at the output is at a subsequent windowing for digital Fourier transform (DFT) with realized. For such a decimation filter with the

Grade 15 so the following elements must be provided: a shifter, four adders, four Memory elements. However, a multiplier is not required. In comparison with a conventional filter iinearphasigen with the degree 15 eight multipliers, adders 15, 15 memory must be provided. The decimation is thus characterized by a significantly lower outlay on circuitry.