Deep wordline trench to shield cross coupling between adjacent cells of nand memory

This invention relates generally to flash electrically erasable and programmable read only memory (EEPROMS), and more specifically to NAND flash memory with a high memory cell density.

Most existing commercial flash EEPROM products operate each memory cell with two ranges of threshold voltages, one above and the other below a breakpoint level, thereby defining two programmed states. One bit of data is thus stored in each cell, a 0 when programmed into one state and a 1 when programmed into its other state. A chunk of a given number of bits of data is programmed at one time into an equal number of cells. The state of each cell is monitored during programming so that application of programming voltages stops when the threshold level of an individual cell is verified to have moved within the range that represents the value of the bit of data being stored in the cell.

In order to increase the amount of data stored in a flash EEPROM system having a certain number of storage cells, the individual cells are operated with more than two threshold level states. Preferably, two or more bits of data are stored in each cell by operating the individual cells with four or more programmable states. Three threshold breakpoint levels are necessary to define four different threshold states. Such a system is described in <patcit id="pcit0001" dnum="US5043940A"><text>U.S. Patent Nos. 5,043,940</text></patcit> and <patcit id="pcit0002" dnum="US5172338A"><text>5,172,338</text></patcit>. In multi-state operation, an available operating voltage range of the individual cells is divided into an increased number of states. The use of eight or more states, resulting in storing three or more bits of data per cell, is contemplated. The voltage range of each state necessarily becomes smaller as the number of states is increased. This leaves less margin within each state to accommodate any error that might occur during operation of the memory system.

One type of error is termed a "disturb," wherein electrons are unintentionally added to or taken away from a floating gate during operation of the memory. One source of a disturb is the presence of a leaky oxide dielectric positioned between the floating gate and another conductive gate of a cell. The charge level programmed onto a floating gate of a cell changes when such a leaky oxide is present, thus leading to the possibility that the state of the cell will be incorrectly read if the change in charge has been large enough. Since few to no errors can be tolerated in a mass digital data storage system, a sufficient margin for this error is provided by making the voltage range allocated to each state sufficient to include an expanded range of voltages that can occur as the result of such disturbs. This necessarily limits the number of states that can be included in a multi-state flash EEPROM system since the total available voltage range is limited.

Another type of error is termed the "Yupin effect." The Yupin effect occurs when the neighboring cell of a selected cell is programmed after the selected cell itself is programmed, and the charges of the neighboring cell influence the voltage of the selected cell. Any potential present in an adjacent cell or string may influence the reading of a selected cell, including those in the channel, floating gate, or control gates etc... Such interference from the subsequently programmed neighbor cell distorts the voltages of the selected cell, possibly leading to an erroneous identification of its memory state during reading.

<patcit id="pcit0003" dnum="US20010014503A"><text>US 2001/0014503</text></patcit> discloses a memory device according to the preamble of Claim 1.

<patcit id="pcit0004" dnum="US6057580A"><text>US 6,057,580</text></patcit> disclose a non-volatile semi-conductor memory device, wherein part of a conductor layer can extend between adjacent floating gates.

<patcit id="pcit0005" dnum="US6159801A"><text>US 6,159,801</text></patcit> discloses a split-gate memory cell with a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell.

<patcit id="pcit0006" dnum="US5943572A"><text>US 5,943,572</text></patcit> discloses a memory cell arrangement wherein adjacent rows of memory cells run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches.

<patcit id="pcit0007" dnum="WO9944239A"><text>WO 99/44239</text></patcit> discloses a memory array in which a substrate is etched to provide trenches between remaining islands of silicon. These silicon islands comprise channel areas. A floating gate is provided on top of these channel areas as well as along the side walls of the trenches. The word line extends into the trenches so that the capacitive coupling between the floating gate electrode and the word line is maximised without compromising packaging density.

<patcit id="pcit0008" dnum="US5949101A"><text>US 5,949,101</text></patcit> discloses a further memory array. This memory array comprises trenches between strings of memory cells. These trenches are part filled with a shallow trench isolation material. This isolation material extends to a height that is below the top surface of the remaining substrate. This enables the word line to extend to a level below the top surface of the remaining substrate, thereby creating a transfer transistor between the word line and the substrate.

According to another aspect of the present invention there is provided a memory device formed from a substrate. The device comprises a plurality of strings of adjacent transistors of a NAND architecture, each string of the plurality of strings comprising a first select gate and a plurality of floating gates. The plurality of floating gates are formed above channel regions in the substrate and separated from the channel regions. Each of the plurality of floating gates has a T-shaped structure having a lowermost bottom surface that is situated above a top height of the channel region. A gate oxide layer in provided between the floating gates and the substrate. Shallow trench isolation trenches are provided between adjacent strings wherein the trenches are filled with a field oxide that extends to a level above the top surface of the substrate. The memory device is a flash memory device. Each string comprises a second select gate. The device is arranged to cause programming operations in adjacent first and second strings to be conducted at the same time. Wordlines extending across adjacent strings extend between the floating gates of the first and second strings into the field oxide in the shallow trench isolation trenches down past the level of an upper surface of the field oxide filling the trenches and the level of an uppermost top surface of the gate oxide layer between the channel regions of the first and second strings.

The present invention is an improved structure for high density NAND type flash memory that minimizes the effect of disturbs and Yupin effect errors.

The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings of illustrative embodiments of the invention.

<figref idref="f0002">FIG. 1A</figref> is a plan view of the structure of memory array 100.

<figref idref="f0001">FIG. 1B</figref> is an electrical circuit diagram corresponding to the structure of <figref idref="f0002">FIG. 1A</figref>.

<figref idref="f0002">FIG. 2</figref> is a cross section of memory array 100.

<figref idref="f0002">FIG. 3</figref> is a cross section of memory array 100.

<figref idref="f0002">FIG. 4</figref> is a cross section of memory array 100.

<figref idref="f0003">FIG. 5A</figref> is a plot of program voltage vs. time during a program operation.

<figref idref="f0003">FIG. 5B</figref> is a plot of the voltage distribution of programming steps.

<figref idref="f0003">FIG. 5C</figref> is a plot of cell voltage vs. program voltage.

<figref idref="f0004">FIG. 5D</figref> is an illustration of an adjacent memory cell during a program operation.

<figref idref="f0004">FIG. 5E</figref> is an illustration of an adjacent memory cell during lockout.

<figref idref="f0005">FIG. 6</figref> is a flow chart of a method of forming an embodiment of the present invention.

<figref idref="f0006 f0007">FIGS. 7A-7L</figref> are cross sections of memory array 100 at various stages during the fabrication process.

The following is a detailed description of illustrative embodiments of the present invention. As these embodiments of the present invention are described with reference to the aforementioned drawings, various modifications or adaptations of the methods and or specific structures described may become apparent to those skilled in the art. All such modifications, adaptations, or variations that rely upon the teachings of the present invention, and through which these teachings have advanced the art, are considered to be within the scope of the present invention. Hence, these descriptions and drawings are not to be considered in a limiting sense, as it is understood that the present invention is in no way limited to the embodiments illustrated.

<figref idref="f0002">FIG. 1A</figref> illustrates a plan view of an embodiment of the NAND flash memory of the present invention. <figref idref="f0002">FIGS. 2-4</figref> are cross sections taken through the structure shown in <figref idref="f0002">FIG. 1A</figref>. An electrical equivalent circuit of the memory array is given in <figref idref="f0001">FIG. 1B</figref>, wherein common elements within the structure of <figref idref="f0002 f0001">FIGS. 1A and 2-4</figref> are identified by the same reference character.

Parallel wordlines 106 connect adjacent NAND strings of floating gates 102. The wordlines 106 are illustrated horizontally, and the strings are illustrated vertically in the figures. A NAND string generally includes a select gate followed by several floating gates and another select gate. The bitline A, B, and C (BL_A, BL_B, BL_C) locations correspond to the string locations in the plan view, although the bitlines are generally located in another plane. The circuit diagram of <figref idref="f0001">FIG. 1B</figref> most clearly shows the vertical array of strings. In this case sixteen floating gates and thus sixteen wordlines are illustrated per string, however, the number of floating gates may be thirty-two or more, and is foreseen to increase in the future. Floating gates 102 are isolated from adjacent floating gates by isolation trenches 104. Isolating trenches 104 are also referred to as shallow trench isolation areas. The select gate line 105 on the source side ("SS") is continuous between trenches 104, as can be seen in section C-C of <figref idref="f0002">FIG. 4</figref>. It is not etched into individual floating gates. At the end of the wordline 106 above SS 105, each NAND string is electrically connected to SS 105 with a via, most easily seen in <figref idref="f0001">FIG. 1B</figref> an <figref idref="f0002">FIG. 3</figref>.

Metal bitlines 116 (only one of which is shown for the sake of clarity) connect to the N+ regions 114 within substrate 108 to sense amplifiers for reading the charge stored in the floating gates 102. Thus, to read a particular floating gate a string is selected via the bitline and a wordline is also selected. The metal bitlines are generally, but not necessarily, formed in a conductive layer insulated from the wordlines. At the end of each string is another select gate coupled to the drain ("SD"). The drain and source can be interchanged in some configurations and more than 16 transistors can also be present in each string, thus also increasing the number of wordlines.

As seen in <figref idref="f0002">FIG. 2</figref>, there is a portion of gate oxide 112 between each floating gate 102 and the substrate 108. A dielectric material 110 separates the wordlines 106 from the floating gates 102 and the isolation trenches 104. Adjacent floating gates 102 are isolated from other floating gates in the same wordline, not only by isolating trenches 104, but also by wordlines 106. Wordlines 106 extend down between floating gates into isolation trenches 104, within, or past the level of gate oxide layer 112. This has several distinct benefits.

It reduces Yupin effects between adjacent cells in the wordline direction. Also, it improves the cell coupling ratio between the wordlines and the floating gates. The portion of the wordline that extends into the isolation trenches, past the depth of the floating gates, increases the overlap of the surface areas and volumes of the wordlines and floating gates. This increased overlap results in better coupling when a charge is read or stored during program, read, or erase operations.

The electrical field across the dielectric layer 110 between adjacent floating gates is reduced, therefore reducing any leakage current through the dielectric layer that may occur as a result of the electrical field. The lesser the electrical field, the lesser the leakage current between two adjacent floating gates. Additionally, the leakage current path is greatly increased by the extended wordlines 106. Any leakage current must travel down and around the extended portion of the wordlines and then back up or over to the adjacent floating gates. The charge level programmed onto a floating gate of a cell changes when such a leakage current is present. Therefore, by minimizing the leakage current, and thus any change in charge of the floating gates, an increased number of levels can be discerned more reliably. This leads to a higher capacity, more cost efficient, and more reliable data storage system.

Additionally, the extended wordline shields a selected floating gate from field effects of nearby channels. In certain program, read, and verify operations, a floating gate that has been programmed with a particular charge may, in a subsequent read or verify operation, indicate that it has a larger charge than it should due to a potential or charge in an adjacent channel. This is especially true with complicated program, read, and verify operations in multi-state NAND flash memory where multiple operations are occurring simultaneously in adjacent strings and cells. In many prior systems, every other cell along one row is part of the same page; in newer systems, every cell along one row can be part of the same page. Referring again to <figref idref="f0002">FIG. 2</figref>, this would mean that in a prior system, the floating gate 102A activated by BL_A and the floating gate 102C activated by BL_C would be programmed while the floating gate 102B activated by BL_B is not programmed. In newer systems, every cell along one row can be part of the same page. Thus, as seen in <figref idref="f0002">FIG. 2</figref>, floating gate 102A of the string activated by BL_A may be undergoing a programming operation at the same time as floating gate 102B. This will be discussed in further detail later in reference to <figref idref="f0004">FIGS. 5D and 5E</figref>. In this way, twice the number of cells may be programmed and or verified at the same time. Although this may be efficient, it results in additional field effect problems during all of the various operations involved in data storage operations.

The relationship between the distribution and the incremental voltage of the programming pulses holds true only if the potential of any other coupling element to the floating gates of the cells being programmed remains constant. In the case of programming adjacent NAND strings, an adjacent (substrate) channel of an adjacent cell may be at a low potential, for instance 0V, for a number of programming pulses while it is being programmed and then suddenly be boosted or "locked out" for subsequent programming pulses to a high potential, for instance, 5, 7.5, or 10 V, after it verifies in order to stop further programming or for any other reason. This boosting of the channel potential also increases the floating gate potential of the adjacent cell. Thus, both the adjacent channel and adjacent floating gate will couple a higher potential to the selected cell for the next programming pulse which may broaden the width of the programmed distribution. This has a number of negative consequences, some of which may include error in reading a particular bit and reduction in the total number of bits of data that may be stored in a given die size. An example of some programming details is illustrated in <figref idref="f0003 f0004">FIGS. 5A-5E</figref> which will be discussed below. The levels given are illustrative and only serve to educate the reader on the operation of an example memory system with which the present invention may be particularly advantageous.

For further information regarding the data storage operations, please refer to. <patcit id="pcit0009" dnum="US89327701A" dnum-type="L"><text>U.S. Patent Application Serial No. 09/893,277, filed June 27, 2001</text></patcit>, entitled "Operating Techniques For Reducing Effects Of Coupling Between Storage Elements Of A Non-Volatile Memory Operated In Multiple Data States," and <patcit id="pcit0010" dnum="US6522580B"><text>granted as US 6,522,580</text></patcit> , and an article entitled "<nplcit id="ncit0001" npl-type="s"><text>Fast and Accurate Programming Method for Multi-level NAND EEPROMs", pp. 129-130, Digest of 1995 Symposium of VLSI Technology</text></nplcit><i>,</i> which discusses the timing and voltage levels of programming pulses using in the read/verify and programming operations.

An example of the incremental voltage steps of the programming pulses are shown in <figref idref="f0003">FIG. 5A</figref>. In the example shown and described, the pulses are incremented by 0.2 volts. After each pulse, there is a verify cycle, followed by an incrementally higher voltage pulse. This takes place until a desired or threshold voltage is verified in the floating gate. For example, this may take place until the floating gate is verified at 2.0 volts.

<figref idref="f0003">FIG. 5B</figref> illustrates that for each program pulse, there is a distribution of the charge stored in the floating gates. For example, with the first pulse of 16.0 volts, the distribution of the verified charges is about three volts. So, if it is desired to store 2.0 volts on the floating gate, it may be necessary to increment up to 17.0 volts and higher in the control gate or wordline. If, for example, after a 17.0 volt programming pulse the distribution of stored charges on the floating gates is such that there are some floating gates above and some below the 2.0 V threshold, those below will receive a further programming while those above the threshold will not by having their channel boosted or "locked out."

With a constant environment, i.e. one where the potential and electric field of the neighboring components is constant, the programming pulses, will, after having reached a steady state, result in a predictable and approximately linear increase in the cell voltage (V_t), as seen in <figref idref="f0003">FIG. 5C</figref>. As seen in the nearly parallel lines, some "fast" floating gates may reach the desired verify V_t at a lower program voltage than other "slow" or "intermediate" floating gates. Once the steady state has been reached, it can be seen that a linear increase in the program voltage results in a nearly linear increase in V_t.

Therefore, if, for example, a cell has a V_t of 1.99 volts, it will receive another programming pulse to take it above the 2.0 volt threshold. In a constant environment, the cell should then have a V_t of 2.19 volts. However, if there is any deviation of the voltage or electric field that is applied to the cell, for example between one programming pulse and another, the voltage stored on the cell may differ from that expected. If a neighboring component exerts an influence of the electrical field of the cell during a programming pulse, the charge stored will also deviate. For example, the cell that was at 1.99 volts in the previous verification cycle, may instead of having a V_t of 2.19 volts may have a V_t of 2.29 or 2.39 volts. As shown in <figref idref="f0003">FIG. 5C</figref>, coupling of potential from a nearby cell may cause one of the intermediate cells to deviate from the linear increase that is characteristic of the steady state. Thus, the distribution of the cells shown in <figref idref="f0003">FIG. 5B</figref> will increase due to any variation in the potential of adjacent components.

The increase in the distribution of cells will lessen the number of states that can be repeatably and reliably discerned in a multi-level storage system. This greatly lessens the storage capacity of a memory device with a given die size, and therefore increases the cost of production of a storage device with a desired storage capacity.

Specifically, as can be seen in <figref idref="f0004">FIGS. 5D and 5E</figref>, the voltages in the components of an adjacent cell will vary greatly during program and during "lockout." An adjacent cell is any cell located near another cell, in any direction, including diagonally. For example, floating gate 102A is adjacent to floating gate 102B. The active area of the cell comprises the channel area in the substrate below the floating gate and the wordline area above the floating gate. The cell may also be said to comprise portions of the shallow trench isolation area and other components. A cell is "locked out" by isolating its corresponding bitline if it has verified at the desired program voltage. In the example given above, if the cell has verified at 2.0 volts, it will be "locked out" from further programming pulses by increasing the cell voltage in the channel (substrate) to a relatively high voltage level by isolating the corresponding bitline.

<figref idref="f0004">FIG. 5D</figref> shows an adjacent cell during the programming operations previously discussed. The shape and configuration of the cells is simplified for ease of understanding. In the example programming operation shown, wordline 106 of the cell is at 18 volts, floating gate 102 is at 10 volts, and substrate 108 is at 0 volts. However, during lockout, as shown in <figref idref="f0004">FIG. 5E</figref>, wordline 106 is now at 18.2 volts, floating gate 102 is now at 13 volts, and substrate 108 is now at 8.0 volts. The channel is a portion of the substrate just below the upper surface of the substrate. While a selected cell is being programmed, an adjacent cell may be either in the program operation shown in <figref idref="f0004">FIG. 5D</figref>, or the lockout state shown in <figref idref="f0004">FIG. 5E</figref>. Furthermore, the voltages shown in the program operations vary with the different programming pulses discussed earlier. All of these voltages shown in an adjacent cell may couple to a selected cell during programming. It is the variation in these voltages that may result in the variation from steady state programming (<figref idref="f0003">FIG. 5C</figref>) and thus increased deviation (<figref idref="f0003">FIG. 5B</figref>).

<figref idref="f0005">FIG. 6</figref> is a flowchart of the steps of making memory array 100 which should be referred to in tandem with <figref idref="f0006 f0007">FIGS. 7A-7L</figref>. The memory array 100 is fabricated in a substrate 108. Substrate 108 preferably comprises silicon but may also comprise any material known to those in the art such as Gallium Arsenide etc... First, a gate oxide layer 112 is formed upon substrate 108 in step 505 as seen in <figref idref="f0006">FIG. 7A</figref>. Gate oxide 112 is preferably grown on substrate 108 but may also be deposited. Gate oxide layer 112 preferably comprises silicon dioxide but may differ depending on what type of substrate is used and other processing factors or elements introduced during processing. For example, for CMOS applications, gate oxide 112 may comprise materials (known as ETO) including nitride/oxynitride. Next, a first gate layer 102a is deposited upon gate oxide layer 112 in step 510 as seen in <figref idref="f0006">FIG. 7B</figref>. The first gate layer 102a is made of semiconducting material such as polysilicon. A nitride layer 120 is then deposited upon the first floating gate layer 102a in step 515 as seen in <figref idref="f0006">FIG 7C</figref>. In step 520, parallel trenches are etched in substrate 108 with well known etching techniques. Generally in fabricating high density memory arrays where the features are of a very small scale, plasma etching is preferred over wet etching in order to have a precise and uniform etch. In step 525 the trenches are then filled with a field oxide, as seen in <figref idref="f0006">FIG. 7D</figref>, to form isolation trenches 104. The field oxide within isolation trenches 104 is preferably comprised of silicon dioxide but can be comprised of other insulating materials (including materials other than oxides). Isolation trenches 104 range from about 0.2 microns to about 0.25 microns wide and are preferably about 0.2 microns wide. The remaining field oxide 124 is removed via chemical-mechanical polishing ("CMP") in step 530, as seen in <figref idref="f0006">FIG. 7F</figref>.

Next, in step 535, nitride layer 120 is etched away such that isolation trenches 104 extend above the surface of the first gate layer 102a, as seen in <figref idref="f0006">FIG 7G</figref>. The isolating trenches 104 may extend above the substrate 108 and gate oxide layer 112 as shown, or, alternatively, may only extend up to the level of either the substrate 108, gate oxide layer 112, or first gate layer 102a, and it should be understood that differing processes and steps may be necessary to achieve these differing embodiments.

A second gate layer 102b of the same semiconducting material as the first gate layer 102a is then deposited upon the gate oxide layer 112 and isolation trenches 104 in step 540. It is then selectively etched above isolation trenches 104 to create floating gates 102 in step 545. The resultant structure can be seen in <figref idref="f0007">FIG. 7H</figref>. Floating gates 102 are substantially "T" shaped in order to maximize the coupling between the floating gate and the control gate, also referred to as the wordline 106 that activates the floating gate. The line between the first and second gate layers 102a and 102b has been removed for the sake of clarity. The T shape provides a large surface area between floating gate and the wordline, thus maximizing the coupling ratio between the two devices for improved read, program and erase operations. For further information, please refer to co-pending <patcit id="pcit0011" dnum="US925102A" dnum-type="L"><text>U.S. Patent Application No. 09/925,102 to Yuan et al.</text></patcit>, entitled "Scalable Self-Aligned Dual Floating Gate Memory Cell Array and Methods of Forming the Array," and granted as <patcit id="pcit0012" dnum="US6762092B"><text>US 6,762,092</text></patcit>.

As seen in <figref idref="f0007">FIG. 7J</figref>, a set of parallel trenches 122 is formed within isolating trenches 104 in step 550. Trenches 122 extend within trenches 104 to any distance within trenches 104 within or below the level of gate oxide 112. Isolation layer 110 is then deposited upon the floating gates 102, and within second trenches 122 in isolation trenches 104, in step 555, as seen in <figref idref="f0007">FIG 7K</figref>. Isolation layer 110 is preferably a dielectric layer such as an oxide-nitride-oxide ("ONO") layer 110. The dielectric layer 110 can be any type of dielectric known in the art and is not necessarily limited to an ONO structure. A wordline layer comprising a semiconducting material layer such as polysilicon and a conductive layer such as tungsten silicide is then deposited upon dielectric layer 110 in step 560, as can be seen in <figref idref="f0007">FIG. 7L</figref>. Wordlines 106 are then etched from the wordline layer in step 565.

As previously mentioned, the wordlines 106 extend down between the floating gates 102 into the isolating trenches 104. This isolates adjacent floating gates 102 from each other. Moreover, wordlines 106 extend within the isolation trenches 104 beyond the level of the upper surface of the gate dielectric 112.

The various layers can be formed and the etching steps can be performed in many different well known methods and orders, and are not necessarily done in the order described, i.e. gate oxide layer 112 may be formed before or after the parallel trenches are etched into substrate 108 etc... Furthermore, additional layers, steps, and resultant structures that are not described may also be part of the process and the resultant memory array.

The extended wordline reduces the problem of the aforementioned Yupin effect because it acts as a shield between adjacent floating gates. Again, in short, the Yupin effect is when the charge stored or otherwise present in a neighboring cell influences the reading of a selected cell. The present solution shields gates to avoid or minimize Yupin effect errors caused by neighboring gates. Yupin effect errors can also be accommodated through program and read circuitry and algorithms.

The extended wordline also protects against conduction leakage between adjacent floating gates within the dielectric layer 110 because it blocks the conduction path between adjacent gates. Furthermore, any possible stringers as a result of an incomplete etch of the floating gate layer that might short circuit adjacent gates are also eliminated in the situation where the etch within the isolation trench extends past the upper (top of the "T") portion of the T shaped floating gate. For more information on the Yupin effect and on disturbs, please refer to <patcit id="pcit0013" dnum="US5867429A"><text>U.S. Patent No. 5, 867,429</text></patcit>, which was previously referred to.