Method and system for encoding short block length low density parity check (LDPC) codes

FIELD OF THE INVENTION

0001The present invention relates to communication systems, and more particularly to coded systems.

BACKGROUND OF THE INVENTION

0002Communication systems employ coding to ensure reliable communication across noisy communication channels. For example, in a wireless (or radio) system, such as a satellite network, noise sources abound, from geographic and environmental factors. These communication channels exhibit a fixed capacity that can be expressed in terms of bits per symbol at certain signal to noise ratio (SNR), defining a theoretical upper limit (known as the Shannon limit). As a result, coding design has aimed to achieve rates approaching this Shannon limit. This objective is particularly germane to bandwidth constrained satellite systems. One such class of codes that approach the Shannon limit is Low Density Parity Check (LDPC) codes.

0003Traditionally, LDPC codes have not been widely deployed because of a number of drawbacks. One drawback is that the LDPC encoding technique is highly complex. Encoding an LDPC code using its generator matrix would require storing a very large, non-sparse matrix. Additionally, LDPC codes require large blocks to be effective; consequently, even though parity check matrices of LDPC codes are sparse, storing these matrices is problematic.

0004From an implementation perspective, a number of challenges are confronted. For example, storage is an important reason why LDPC codes have not become widespread in practice. Length LDPC codes, thus, require greater storage space. Also, a key challenge in LDPC code implementation has been how to achieve the connection network between several processing engines (nodes) in the decoder. Further, the computational load in the decoding process, specifically the check node operations, poses a problem.

0005<nplcit id="ncit0001" npl-type="s"><text>Le Goff S.Y.: "Channel capacity of bit-interleaved coded modulation scheme using 8-ary signal constellations", IEE Electronic Letters, vol. 38, no. 4, 14th Feb. 2002</text></nplcit> (XP006017828) describes bit-interleaved coded modulation using 8-ary signal constellations.

0006[05a] <nplcit id="ncit0002" npl-type="s"><text>Le Goff S.Y.: "Signal constellations for bit-interleaved coded modulation", IEEE Trans. on Inf. Theory, vol. 49, no. 1, Jan. 2003, pp. 307-313</text></nplcit> describes bit-interleaved coded modulation used in conjunction with turbo codes.

0007[05b] <nplcit id="ncit0003" npl-type="b"><text>Le Goff S.Y.: "Signalling constellations for power-efficient bit-interleaved coded modulation schemes", IEE PROCEEDINGS : COMMUNICATIONS, INSTITUTION OF ELECTRICAL ENGINEERS, GB, 13 June 2003, pp. 141-148</text></nplcit> (XP006020428) describes different signal constellations for bit-interleaved coded modulation schemes.

0008[05c] <nplcit id="ncit0004" npl-type="s"><text>Hou J. et al.: "Capacity-approaching bandwidth-efficient coded modulation schemes based on low-density parity-check codes", IEEE Trans. on Inform. Theory, vol. 49, no. 9, pp. 2141-2155</text></nplcit> describes bandwidth efficient-coded modulation schemes based on Low-Density Parity-Check (LDPC) codes.

0009[05d] <nplcit id="ncit0005" npl-type="s"><text>Richardson T.: "The renaissance of Gallager's low-density parity-check codes", IEEE Communications Magazine, Aug. 2003, pp. 126-131</text></nplcit> (XP001177711) discloses some background information on Low-Density Parity-Check (LDPC) codes.

0010[05e] <nplcit id="ncit0006" npl-type="s"><text>Calzolari G.P.: "Report on DVB-S2 channel coding standardization effort", CCSDS Sub-Panel 1B Channel Coding, 7th April 2003, Matera, Italy</text></nplcit> (XP002311762) discusses the possibility of using various modulation schemes in conjunction with Low-Density Parity-Check (LDPC) codes.

0011[05f] There is still a need for an LDPC communication system that employs simple encoding and decoding processes. There is also a need for using LDPC codes efficiently to support high data rates, without introducing greater complexity. There is also a need to improve performance of LDPC encoders and decoders. There is also a need to minimize storage requirements for implementing LDPC coding.

SUMMARY OF THE INVENTION

0012These and other needs are addressed by the present invention, wherein an approach for encoding Low Density Parity Check (LDPC) codes is provided. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code according to one of Tables 2-8 for transmission as the LDPC coded signal. Each of the Tables 2-8 specifies the address of parity bit accumulators. Short LDPC codes are output by utilizing LDPC mother codes that are based on Tables 2-8. <i>k_ldpc</i> of the BCH encoded bits are preceded <i>by k_m -k_ldpc</i> dummy zeros. The resulting <i>k_m</i> bits are systematically encoded to generate <i>n_m</i> bits. The first <i>k_m - k_ldpc</i> dummy zeros are then deleted to yield the shortened code. For an LDPC code with code rate of 3/5 utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The approach advantageously provides expedient encoding as well as decoding of LDPC codes, while minimizing storage and processing resources.

0013One aspect of an embodiment of the present invention is a method for supporting transmission of a Low Density Parity Check (LDPC) coded signal as specified in the appended claims.

0014According to another aspect of an embodiment of the present invention, the modulated LDPC coded signal is transmitted over a satellite link in support of a broadband satellite application.

0015Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, simply by illustrating a number of particular embodiments and implementations, including the best mode contemplated for carrying out the present invention. The present invention is also capable of other and different embodiments, and its several details can be modified in various obvious respects, all without departing from scope of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

0016The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

0017<figref idref="f0001">FIG. 1</figref> is a diagram of a communications system configured to utilize Low Density Parity Check (LDPC) codes, according to an embodiment of the present invention;

0018<figref idref="f0002">FIGs. 2A and 2B</figref> are diagrams of exemplary LDPC encoders deployed in the transmitter of <figref idref="f0001">FIG. 1</figref>;

0019<figref idref="f0003">FIGs. 2C</figref> and <figref idref="f0004">2D</figref> are flowcharts of the encoding process of the LDPC encoder of <figref idref="f0002">FIG. 2B</figref> for generating short frame length LDPC codes, according to an embodiment of the present invention;

0020<figref idref="f0005">FIG. 3</figref> is a diagram of an exemplary receiver in the system of <figref idref="f0001">FIG. 1</figref>;

0021<figref idref="f0006">FIG. 4</figref> is a diagram of a sparse parity check matrix, in accordance with an embodiment of the present invention;

0022<figref idref="f0006">FIG. 5</figref> is a diagram of a bipartite graph of an LDPC code of the matrix of <figref idref="f0006">FIG. 4</figref>;

0023<figref idref="f0006">FIG. 6</figref> is a diagram of a sub-matrix of a sparse parity check matrix, wherein the sub-matrix contains parity check values restricted to the lower triangular region, according to an embodiment of the present invention;

0024<figref idref="f0007">FIG. 7</figref> is a graph of performance of the LDPC codes at the various code rates and modulation schemes supported by the transmitter of <figref idref="f0002">FIG. 2B</figref>;

0025<figref idref="f0008">FIG. 8</figref> is a graph of performance of the short LDPC codes at the various code rates supported by the transmitter of <figref idref="f0002">FIG. 2B</figref>; and

0026<figref idref="f0009">FIG. 9</figref> is a diagram of a computer system that can perform the LDPC encoding process, in accordance with embodiments of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

0027A system, method, and software for efficiently encoding short frame length Low Density Parity Check (LDPC) codes are described. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It is apparent, however, to one skilled in the art that the present invention may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the present invention.

0028<figref idref="f0001">FIG. 1</figref> is a diagram of a communications system configured to utilize Low Density Parity Check (LDPC) codes, according to an embodiment of the present invention. A digital communications system 100 includes a transmitter 101 that generates signal waveforms across a communication channel 103 to a receiver 105. In this discrete communications system 100, the transmitter 101 has a message source that produces a discrete set of possible messages; each of the possible messages has a corresponding signal waveform. These signal waveforms are attenuated, or otherwise altered, by communications channel 103. To combat the noise channel 103, LDPC codes are utilized.

0029By way of example, the channel 103 is a satellite link serving satellite terminals (e.g., Very Small Aperture Terminals (VSATs)) in support of broadband satellite applications. Such applications include satellite broadcasting and interactive services (and compliant with the Digital Video Broadcast (DVB) - S2 standard). The Digital Video Broadcasting via Satellite (DVB-S) standard has been widely adopted worldwide to provide, for instance, digital satellite television programming.

0030The LDPC codes that are generated by the transmitter 101 enable high speed implementation without incurring any performance loss. These structured LDPC codes output from the transmitter 101 avoid assignment of a small number of check nodes to the bit nodes already vulnerable to channel errors by virtue of the modulation scheme (e.g., 8-PSK).

0031Such LDPC codes have a parallelizable decoding algorithm (unlike turbo codes), which advantageously involves simple operations such as addition, comparison and table look-up. Moreover, carefully designed LDPC codes do not exhibit any sign of error floor.

0032According to one embodiment of the present invention, the transmitter 101 generates, using a relatively simple encoding technique, LDPC codes based on parity check matrices (which facilitate efficient memory access during decoding) to communicate with the receiver 105. The transmitter 101 employs LDPC codes that can outperform concatenated turbo+RS (Reed-Solomon) codes, provided the block length is sufficiently large.

0033<figref idref="f0002">FIGs. 2A and 2B</figref> are diagrams of exemplary LDPC encoders deployed in the transmitter of <figref idref="f0001">FIG. 1</figref>. As seen in <figref idref="f0002">FIG. 2A</figref>, a transmitter 200 is equipped with an LDPC encoder 203 that accepts input from an information source 201 and outputs coded stream of higher redundancy suitable for error correction processing at the receiver 105. The information source 201 generates k signals from a discrete alphabet, X. LDPC codes are specified with parity check matrices. On the other hand, encoding LDPC codes require, in general, specifying the generator matrices. Even though it is possible to obtain generator matrices from parity check matrices using Gaussian elimination, the resulting matrix is no longer sparse and storing a large generator matrix can be complex.

0034The encoder 203 generates signals from alphabet <i>Y</i> to a modulator 205 using a simple encoding technique that makes use of only the parity check matrix by imposing structure onto the parity check matrix. Specifically, a restriction is placed on the parity check matrix by constraining certain portion of the matrix to be triangular. The construction of such a parity check matrix is described more fully below in <figref idref="f0006">FIG. 6</figref>. Such a restriction results in negligible performance loss, and therefore, constitutes an attractive trade-off.

0035The modulator 205 maps the encoded messages from encoder 203 to signal waveforms that are transmitted to a transmit antenna 207, which emits these waveforms over the communication channel 103. Accordingly, the encoded messages are modulated and distributed to a transmit antenna 207. The transmissions from the transmit antenna 207 propagate to a receiver (shown in <figref idref="f0005">FIG. 3</figref>), as discussed below.

0036<figref idref="f0002">FIG. 2B</figref> shows an LDPC encoder utilized with a Bose Chaudhuri Hocquenghem (BCH) encoder and a cyclic redundancy check (CRC) encoder, according to one embodiment of the present invention. Under this scenario, the codes generated by the LDPC encoder 203, along with the CRC encoder 209 and the BCH encoder 211, have a concatenated outer BCH code and inner low density parity check (LDPC) code. Furthermore, error detection is achieved using cyclic redundancy check (CRC) codes. The CRC encoder 209, in an exemplary embodiment, encodes using an 8-bit CRC code with generator polynomial (x⁵+x⁴+x³+x²+1)(x²+x+1)(x+1). The CRC code is output to the BCH encoder 211.

0037The LDPC encoder 203 systematically encodes an information block of size <i>k_ldpc, i =</i> (<i>i</i>₀<i>,i</i>₁<i>,..., i</i>_{<i>k_ldpc</i>-1}) onto a codeword of size <i>n_ldpc</i>, <i>c</i>=(<i>i</i>₀,<i>i</i>₁,..., i_{k<sub2>ldcp</sub2>-1}, <i>p</i>₀, <i>p</i>₁,... <i>p</i>_{<i>n_ldcp</i>-<i>k_ldcp</i>-1}) The transmission of the codeword starts in the given order from i₀ and ends with <i>p</i>_{<i>n _ldpc</i>-<i>k_ldpc</i>-1}. LDPC code parameters (<i>n_ldpc k_ldpc</i>) are given in Table 1 below. <tables id="tabl0001" num="0001"><table frame="all"><title>Table 1</title><tgroup cols="3"><colspec colnum="1" colname="col1" colwidth="22mm" /><colspec colnum="2" colname="col2" colwidth="56mm" /><colspec colnum="3" colname="col3" colwidth="53mm" /><thead><row><entry namest="col1" nameend="col3" align="center" valign="top"><b>LDPC Code Parameters</b> (<i>n_ldpc, k_ldpc</i>)</entry></row><row><entry align="center" valign="top"><b>Code Rate</b></entry><entry align="center" valign="top"><b>LDPC Uncoded Block Length</b><i>k_ldpc</i></entry><entry align="center" valign="top"><b>LDPC Coded Block Length</b><i>n_ldpc</i></entry></row></thead><tbody><row><entry align="center">1/2</entry><entry align="center">32400</entry><entry align="center">64800</entry></row><row><entry align="center">2/3</entry><entry align="center">43200</entry><entry align="center">64800</entry></row><row><entry align="center">3/4</entry><entry align="center">48600</entry><entry align="center">64800</entry></row><row><entry align="center">4/5</entry><entry align="center">51840</entry><entry align="center">64800</entry></row><row><entry align="center">5/6</entry><entry align="center">54000</entry><entry align="center">64800</entry></row><row><entry align="center">3/5</entry><entry align="center">38880</entry><entry align="center">64800</entry></row><row><entry align="center">8/9</entry><entry align="center">57600</entry><entry align="center">64800</entry></row></tbody></tgroup></table></tables>

0038The task of the LDPC encoder 203 is to determine <i>n_ldpc - k_ldpc</i> parity bits (<i>p</i>₀<i>, p</i>₁<i>,...,p</i>_{<i>n_ldpc</i>-<i>k_ldpc</i>-1}) for every block of <i>k_ldpc</i> information bits, (<i>i</i>₀, <i>i</i>₁ ,...,<i>i</i>_{<i>k_ldpc</i>-1}). The procedure is as follows. First, the parity bits are initialized; <i>p</i>₀ = <i>p</i>₁ = <i>p</i>₂ = ... = <i>p_{n<sub2>ldpc</sub2>-k<sub2>ldpc</sub2>-1}</i> = 0. The first information bit, <i>i</i>₀, are accumulated at parity bit addresses specified in the first row of Tables 2 - 8. For example, for rate 2/3 (Table 4), the following results: <ul id="ul0001" list-style="none" compact="compact"><li><i>p</i>₀ = <i>p</i>₀ ⊕ <i>i</i>₀</li><li><i>p</i>₁₀₄₉₁ = <i>p</i>₁₀₄₉₁ ⊕ <i>i</i>₀</li><li><i>p</i>₁₆₀₄₃ = <i>p</i>₁₆₀₄₃ ⊕ <i>i</i>₀</li><li><i>p</i>₅₀₆ = <i>p</i>₅₀₆ ⊕ <i>i</i>₀</li><li><i>p</i>₁₂₈₂₆ = <i>p</i>₁₂₈₂₆ ⊕ <i>i</i>₀</li><li><i>p</i>₈₀₆₅ = <i>p</i>₈₀₆₅ ⊕ <i>i</i>₀</li><li><i>p</i>₈₂₂₆ = <i>p</i>₈₂₂₆ ⊕ <i>i</i>₀</li><li><i>p</i>₂₇₆₇ = <i>p</i>₂₇₆₇ ⊕ <i>i</i>₀</li><li><i>p</i>₂₄₀ = <i>p</i>₂₄₀ ⊕ <i>i</i>₀</li><li><i>p</i>₁₈₆₇₃ = <i>p</i>₁₈₆₇₃ = ⊕ <i>i</i>₀</li><li><i>p</i>₉₂₇₉ = <i>p</i>₉₂₇₉ ⊕ <i>i</i>₀</li><li><i>p</i>₁₀₅₇₉ = <i>p</i>₁₀₅₇₉ ⊕ <i>i</i>₀</li><li><i>p</i>₂₀₉₂₈ = <i>p</i>₂₀₉₂₈ ⊕ <i>i</i>₀</li></ul>

(All additions are in GF(2)).

0039Then, for the next 359 information bits, <i>i_m</i>,<i>m</i> = 1,2,...,359 , these bits are accumulated at parity bit addresses {<i>x</i> + <i>m</i> mod 360 × <i>q</i>} mod(<i>n_ldpc - k_ldpc</i>), where <i>x</i> denotes the address of the parity bit accumulator corresponding to the first bit <i>i</i>₀ , and <i>q</i> is a code rate dependent constant specified in Table 9. Continuing with the example, <i>q</i> = 60 for rate 2/3. By way of example, for information bit i₁ the following operations are performed: <ul id="ul0002" list-style="none" compact="compact"><li><i>p</i>₆₀ = <i>p</i>₆₀ ⊕<i>i</i>₁</li><li><i>p</i>₁₀₅₅₁ = <i>p</i>₁₀₅₅₁ ⊕ <i>i</i>₁</li><li><i>p</i>₁₆₁₀₃ = <i>p</i>₁₆₁₀₃ ⊕ <i>i</i>₁</li><li><i>p</i>₅₆₆ = <i>p</i>₅₆₆ ⊕ <i>i</i>₁</li><li><i>p</i>₁₂₈₈₆ = <i>p</i>₁₂₈₈₆ ⊕ <i>i</i>₁</li><li><i>p</i>₈₁₂₅ = <i>p</i>₈₁₂₅ ⊕ <i>i</i>₁</li><li><i>p</i>₈₂₈₆ = <i>p</i>₈₂₈₆ ⊕ <i>i</i>₁</li><li><i>p</i>₂₈₂₇ = <i>p</i>₂₈₂₇ ⊕ <i>i</i>₁</li><li><i>p</i>₃₀₀ = <i>p</i>₃₀₀ ⊕ <i>i</i>₁</li><li><i>p</i>₁₈₇₃₃ = <i>p</i>₁₈₇₃₃ ⊕ <i>i</i>₁</li><li><i>p</i>₉₃₃₉ = <i>p</i>₉₃₃₉ ⊕ <i>i</i>₁</li><li><i>p</i>₁₀₆₃₉ = <i>p</i>₁₀₆₃₉ ⊕ <i>i</i>₁</li><li><i>p</i>₂₀₉₈₈ = <i>p</i>₂₀₉₈₈ ⊕ <i>i</i>₁</li></ul>

0040For the 361^st information bit <i>i</i>₃₆₀, the addresses of the parity bit accumulators are given in the second row of the Tables 2 - 8. In a similar manner the addresses of the parity bit accumulators for the following 359 information bits <i>i_m, m</i> = 361,362,...,719 are obtained using the formula {<i>x</i> + <i>m</i> mod 360 × <i>q</i>} <i>mod(n_ldpc - k_ldpc),</i> where <i>x</i> denotes the address of the parity bit accumulator corresponding to the information bit <i>i</i>₃₆₀, i.e., the entries in the second row of the Tables 2 - 8. In a similar manner, for every group of 360 new information bits, a new row from Tables 2 - 8 are used to find the addresses of the parity bit accumulators.

0041Addresses of parity bit accumulators are given in Tables 2 - 8. <tables id="tabl0002" num="0002"><table frame="all"><title>Table 2</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="73mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 1/2)</b></entry></row></thead><tbody><row rowsep="0"><entry>15 5604 5754 7705 4356 6844 8186 4014</entry></row><row rowsep="0"><entry>16 5341 2456 6053 4571 5034 8521 1858</entry></row><row rowsep="0"><entry>17 5207 8819 4926 8482 7518 8225 2585</entry></row><row rowsep="0"><entry>18 4948 1285 6825 8840 3454 8255 3137</entry></row><row rowsep="0"><entry>19 672 263 6959 5970 2556 1273 6091</entry></row><row rowsep="0"><entry>20 712 2386 6354 4061 1062 5045 5158</entry></row><row rowsep="0"><entry>21 2543 5748 4822 2348 3089 6328 5876</entry></row><row rowsep="0"><entry>22 926 5701 269 3693 2438 3190 3507</entry></row><row rowsep="0"><entry>23 2802 4520 3577 5324 1091 4667 4449</entry></row><row rowsep="0"><entry>24 5140 2003 1263 4742 6497 1185 6202</entry></row><row rowsep="0"><entry>0 4046 6934</entry></row><row rowsep="0"><entry>1 2855 66</entry></row><row rowsep="0"><entry>2 6694 212</entry></row><row rowsep="0"><entry>3 3439 1158</entry></row><row rowsep="0"><entry>4 3850 4422</entry></row><row rowsep="0"><entry>5 5924 290</entry></row><row rowsep="0"><entry>6 1467 4049</entry></row><row rowsep="0"><entry>7 7820 2242</entry></row><row rowsep="0"><entry>8 4606 3080</entry></row><row rowsep="0"><entry>9 4633 7877</entry></row><row rowsep="0"><entry>10 3884 6868</entry></row><row rowsep="0"><entry>11 8935 4996</entry></row><row rowsep="0"><entry>12 3028 764</entry></row><row rowsep="0"><entry>13 5988 1057</entry></row><row><entry>14 7411 3450</entry></row></tbody></tgroup></table></tables><tables id="tabl0003" num="0003"><table frame="all"><title>Table 3</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="96mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 3/5)</b></entry></row></thead><tbody><row rowsep="0"><entry>2765 5713 6426 3596 1374 4811 2182 544 3394 2840 4310 771</entry></row><row rowsep="0"><entry>4951 211 2208 723 1246 2928 398 5739 265 5601 5993 2615</entry></row><row rowsep="0"><entry>210 4730 5777 3096 4282 6238 4939 1119 6463 5298 6320 4016</entry></row><row rowsep="0"><entry>4167 2063 4757 3157 5664 3956 6045 563 4284 2441 3412 6334</entry></row><row rowsep="0"><entry>4201 2428 4474 59 1721 736 2997 428 3807 1513 4732 6195</entry></row><row rowsep="0"><entry>2670 3081 5139 3736 1999 5889 4362 3806 4534 5409 6384 5809</entry></row><row rowsep="0"><entry>5516 1622 2906 3285 1257 5797 3816 817 875 2311 3543 1205</entry></row><row rowsep="0"><entry>4244 2184 5415 1705 5642 4886 2333 287 1848 1121 3595 6022</entry></row><row rowsep="0"><entry>2142 2830 4069 5654 1295 2951 3919 1356 884 1786 396 4738</entry></row><row rowsep="0"><entry>0 2161 2653</entry></row><row rowsep="0"><entry>1 1380 1461</entry></row><row rowsep="0"><entry>2 2502 3707</entry></row><row rowsep="0"><entry>3 3971 1057</entry></row><row rowsep="0"><entry>4 5985 6062</entry></row><row rowsep="0"><entry>5 1733 6028</entry></row><row rowsep="0"><entry>6 3786 1936</entry></row><row rowsep="0"><entry>7 4292 956</entry></row><row rowsep="0"><entry>8 5692 3417</entry></row><row rowsep="0"><entry>9 266 4878</entry></row><row rowsep="0"><entry>10 4913 3247</entry></row><row rowsep="0"><entry>11 4763 3937</entry></row><row rowsep="0"><entry>12 3590 2903</entry></row><row rowsep="0"><entry>13 2566 4215</entry></row><row rowsep="0"><entry>14 5208 4707</entry></row><row rowsep="0"><entry>15 3940 3388</entry></row><row rowsep="0"><entry>16 5109 4556</entry></row><row><entry>17 4908 4177</entry></row></tbody></tgroup></table></tables><tables id="tabl0004" num="0004"><table frame="all"><title>Table 4</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="97mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 2/3)</b></entry></row></thead><tbody><row rowsep="0"><entry>0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622</entry></row><row rowsep="0"><entry>1 122 1516 3448 2880 1407 1847 3799 3529 373 971 4358 3108</entry></row><row rowsep="0"><entry>2 259 3399 929 2650 864 3996 3833 107 5287 164 3125 2350</entry></row><row rowsep="0"><entry>3 342 3529</entry></row><row rowsep="0"><entry>4 4198 2147</entry></row><row rowsep="0"><entry>5 1880 4836</entry></row><row rowsep="0"><entry>6 3864 4910</entry></row><row rowsep="0"><entry>7 243 1542</entry></row><row rowsep="0"><entry>8 3011 1436</entry></row><row rowsep="0"><entry>9 2167 2512</entry></row><row rowsep="0"><entry>10 4606 1003</entry></row><row rowsep="0"><entry>11 2835 705</entry></row><row rowsep="0"><entry>12 3426 2365</entry></row><row rowsep="0"><entry>13 3848 2474</entry></row><row rowsep="0"><entry>14 1360 1743</entry></row><row rowsep="0"><entry>0 1632536</entry></row><row rowsep="0"><entry>1 2583 1 180</entry></row><row rowsep="0"><entry>2 1542 509</entry></row><row rowsep="0"><entry>3 4418 1005</entry></row><row rowsep="0"><entry>4 5212 51 17</entry></row><row rowsep="0"><entry>5 21 55 2922</entry></row><row rowsep="0"><entry>6 347 2696</entry></row><row rowsep="0"><entry>7 226 4296</entry></row><row rowsep="0"><entry>8 1560 487</entry></row><row rowsep="0"><entry>9 3926 1640</entry></row><row rowsep="0"><entry>10 1492928</entry></row><row rowsep="0"><entry>11 2364 563</entry></row><row rowsep="0"><entry>12 635 688</entry></row><row rowsep="0"><entry>13 231 1684</entry></row><row><entry>14 1129 3894</entry></row></tbody></tgroup></table></tables><tables id="tabl0005" num="0005"><table frame="all"><title>Table 5</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="89mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 3/4)</b></entry></row></thead><tbody><row rowsep="0"><entry>0 3576 1576 3860 1290 4199 815 2978 3428 3639 2181 1750</entry></row><row rowsep="0"><entry>1 1960 2307 2697 4240 3238 3555 265 379 128 2911 3653</entry></row><row rowsep="0"><entry>2 99 1389 3627 830 2448 1185 3034 2946 2598 1960 1032</entry></row><row rowsep="0"><entry>3 3198 478 4207 1481 1009 2616 1924 3437 554 683 1801</entry></row><row rowsep="0"><entry>4 2681 2135</entry></row><row rowsep="0"><entry>5 3107 4027</entry></row><row rowsep="0"><entry>6 2637 3373</entry></row><row rowsep="0"><entry>7 3830 3449</entry></row><row rowsep="0"><entry>8 4129 2060</entry></row><row rowsep="0"><entry>9 4184 2742</entry></row><row rowsep="0"><entry>10 3946 1070</entry></row><row rowsep="0"><entry>11 2239 984</entry></row><row rowsep="0"><entry>0 1458 3031</entry></row><row rowsep="0"><entry>1 3003 1328</entry></row><row rowsep="0"><entry>2 1137 1716</entry></row><row rowsep="0"><entry>3 132 3725</entry></row><row rowsep="0"><entry>4 1817 638</entry></row><row rowsep="0"><entry>5 1774 3447</entry></row><row rowsep="0"><entry>6 3632 1257</entry></row><row rowsep="0"><entry>7 542 3694</entry></row><row rowsep="0"><entry>8 1015 1945</entry></row><row rowsep="0"><entry>9 1948 412</entry></row><row rowsep="0"><entry>10 995 2238</entry></row><row rowsep="0"><entry>11 4141 1907</entry></row><row rowsep="0"><entry>0 2480 3079</entry></row><row rowsep="0"><entry>1 3021 1088</entry></row><row rowsep="0"><entry>2 713 1379</entry></row><row rowsep="0"><entry>3 997 3903</entry></row><row rowsep="0"><entry>4 2323 3361</entry></row><row rowsep="0"><entry>5 1110 986</entry></row><row rowsep="0"><entry>6 2532 142</entry></row><row rowsep="0"><entry>7 1690 2405</entry></row><row rowsep="0"><entry>8 1298 1881</entry></row><row rowsep="0"><entry>9 615 174</entry></row><row rowsep="0"><entry>10 1648 3112</entry></row><row><entry>11 14152808</entry></row></tbody></tgroup></table></tables><tables id="tabl0006" num="0006"><table frame="all"><title>Table 6</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="81mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 4/5)</b></entry></row></thead><tbody><row rowsep="0"><entry>0 2319 198 789 902 1314 2806 143 2088 3525 1972</entry></row><row rowsep="0"><entry>1 1285 1816 2194 103732935093417229424383111</entry></row><row rowsep="0"><entry>2 704 1967 1228 1486 842 3400 1075 2776 3473 3327</entry></row><row rowsep="0"><entry>3 1501 63 3235 2253 661 2968 1819 252 360 2174</entry></row><row rowsep="0"><entry>4 3040 2231 2531 2690 1527 2605 2130 791 1786 1699</entry></row><row rowsep="0"><entry>5 896 1565</entry></row><row rowsep="0"><entry>6 2493 184</entry></row><row rowsep="0"><entry>7 212 3210</entry></row><row rowsep="0"><entry>8 727 1339</entry></row><row rowsep="0"><entry>9 3428 612</entry></row><row rowsep="0"><entry>0 2663 1947</entry></row><row rowsep="0"><entry>1 230 2695</entry></row><row rowsep="0"><entry>2 2025 2794</entry></row><row rowsep="0"><entry>3 3039 283</entry></row><row rowsep="0"><entry>4 862 2889</entry></row><row rowsep="0"><entry>5 376 2110</entry></row><row rowsep="0"><entry>6 2034 2286</entry></row><row rowsep="0"><entry>7 951 2068</entry></row><row rowsep="0"><entry>8 3108 3542</entry></row><row rowsep="0"><entry>9 307 1421</entry></row><row rowsep="0"><entry>0 2272 1197</entry></row><row rowsep="0"><entry>1 1800 3280</entry></row><row rowsep="0"><entry>2 331 2308</entry></row><row rowsep="0"><entry>3 465 2552</entry></row><row rowsep="0"><entry>4 1038 2479</entry></row><row rowsep="0"><entry>5 1383 343</entry></row><row rowsep="0"><entry>6 94 236</entry></row><row rowsep="0"><entry>7 2619 121</entry></row><row rowsep="0"><entry>8 1497 2774</entry></row><row rowsep="0"><entry>9 2116 1855</entry></row><row rowsep="0"><entry>0 722 1584</entry></row><row rowsep="0"><entry>1 2767 1881</entry></row><row rowsep="0"><entry>2 2701 1610</entry></row><row rowsep="0"><entry>3 3283 1732</entry></row><row rowsep="0"><entry>4 168 1099</entry></row><row rowsep="0"><entry>5 3074 243</entry></row><row rowsep="0"><entry>6 3460 94S</entry></row><row rowsep="0"><entry>7 2049 1746</entry></row><row rowsep="0"><entry>8 566 1427</entry></row><row><entry>9 3545 1168</entry></row></tbody></tgroup></table></tables><tables id="tabl0007" num="0007"><table frame="all"><title>Table 7</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="94mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 5/6)</b></entry></row></thead><tbody><row rowsep="0"><entry>0 1752 825 2637 402 2730 1838 1945 2490 1627 2137 1202 2188</entry></row><row rowsep="0"><entry>1 1501 1900 2147 1967 1757 2803 555 2020 333 2266 2577 1399</entry></row><row rowsep="0"><entry>2 1675 799 422 488 945 1536 2288 999 1727 2214 1923 2152</entry></row><row rowsep="0"><entry>3 2409 499 1481 908 559 716 1270 333 2508 2264 1702 2805</entry></row><row rowsep="0"><entry>4 2447 1926</entry></row><row rowsep="0"><entry>5 414 1224</entry></row><row rowsep="0"><entry>6 2114 842</entry></row><row rowsep="0"><entry>7 212 573</entry></row><row rowsep="0"><entry>0 2383 2112</entry></row><row rowsep="0"><entry>1 2286 2348</entry></row><row rowsep="0"><entry>2 545 819</entry></row><row rowsep="0"><entry>3 1264 143</entry></row><row rowsep="0"><entry>4 1701 2258</entry></row><row rowsep="0"><entry>5 964 166</entry></row><row rowsep="0"><entry>6 114 2413</entry></row><row rowsep="0"><entry>7 2243 81</entry></row><row rowsep="0"><entry>0 1245 1581</entry></row><row rowsep="0"><entry>1 775 169</entry></row><row rowsep="0"><entry>2 1696 1104</entry></row><row rowsep="0"><entry>3 1914 2831</entry></row><row rowsep="0"><entry>4 532 1450</entry></row><row rowsep="0"><entry>5 91 974</entry></row><row rowsep="0"><entry>6 497 2228</entry></row><row rowsep="0"><entry>7 2326 1579</entry></row><row rowsep="0"><entry>0 2482 256</entry></row><row rowsep="0"><entry>1 1117 1261</entry></row><row rowsep="0"><entry>2 1257 1658</entry></row><row rowsep="0"><entry>3 1478 1225</entry></row><row rowsep="0"><entry>4 25 11 980</entry></row><row rowsep="0"><entry>5 2320 2675</entry></row><row rowsep="0"><entry>6 435 1278</entry></row><row rowsep="0"><entry>7 228 503</entry></row><row rowsep="0"><entry>0 1885 2369</entry></row><row rowsep="0"><entry>1 57 483</entry></row><row rowsep="0"><entry>2 838 1050</entry></row><row rowsep="0"><entry>3 1231 1990</entry></row><row rowsep="0"><entry>4 1738 68</entry></row><row rowsep="0"><entry>5 2392 951</entry></row><row rowsep="0"><entry>6 163 645</entry></row><row><entry>7 2644 1704</entry></row></tbody></tgroup></table></tables><tables id="tabl0008" num="0008"><table frame="all"><title>Table 8</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="73mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 8/9)</b></entry></row></thead><tbody><row rowsep="0"><entry>0 1558 712 805</entry></row><row rowsep="0"><entry>1 1450 873 1337</entry></row><row rowsep="0"><entry>2 1741 1129 1184</entry></row><row rowsep="0"><entry>3 294 806 1566</entry></row><row rowsep="0"><entry>4 482 605 923</entry></row><row rowsep="0"><entry>0 926 1578</entry></row><row rowsep="0"><entry>1 777 1374</entry></row><row rowsep="0"><entry>2 608 151</entry></row><row rowsep="0"><entry>3 1195 210</entry></row><row rowsep="0"><entry>4 1484692</entry></row><row rowsep="0"><entry>0 427 488</entry></row><row rowsep="0"><entry>1 828 1124</entry></row><row rowsep="0"><entry>2 874 1366</entry></row><row rowsep="0"><entry>3 1500 835</entry></row><row rowsep="0"><entry>4 1496 502</entry></row><row rowsep="0"><entry>0 1006 1701</entry></row><row rowsep="0"><entry>1 115597</entry></row><row rowsep="0"><entry>2 657 1403</entry></row><row rowsep="0"><entry>3 1453 624</entry></row><row rowsep="0"><entry>4 429 1495</entry></row><row rowsep="0"><entry>0 809 385</entry></row><row rowsep="0"><entry>1 367 151</entry></row><row rowsep="0"><entry>2 1323 202</entry></row><row rowsep="0"><entry>3 960 318</entry></row><row rowsep="0"><entry>4 1451 1039</entry></row><row rowsep="0"><entry>0 1098 1722</entry></row><row rowsep="0"><entry>1 1015 1428</entry></row><row rowsep="0"><entry>2 1261 1564</entry></row><row rowsep="0"><entry>3 544 1190</entry></row><row rowsep="0"><entry>4 1472 1246</entry></row><row rowsep="0"><entry>0 508 630</entry></row><row rowsep="0"><entry>1 421 1704</entry></row><row rowsep="0"><entry>2 284 898</entry></row><row rowsep="0"><entry>3 392 577</entry></row><row rowsep="0"><entry>4 1155 556</entry></row><row rowsep="0"><entry>0 631 1000</entry></row><row rowsep="0"><entry>1 732 1368</entry></row><row rowsep="0"><entry>2 1328 329</entry></row><row rowsep="0"><entry>3 1515 506</entry></row><row><entry>4 1104 1172</entry></row></tbody></tgroup></table></tables>

0042After all of the information bits are exhausted, the final parity bits are obtained as follows. First, the following operations are performed, starting with <i>i</i> = 1 <maths id="math0001" num=""><math display="block"><msub><mi mathvariant="italic">p</mi><mi mathvariant="italic">i</mi></msub><mo>=</mo><msub><mi mathvariant="italic">p</mi><mi mathvariant="italic">i</mi></msub><mo>⊕</mo><msub><mi mathvariant="italic">p</mi><mrow><mi mathvariant="italic">i</mi><mo>-</mo><mn /><mo>⁢</mo><mn>1</mn><mo>⁢</mo><mn /></mrow></msub><mo>,</mo><mspace width="1em" /><mi mathvariant="italic">i</mi><mo>=</mo><mn>1</mn><mo>,</mo><mn>2</mn><mo>,</mo><mn>...</mn><mo>,</mo><msub><mi mathvariant="italic">n</mi><mi mathvariant="italic">ldpc</mi></msub><mo>-</mo><msub><mi mathvariant="italic">k</mi><mi mathvariant="italic">ldpc</mi></msub><mo>-</mo><mn>1.</mn></math><img file="EP1513258B1_D0001.tif" /></maths> Final content of <i>p_i , i</i> = 0,1,<i>..,n_ldpc -k_ldpc</i> -1 is equal to the parity bit <i>p_i</i>. <tables id="tabl0009" num="0009"><table frame="all"><title>Table 9</title><tgroup cols="2"><colspec colnum="1" colname="col1" colwidth="20mm" /><colspec colnum="2" colname="col2" colwidth="10mm" /><thead><row><entry align="center" valign="top"><b>Code Rate</b></entry><entry align="center" valign="top"><b><i>q</i></b></entry></row></thead><tbody><row><entry align="center">2/3</entry><entry align="center">60</entry></row><row><entry align="center">5/6</entry><entry align="center">30</entry></row><row><entry align="center">1/2</entry><entry align="center">90</entry></row><row><entry align="center">3/4</entry><entry align="center">45</entry></row><row><entry align="center">4/5</entry><entry align="center">36</entry></row><row><entry align="center">3/5</entry><entry align="center">72</entry></row><row><entry align="center">8/9</entry><entry align="center">20</entry></row></tbody></tgroup></table></tables>

0043The generator polynomial of the <i>t</i> error correcting BCH encoder 211 is obtained by multiplying the first t polynomials in the following list of Table 10: <tables id="tabl0010" num="0010"><table frame="all"><title>Table 10</title><tgroup cols="2"><colspec colnum="1" colname="col1" colwidth="14mm" /><colspec colnum="2" colname="col2" colwidth="73mm" /><tbody><row><entry align="center">g₁(x)</entry><entry>1+x²+x³+x⁵+x¹⁶</entry></row><row><entry align="center">g₂(x)</entry><entry>1+x+x⁴+x⁵+x⁶+x⁸+x¹⁶</entry></row><row><entry align="center">g₃(x)</entry><entry>1+x²+x³+x⁴+x⁵+x⁷+x⁸+x⁹+x¹⁰+x¹¹+x¹⁶</entry></row><row><entry align="center">g₄(x)</entry><entry>1+x²+x⁴+x⁶+x⁹+x¹¹+x¹²+x¹⁴+x¹⁶</entry></row><row><entry align="center">g₅(x)</entry><entry>1+x+x²+x³+x⁵+x⁸+x⁹+x¹⁰+x¹¹+x¹²+x¹⁶</entry></row><row><entry align="center">g₆(x)</entry><entry>1+x²+x⁴+x⁵+x⁷+x⁸+x⁹+x¹⁰+x¹²+x¹³+x¹⁴+x¹⁵+x¹⁶</entry></row><row><entry align="center">g₇(x)</entry><entry>1+x²+x⁵+x⁶+x⁸+x⁹+x¹⁰+x¹¹+x¹³+x¹⁵+x¹⁶</entry></row><row><entry align="center">g₈(x)</entry><entry>1+x+x²+x⁵+x⁶+x⁸+x⁹+x¹²+x¹³+x¹⁴+x¹⁶</entry></row><row><entry align="center">g₉(x)</entry><entry>1+x⁵+x⁷+x⁹+x¹⁰+x¹¹+x¹⁶</entry></row><row><entry align="center">g₁₀(x)</entry><entry>1+x+x²+x⁵+x⁷+x⁸+x¹⁰+x¹²+x¹³+x¹⁴+x¹⁶</entry></row><row><entry align="center">g₁₁(x)</entry><entry>1 +x²+x³+x⁵+x⁹+x¹¹+x¹²+x¹³+x¹⁶</entry></row><row><entry align="center">g₁₂(x)</entry><entry>1+x+x⁵+x⁶+x⁷+x⁹+x¹¹+x¹²+x¹⁶</entry></row></tbody></tgroup></table></tables>

0044BCH encoding of information bits <i>m</i> = (<i>m</i>_{<i>k^bch</i>-1}<i>, m</i>_{k<sub2>bch</sub2>-2}<i>, ..., m</i>₁<i>, m</i>₀) onto a codeword <i>c</i> = <i>m</i>_{<i>k_bch</i>-1}<i>, m</i>_{<i>k_bch</i>-2}, ..., <i>m</i>₁, <i>m</i>₀<i>, d</i>_{<i>n^bch</i>-<i>k_bch</i>-1}<i>, d</i>_{<i>n_bch</i>-<i>k_bch</i>-2}<i>, ..., d</i>₁<i>, d</i>₀) is achieved as follows. The message polynomial <i>m</i>(<i>x</i>) = <i>m</i>_{<i>k_bch</i>-1}<i>x</i>^{<i>k^bch</i>-1} + <i>m</i>_{<i>k_bch</i>-2}<i>x</i>^{<i>k^bch</i>-2} +...+ <i>m</i>₁<i>x</i>+<i>m</i>₀ is multiplied by <i>x</i>^{<i>n^bch</i>-<i>k^bch</i>} Next, <i>x</i>^{<i>n^bch</i>-}<i>^{k<sup2>bch</sup2>} m</i>(<i>x</i>) divided by <i>g</i>(<i>x</i>). With <i>d</i>(<i>x</i>) = <i>d</i>_{<i>n_bch</i>-<i>k_bch</i>-1}x^{<i>n^bch</i>-<i>k^bch</i>-1} +...+ <i>d</i>₁<i>x</i>+<i>d</i>₀ as the remainder, the codeword polynomial is set as follows: <i>c</i>(<i>x</i>) = <i>x</i>^{<i>n^bch</i>-}<i>^{k<sup2>bch</sup2>} m</i>(<i>x</i>) + <i>d</i>(<i>x</i>).

0045As seen in <figref idref="f0002">FIG. 2B</figref>, the LDPC encoder 203 outputs to a bit interleaver 213. By way of example, 8-PSK, 16-APSK, and 32-APSK modulation formats are utilized. Data is serially written into the interleaver column-wise (from the top to the bottom), and serially read out row-wise (from the left to the right). However, in the case of code rate 3/5 with 8-PSK, it has been determined that reading the data out from the right to the left, instead of left to right, yields better performance (as illustrated in <figref idref="f0007">FIG. 7</figref>).

0046The configuration of the block interleaver for each modulation format is specified in Table 11. <tables id="tabl0011" num="0011"><table frame="all"><title>Table 11</title><tgroup cols="4"><colspec colnum="1" colname="col1" colwidth="21mm" /><colspec colnum="2" colname="col2" colwidth="29mm" /><colspec colnum="3" colname="col3" colwidth="29mm" /><colspec colnum="4" colname="col4" colwidth="18mm" /><tbody><row><entry namest="col1" nameend="col4" align="center"><b>Bit Interleaver Structure</b></entry></row><row rowsep="0"><entry>Modulation</entry><entry>Rows</entry><entry>Rows</entry><entry>Columns</entry></row><row><entry /><entry>(for <i>n_ldpc</i>=64800)</entry><entry>(for <i>n_ldpc</i>=16200)</entry><entry /></row><row><entry>8-PSK</entry><entry>21600</entry><entry>5400</entry><entry>3</entry></row><row><entry>16-APSK</entry><entry>16200</entry><entry>4050</entry><entry>4</entry></row><row><entry>32-APSK</entry><entry>12960</entry><entry>3240</entry><entry>5</entry></row></tbody></tgroup></table></tables>

0047<figref idref="f0003">FIGs. 2C</figref> and <figref idref="f0004">2D</figref> are flowcharts of the encoding process of the LDPC encoder of <figref idref="f0002">FIG. 2B</figref> for generating short frame length LDPC codes, according to an embodiment of the present invention. In step 211, information bits are received and processed to the chain of encoders 209, 211, and 203. Consequently, the LDPC encoder 203 generates LDPC codes with outer BCH codes based on the received information bits, as in step 223. The codes also contain the CRC code. In step 225, the coded bits are altered by the bit interleaver 213, as described above. Next, the LDPC codes are represented by signals that are modulated, per step 227, for transmission over the channel 103, which in an exemplary embodiment, is a satellite link to one or more satellite terminals (step 229).

0048As discussed, <i>k_ldpc</i> bits are systematically encoded to generate <i>n_ldpc</i> bits. According to one embodiment of the present invention, <i>n_ldpc</i> is 16200 bits, which is a short block length. Given the relatively short length of such codes, LDPC codes having approximate lengths of 16200 bits or less are deemed "short" block length codes.

0049In accordance with an embodiment of the present invention, short blocks codes are generated by shortening versions of slightly longer (<i>k_m, n_m</i>) "mother" codes of block size <i>n_m</i> > 16200. As shown in <figref idref="f0004">FIG. 2D</figref>, <i>k_ldpc</i> of the BCH encoded bits are preceded by <i>k_m -k_ldpc</i> dummy zeros (per step 251). The resulting <i>k_m</i> bits are systematically encoded to generate <i>n_m</i> bits, as in step 253. The first <i>k_m -k_ldpc</i> dummy zeros are then deleted, as in step 255, and the resulting <i>n_ldpc</i> =16200 bits will be transmitted (step 257). It is noted that <i>k_m - k_ldpc = n_m n</i>_<i>ldp</i>c

0050The parameters of short frame length codes are provided in Table 12 as follows. <tables id="tabl0012" num="0012"><table frame="all"><title>Table 12</title><tgroup cols="7"><colspec colnum="1" colname="col1" colwidth="37mm" /><colspec colnum="2" colname="col2" colwidth="14mm" /><colspec colnum="3" colname="col3" colwidth="14mm" /><colspec colnum="4" colname="col4" colwidth="14mm" /><colspec colnum="5" colname="col5" colwidth="14mm" /><colspec colnum="6" colname="col6" colwidth="38mm" /><colspec colnum="7" colname="col7" colwidth="37mm" /><thead><row><entry align="center" valign="top"><b>Mother Code Rate <i>k_m</i>/<i>n_m</i></b></entry><entry align="center" valign="top"><b><i>k_ldpc</i></b></entry><entry align="center" valign="top"><b><i>k_m</i></b></entry><entry align="center" valign="top"><b><i>n_m</i></b></entry><entry align="center" valign="top"><b><i>k_bch</i></b></entry><entry align="center" valign="top"><b>BCH Correction (bits)</b></entry><entry align="center" valign="top"><b>Effective Rate <i>k_bch</i>/<i>16200</i></b></entry></row></thead><tbody><row><entry align="center">1/2</entry><entry align="center">7200</entry><entry align="center">9000</entry><entry align="center">18000</entry><entry align="center">7032</entry><entry align="center">12</entry><entry align="char" char=".">0.434</entry></row><row><entry align="center">3/5</entry><entry align="center">9720</entry><entry align="center">9720</entry><entry align="center">16200</entry><entry align="center">9552</entry><entry align="center">12</entry><entry align="char" char=".">0.589</entry></row><row><entry align="center">2/3</entry><entry align="center">10800</entry><entry align="center">10800</entry><entry align="center">16200</entry><entry align="center">10632</entry><entry align="center">12</entry><entry align="char" char=".">0.656</entry></row><row><entry align="center">3/4</entry><entry align="center">11880</entry><entry align="center">12960</entry><entry align="center">17280</entry><entry align="center">11712</entry><entry align="center">12</entry><entry align="char" char=".">0.722</entry></row><row><entry align="center">4/5</entry><entry align="center">12600</entry><entry align="center">14400</entry><entry align="center">18000</entry><entry align="center">12432</entry><entry align="center">12</entry><entry align="char" char=".">0.767</entry></row><row><entry align="center">5/6</entry><entry align="center">13320</entry><entry align="center">14400</entry><entry align="center">17280</entry><entry align="center">13152</entry><entry align="center">12</entry><entry align="char" char=".">0.811</entry></row><row><entry align="center">8/9</entry><entry align="center">14400</entry><entry align="center">14400</entry><entry align="center">16200</entry><entry align="center">14232</entry><entry align="center">12</entry><entry align="char" char=".">0.878</entry></row></tbody></tgroup></table></tables>

0051Simulations of the performance of these codes were conducted, as shown in <figref idref="f0008">FIG. 8</figref>.

0052Tables 13-15 provide other exemplary code rates, 1/3, 1/5 and 2/5 for <i>n_ldpc</i> of 16200 bits: <tables id="tabl0013" num="0013"><table frame="all"><title>Table 13</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="99mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 1/3)</b></entry></row></thead><tbody><row rowsep="0"><entry>416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 6912</entry></row><row rowsep="0"><entry>8978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 3575</entry></row><row rowsep="0"><entry>3383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 2291</entry></row><row rowsep="0"><entry>2797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 5420</entry></row><row rowsep="0"><entry>6110 855 1515 7404487949465383 1831 3441 9569 10472 4306</entry></row><row rowsep="0"><entry>1505 5682 7778</entry></row><row rowsep="0"><entry>7172 6830 6623</entry></row><row rowsep="0"><entry>7281 3941 3505</entry></row><row rowsep="0"><entry>10270 8669 914</entry></row><row rowsep="0"><entry>3622 7563 9388</entry></row><row rowsep="0"><entry>9930 5058 4554</entry></row><row rowsep="0"><entry>4844 9609 2707</entry></row><row rowsep="0"><entry>6883 3237 1714</entry></row><row rowsep="0"><entry>4768 3878 10017</entry></row><row><entry>10127 3334 8267</entry></row></tbody></tgroup></table></tables><tables id="tabl0014" num="0014"><table frame="all"><title>Table 14</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="103mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Shortened from Rate 1/5)</b></entry></row></thead><tbody><row rowsep="0"><entry>6295 9626 304 7695 4839 4936 1660 144 11203 5567 6347 12557</entry></row><row rowsep="0"><entry>10691 4988 3859 3734 3071 3494 7687 10313 5964 8069 8296 11090</entry></row><row rowsep="0"><entry>10774 3613 5208 11177 7676 3549 8746 6583 7239 12265 2674 4292</entry></row><row rowsep="0"><entry>11869 3708 5981 8718 4908 10650 6805 3334 2627 10461 9285 11120</entry></row><row rowsep="0"><entry>7844 3079 10773</entry></row><row rowsep="0"><entry>3385 10854 5747</entry></row><row rowsep="0"><entry>1360 12010 12202</entry></row><row rowsep="0"><entry>6189 4241 2343</entry></row><row><entry>9840 12726 4977</entry></row></tbody></tgroup></table></tables><tables id="tabl0015" num="0015"><table frame="all"><title>Table 5</title><tgroup cols="1" colsep="0"><colspec colnum="1" colname="col1" colwidth="96mm" colsep="1" /><thead><row><entry align="center" valign="top"><b>Address of Parity Bit Accumulators (Rate 2/5)</b></entry></row></thead><tbody><row rowsep="0"><entry>5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658</entry></row><row rowsep="0"><entry>5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016</entry></row><row rowsep="0"><entry>3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931</entry></row><row rowsep="0"><entry>4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254</entry></row><row rowsep="0"><entry>4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963</entry></row><row rowsep="0"><entry>9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134</entry></row><row rowsep="0"><entry>1652 8171 1435</entry></row><row rowsep="0"><entry>3366 6543 3745</entry></row><row rowsep="0"><entry>9286 8509 4645</entry></row><row rowsep="0"><entry>7397 5790 8972</entry></row><row rowsep="0"><entry>65974422 1799</entry></row><row rowsep="0"><entry>9276 4041 3847</entry></row><row rowsep="0"><entry>8683 7378 4946</entry></row><row rowsep="0"><entry>5348 1993 9186</entry></row><row rowsep="0"><entry>672490155646</entry></row><row rowsep="0"><entry>4502 4439 8474</entry></row><row rowsep="0"><entry>5107 7342 9442</entry></row><row><entry>1387 8910 2660</entry></row></tbody></tgroup></table></tables>

0053The above approach to designing LDPC codes, as provided in Tables 2-8 and 13-15, advantageously permits storage and retrieval of relevant information regarding partitioned groups of bit nodes and check nodes to be always placed in contiguously memory locations within memory (e.g., Random Access Memory (RAM)). Further, this enables use of a single RAM bank, thereby minimizing size of the integrated circuit. As mentioned, the above LDPC codes, can be used to variety of digital video applications, such as MPEG (Motion Pictures Expert Group) packet transmission.

0054<figref idref="f0005">FIG. 3</figref> is a diagram of an exemplary receiver in the system of <figref idref="f0001">FIG. 1</figref>. At the receiving side, a receiver 300 includes a demodulator 301 that performs demodulation of received signals from transmitter 200. These signals are received at a receive antenna 303 for demodulation. After demodulation, the received signals are forwarded to a decoder 305, which attempts to reconstruct the original source messages by generating messages, <i>X</i>', in conjunction with a bit metric generator 307. The bit metric generator 307 may exchange information with the decoder 305 back and forth (iteratively) during the decoding process. These decoding approaches are more fully described in co-pending application, entitled "Method and System for Routing in Low Density Parity Check (LDPC) Decoders," filed July 3, 2003 (Serial No. 10/613,824; Attorney Docket PD-203009). To appreciate the advantages offered by the present invention, it is instructive to examine how LDPC codes are generated, as discussed in <figref idref="f0006">FIG. 4</figref>.

0055<figref idref="f0006">FIG. 4</figref> is a diagram of a sparse parity check matrix, in accordance with an embodiment of the present invention. LDPC codes are long, linear block codes with sparse parity check matrix <i>H</i>_{(<i>n</i>-<i>k</i>)<i>xn</i>}. Typically the block length, <i>n</i>, ranges from thousands to tens of thousands of bits. For example, a parity check matrix for an LDPC code of length <i>n</i>=8 and rate ½ is shown in <figref idref="f0006">FIG. 4</figref>. The same code can be equivalently represented by the bipartite graph, per <figref idref="f0006">FIG. 5</figref>.

0056<figref idref="f0006">FIG. 5</figref> is a diagram of a bipartite graph of an LDPC code of the matrix of <figref idref="f0006">FIG. 4</figref>. Parity check equations imply that for each check node, the sum (over GF (Galois Field)(2)) of all adjacent bit nodes is equal to zero. As seen in the figure, bit nodes occupy the left side of the graph and are associated with one or more check nodes, according to a predetermined relationship. For example, corresponding to check node m₁, the following expression exists <i>n₁</i> + <i>n</i>₄ + <i>n</i>₅ + <i>n₈</i> = 0 with respect to the bit nodes.

0057Returning the receiver 303, the LDPC decoder 305 is considered a message passing decoder, whereby the decoder 305 aims to find the values of bit nodes. To accomplish this task, bit nodes and check nodes iteratively communicate with each other. The nature of this communication is described below.

0058From check nodes to bit nodes, each check node provides to an adjacent bit node an estimate ("opinion") regarding the value of that bit node based on the information coming from other adjacent bit nodes. For instance, in the above example if the sum of <i>n</i>₄, <i>n</i>₅ and <i>n</i>₈ "looks like" 0 to <i>m</i>₁ , then <i>m</i>₁, would indicate to <i>n</i>₁ that the value of <i>n</i>₁ is believed to be 0 (since <i>n</i>₁ + <i>n₄</i> + <i>n</i>₅ + <i>n</i>₈ = 0); otherwise <i>m</i>₁ indicate to <i>n</i>₁ that the value of <i>n</i>₁ is believed to be 1. Additionally, for soft decision decoding, a reliability measure is added.

0059From bit nodes to check nodes, each bit node relays to an adjacent check node an estimate about its own value based on the feedback coming from its other adjacent check nodes. In the above example <i>n</i>₁ has only two adjacent check nodes <i>m</i>₁ and <i>m</i>₃ . If the feedback coming from <i>m</i>₃ to <i>n</i>₁ indicates that the value of n₁ is probably 0, then <i>n</i>₁ would notify <i>m</i>₁ that an estimate of <i>n</i>₁ 's own value is 0. For the case in which the bit node has more than two adjacent check nodes, the bit node performs a majority vote (soft decision) on the feedback coming from its other adjacent check nodes before reporting that decision to the check node it communicates. The above process is repeated until all bit nodes are considered to be correct (i.e., all parity check equations are satisfied) or until a predetermined maximum number of iterations is reached, whereby a decoding failure is declared.

0060<figref idref="f0006">FIG. 6</figref> is a diagram of a sub-matrix of a sparse parity check matrix, wherein the sub-matrix contains parity check values restricted to the lower triangular region, according to an embodiment of the present invention. As described previously, the encoder 203 (of <figref idref="f0002">FIGs. 2A and 2B</figref>) can employ a simple encoding technique by restricting the values of the lower triangular area of the parity check matrix. According to an embodiment of the present invention, the restriction imposed on the parity check matrix is of the form: <maths id="math0002" num=""><math display="block"><msub><mi>H</mi><mrow><mfenced separators=""><mi>n</mi><mo>-</mo><mi>k</mi></mfenced><mo>⁢</mo><mi mathvariant="italic">xn</mi></mrow></msub><mo>=</mo><mfenced open="[" close="]" separators=""><msub><mi>A</mi><mrow><mfenced separators=""><mi>n</mi><mo>-</mo><mi>k</mi></mfenced><mo>⁢</mo><mi mathvariant="italic">xk</mi></mrow></msub><mo>⁢</mo><msub><mi>B</mi><mrow><mfenced separators=""><mi>n</mi><mo>-</mo><mi>k</mi></mfenced><mo>⁢</mo><mi>x</mi><mo>⁢</mo><mfenced separators=""><mi>n</mi><mo>-</mo><mi>k</mi></mfenced></mrow></msub></mfenced></math><img file="EP1513258B1_D0002.tif" /></maths> , where <i>B</i> is lower triangular.

0061Any information block <i>i</i>= (<i>i₀, i</i>₁<i>, ..., i</i>_<i>k</i>-1) is encoded to a codeword <i>c</i>=(<i>i₀,i</i>₁,<i>...,i</i>_<i>k</i>-1<i>, p</i>₀<i>,p</i>₁<i>, ...p_n-k-1</i>) using <i>Hc</i>^T= 0, and recursively solving for parity bits; for example, <maths id="math0003" num=""><math display="block"><msub><mi>a</mi><mn>00</mn></msub><mo>⁢</mo><msub><mi>i</mi><mn>0</mn></msub><mo>+</mo><msub><mi>a</mi><mn>01</mn></msub><mo>⁢</mo><msub><mi>i</mi><mn>1</mn></msub><mo>+</mo><mo>…</mo><mo>+</mo><msub><mi>a</mi><mrow><mn>0</mn><mo>,</mo><mi>k</mi><mo>-</mo><mn>1</mn></mrow></msub><mo>⁢</mo><msub><mi>i</mi><mrow><mi>k</mi><mo>-</mo><mn>1</mn></mrow></msub><mo>+</mo><msub><mi>p</mi><mn>0</mn></msub><mo>=</mo><mn>0</mn><mo>⇒</mo><mi>Solve</mi><mspace width="1em" /><msub><mi>p</mi><mn>0</mn></msub></math><img file="EP1513258B1_D0003.tif" /></maths><maths id="math0004" num=""><math display="block"><msub><mi>a</mi><mn>10</mn></msub><mo>⁢</mo><msub><mi>i</mi><mn>0</mn></msub><mo>+</mo><msub><mi>a</mi><mn>11</mn></msub><mo>⁢</mo><msub><mi>i</mi><mn>1</mn></msub><mo>+</mo><mo>…</mo><mo>+</mo><msub><mi>a</mi><mrow><mn>1</mn><mo>,</mo><mi>k</mi><mo>-</mo><mn>1</mn></mrow></msub><mo>⁢</mo><msub><mi>i</mi><mrow><mi>k</mi><mo>-</mo><mn>1</mn></mrow></msub><mo>+</mo><msub><mi>b</mi><mn>10</mn></msub><mo>⁢</mo><msub><mi>p</mi><mn>0</mn></msub><mo>+</mo><msub><mi>p</mi><mn>1</mn></msub><mo>=</mo><mn>0</mn><mo>⇒</mo><mi>Solve</mi><mspace width="1em" /><msub><mi>p</mi><mn>1</mn></msub></math><img file="EP1513258B1_D0004.tif" /></maths> and similarly for <i>p</i>₂<i>, p</i>₃<i>,...,p</i>_n-k-1<i>.</i>

0062<figref idref="f0007">FIG. 7</figref> is a graph of performance of the LDPC codes at the various code rates and modulation schemes supported by the transmitter of <figref idref="f0002">FIG. 2B</figref>. As seen, the 3/5 rate, 8-PSK scenario rivals the performance of the LDPC codes employing QPSK.

0063<figref idref="f0008">FIG. 8</figref> shows the simulation results for short block size LDPC codes, in accordance with an embodiment of the present invention. Table 16 provides the estimated performance at Packet Error Rate (PER) of 10^-7 for the short codes (<i>n_ldpc=</i> 16200). <tables id="tabl0016" num="0016"><table frame="all"><title>Table 16</title><tgroup cols="2"><colspec colnum="1" colname="col1" colwidth="23mm" /><colspec colnum="2" colname="col2" colwidth="37mm" /><thead><row><entry align="center" valign="top"><b>Mode</b></entry><entry align="center" valign="top"><b>Estimated Es/No (dB)</b></entry></row></thead><tbody><row><entry align="center">QPSK 0.444</entry><entry align="char" char="." charoff="5">0.65</entry></row><row><entry align="center">QPSK 3/5</entry><entry align="char" char="." charoff="5">2.45</entry></row><row><entry align="center">QPSK 2/3</entry><entry align="char" char="." charoff="5">3.35</entry></row><row><entry align="center">QPSK 0.733</entry><entry align="char" char="." charoff="5">4.35</entry></row><row><entry align="center">QPSK 0.777</entry><entry align="char" char="." charoff="5">4.90</entry></row><row><entry align="center">QPSK 0.822</entry><entry align="char" char="." charoff="5">5.40</entry></row><row><entry align="center">QPSK 8/9</entry><entry align="char" char="." charoff="5">6.50</entry></row></tbody></tgroup></table></tables>

0064<figref idref="f0009">FIG. 9</figref> illustrates a computer system upon which an embodiment according to the present invention can be implemented. The computer system 900 includes a bus 901 or other communication mechanism for communicating information, and a processor 903 coupled to the bus 901 for processing information. The computer system 900 also includes main memory 905, such as a random access memory (RAM) or other dynamic storage device, coupled to the bus 901 for storing information and instructions to be executed by the processor 903. Main memory 905 can also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor 903. The computer system 900 further includes a read only memory (ROM) 907 or other static storage device coupled to the bus 901 for storing static information and instructions for the processor 903. A storage device 909, such as a magnetic disk or optical disk, is additionally coupled to the bus 901 for storing information and instructions.

0065The computer system 900 may be coupled via the bus 901 to a display 911, such as a cathode ray tube (CRT), liquid crystal display, active matrix display, or plasma display, for displaying information to a computer user. An input device 913, such as a keyboard including alphanumeric and other keys, is coupled to the bus 901 for communicating information and command selections to the processor 903. Another type of user input device is cursor control 915, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to the processor 903 and for controlling cursor movement on the display 911.

0066According to one embodiment of the invention, generation of LDPC codes is provided by the computer system 900 in response to the processor 903 executing an arrangement of instructions contained in main memory 905. Such instructions can be read into main memory 905 from another computer-readable medium, such as the storage device 909. Execution of the arrangement of instructions contained in main memory 905 causes the processor 903 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the instructions contained in main memory 905. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement the embodiment of the present invention. Thus, embodiments of the present invention are not limited to any specific combination of hardware circuitry and software.

0067The computer system 900 also includes a communication interface 917 coupled to bus 901. The communication interface 917 provides a two-way data communication coupling to a network link 919 connected to a local network 921. For example, the communication interface 917 may be a digital subscriber line (DSL) card or modem, an integrated services digital network (ISDN) card, a cable modem, or a telephone modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 917 may be a local area network (LAN) card (e.g. for Ethernet™ or an Asynchronous Transfer Model (ATM) network) to provide a data communication connection to a compatible LAN. Wireless links can also be implemented. In any such implementation, communication interface 917 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information. Further, the communication interface 917 can include peripheral interface devices, such as a Universal Serial Bus (USB) interface, a PCMCIA (Personal Computer Memory Card International Association) interface, etc.

0068The network link 919 typically provides data communication through one or more networks to other data devices. For example, the network link 919 may provide a connection through local network 921 to a host computer 923, which has connectivity to a network 925 (e.g. a wide area network (WAN) or the global packet data communication network now commonly referred to as the "Internet") or to data equipment operated by service provider. The local network 921 and network 925 both use electrical, electromagnetic, or optical signals to convey information and instructions. The signals through the various networks and the signals on network link 919 and through communication interface 917, which communicate digital data with computer system 900, are exemplary forms of carrier waves bearing the information and instructions.

0069The computer system 900 can send messages and receive data, including program code, through the network(s), network link 919, and communication interface 917. In the Internet example, a server (not shown) might transmit requested code belonging to an application program for implementing an embodiment of the present invention through the network 925, local network 921 and communication interface 917. The processor 903 may execute the transmitted code while being received and/or store the code in storage device 99, or other non-volatile storage for later execution. In this manner, computer system 900 may obtain application code in the form of a carrier wave.

0070The term "computer-readable medium" as used herein refers to any medium that participates in providing instructions to the processor 903 for execution. Such a medium may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 909. Volatile media include dynamic memory, such as main memory 905. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus 901. Transmission media can also take the form of acoustic, optical, or electromagnetic waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, CDRW, DVD, any other optical medium, punch cards, paper tape, optical mark sheets, any other physical medium with patterns of holes or other optically recognizable indicia, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave, or any other medium from which a computer can read.

0071Various forms of computer-readable media may be involved in providing instructions to a processor for execution. For example, the instructions for carrying out at least part of the present invention may initially be borne on a magnetic disk of a remote computer. In such a scenario, the remote computer loads the instructions into main memory and sends the instructions over a telephone line using a modem. A modem of a local computer system receives the data on the telephone line and uses an infrared transmitter to convert the data to an infrared signal and transmit the infrared signal to a portable computing device, such as a personal digital assistance (PDA) and a laptop. An infrared detector on the portable computing device receives the information and instructions borne by the infrared signal and places the data on a bus. The bus conveys the data to main memory, from which a processor retrieves and executes the instructions. The instructions received by main memory may optionally be stored on storage device either before or after execution by processor.

0072Accordingly, the various examples of the present invention provide an LDPC encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code according to one of Tables 2-8 for transmission as a LDPC coded signal. Each of the Tables 2-8 specifies the address of parity bit accumulators. Short LDPC codes are output by utilizing LDPC mother codes that are based on Tables 2-8. <i>k_ldpc</i> of the BCH encoded bits are preceded by <i>k_m</i> - <i>k_ldpc</i> dummy zeros. The resulting <i>k_m</i> bits are systematically encoded to generate <i>n_m</i> bits. The first <i>k_m - k_ldpc</i> dummy zeros are then deleted to yield the shortened code. For an LDPC code with code rate of 3/5 utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach advantageously yields reduced complexity without sacrificing performance.

0073while the present invention has been described in connection with a number of embodiments and implementations, the present invention is not so limited but covers various obvious modifications and equivalent arrangements, which fall within the purview of the appended claims.