Method of controlling the fill level of a buffer and corresponding data processing system

0001In coming data, including signal data processing systems commonly address generators are used, which for generating Write and read addresses to access a buffer memory serve. Such address generator conventionally includes one or more address registers, the contents of which as Read address or write address on an address bus of the system can be output to the to be controlled buffer is connected, and at least one counter or Inkrementstatement which to change, eg incrementing the Register after each outputting a read or write address used to so the register further determine an address on the newly issued - in ascending or descending Direction - follows. A common form of such a Address generator and a modulo register, in which the length of the buffer memory, and more precisely the number of its memory locations, is entered. If the read or write register Offset contained to the base address by incrementing increases beyond the value contained in the modulo register, the offset is taken modulo the buffer length. base address and offset can be stored in a register.

0002To determine the level of such a buffer is of Time to time in the difference between the write and read registers Offset contained modulo calculates the buffer length. This technique works if the data rates at which is written into the buffer and read from, not too diverse and time not unduly vary. If these conditions are not met, so can it between two calculations of the buffer fill level to a the write register, the reading register, with the result that data are overwritten in the buffer before they read have been. When an underflow is the reading register, which overtaken the write register, so that data is read twice will.

0003The object of the present invention is a method for detecting or controlling the level of a buffer and a to specify implementing the method appropriate address generator, which allow a Pufferüber- or underflow reliably detect or prevent its occurrence.

0004The object is achieved firstly by a process with the Features of claim 1. By provided a Füllstahdsregister is the incremented at each write operation in the buffer and decremented at each read operation from the buffer is located at any time before a current level value, the read and if necessary to trigger countermeasures against a Overflow or underflow can be used. Since the content the level register is always up to date, can a Speicherüber- or underflow countermeasures in time, or it can be detected at least safe.

0005A simple way to control the filling level, is that Frequency of read and / or write access to the buffer to control depending on the detected level. The easiest this can be done, in which a lower limit value is set at below which the frequency of reading reduced or the writing frequency is increased, or upper limit is set above which increases the frequency of reading or reduces the write frequency becomes. Both limit values ​​can be the same, so that two read and write frequencies above and below of the limit value are used.

0006Usually, however, used the deviation of the level from the nominal value and increases or allowing the read or Write button proportional to the deviation.

0007A further possibility for controlling the filling level is Use of different methods of accessing fast to the buffer. Thus, it may, as long as the filling level of the buffer is low, be sufficient data from the buffer in each case individually to read, while if it exceeds a limit may be necessary to read the data blockwise move in order to get them more quickly from the buffer and execute.

0008The limit must be at least the size to be read a Blocks correspond, otherwise the reading of the block itself could lead to a memory underflow.

0009Conversely, it may be expedient Blockwise letter in allow the buffer, as long as the level is low, and the data rate by disabling the block-wise writing to reduce, when the level exceeds a second threshold. This second limit shall not be greater than the difference between the size of the buffer and the size of a to be read block.

0010The object is further achieved by an address generator a level register as defined in claim eighth

0011To be processed in a data system, the data rate of a Data source to the buffer memory and / or from the buffer memory to a data sink based on the detected fill level of the buffer to control, a first embodiment according to the Address generator adapted to the data source is exceeded stopping a first level limit and falls below a second threshold value (of the first can be the same) again to set in motion. This kind Level control is particularly suitable for a data processing system, in which a plurality of address generators and buffers through a common bus data received associated sources. Namely, since in such a System data source, its associated buffer memory a has reached critical level, no bandwidth bus claimed whose transmission capacity is fully for those data sources whose assigned have buffer capacity.

0012According to another preferred embodiment, the buffer memory to a write bus for receiving data from a source and a read bus for outputting the data to a connected sink that independent on each other clock signals feature, and the address generator is set up to Clock rate to control at least one of the buses, so the adjust the data rate to a respective detected level.

0013Further features and advantages of the invention will be made the following description of exemplary embodiments, Reference to the accompanying figures. Show it:<dl tsize="6"><dt>Fig. 1</dt><dd>a block diagram of an address generator according to the invention;</dd><dt>FIG. 2</dt><dd>a first embodiment of a data processing System that the address generator of FIG. 1 used, and</dd><dt>Fig. 3</dt><dd>A second embodiment of such a data processing system.</dd></dl>

0014The address generator 1 shown schematically in Fig. May be divided be in a write address generator section 1, a read address generator section 2, and a level measuring section 3. The structure of the two portions 1, 2 is in substantially always the same, so only one of them is described in detail here; functionally identical elements in the two sections each have up to a prefixed 1 or 2, identical reference numerals.

0015An address output 10 of the write address generator section includes 32 bits, including a group of 16 high-order Bits directly 16 high-order bits of the base address register 12 meet, and 16 less significant bits by summation of the 16 lower bits of the base address register 12 and the contents of a write address register 11 are formed. The same output of the write address register 11 is connected to a first input of the adder 13, to whose second input the contents of a Inkrementwertregisters 14 bears. The Inkrementwertregister 14 can be described as having values ​​± 1, ± 2, ± 4, depending on if the buffer byte, 2-byte or 4-byte-wise, in ascending or descending direction is read.

0016The adder 13 receives a trigger signal via a trigger input 15. The output of adder 13 is a modulo arithmetic circuit 16 is connected, which comprises a register 17, in wherein the length of a to be controlled by the address generator is buffer stored. An output of the modulo arithmetic circuit 16 is connected to a data input of the write address register 11 connected. The contents of the registers 14, 17 from the outside are programmable or adjustable by switch.

0017If a data value in the address generator controlled by the buffer is to be written, a trigger pulse on Trigger input 15 applied. This causes trigger pulse the adder 13, the output from the registers 11, 14 to add values ​​and supplied to the modulo arithmetic circuit sixteenth The contents of Inkrementwertregisters 14 corresponds to that Number of storage locations of the buffer memory, the at a single write (or read) access to the buffer memory simultaneously written (or read) can be, ie, the width of the data bus to which the buffer memory is connected, in bytes.

0018If the content of Inkrementwertregisters 14 is positive, the So buffer described in the direction of increasing addresses and is read, compare the modulo arithmetic circuit 16, the result of the addition with the content of the length register 17. If the result is smaller, it outputs it to the write address register whose content is new by the Value is overwritten.

0019then appears the sum of the new On address output 10 Content of the write address register 11 and the contents of the Base address register 12 so that a designated by this address Bytes of the buffer memory (and may, depending on described width of the data bus, one or three subsequent) can be.

0020If the modulo arithmetic circuit 16 determines that the from Adder 13 output result greater than or equal to the tab 17 registered length of the buffer is, so subtracted they the records from the result of the adder 13 and are the resultant difference to the write address register 11 further.

0021If the content of Inkrementwertregisters 14 is negative, compares the modulo arithmetic circuit the result with 0 and, if it is small, it adds the contents of the length register 17 added. With the result, they will overwrite the write address register 11th

0022When the write address has reached an end of the buffer, will in this way of the modulo arithmetic circuit to the opposite end of the buffer back to, and the Buffer is written again continuously from one end to another.

0023In a corresponding manner, the read address generating section by voltage applied to the trigger input 25 pulses caused successively outputting read addresses to the buffer.

0024The level measurement section comprises a level register 30 and an adder 31 which with two trigger inputs 15, 25 is connected to each at the arrival of a trigger signal, at the input 15 the contents of the 14 to Inkrementwertregisters hinzuzuaddieren the level of the register 30 or upon arrival a trigger signal at the input 25 the contents of the Inkrementwertregisters 24 thereof to subtract. How one easily seen, the value in the level register 30, when, for example, at start-up of the buffer memory, with is initialized to zero, will reflect the number of described, but not read memory locations in the buffer memory. This count is continuously at an output 32 of the address generator and may be used to control traffic used in a data be processed System are as below based on the embodiments of the Fig. 2 and 3 is explained.

0025In the block diagram of FIG. 2, the address generator is known from Fig. 1 are denoted by 40, and of it with write and read addresses Tend buffer 41. The buffer 41 is a D / A converter 42 downstream as an example of a data sink. A data source 42 to be converted by the D / A converters digital provides data to the buffer 41 via a write bus 43, is not shown in the figure. A digitally controlled Oscillator 45 and this downstream frequency divider 46 provide a clock signal CLK to the address generator 40 and the D / A converter 42, the frequency with which data from be read and changed the buffer 41, determined. The oscillator 45 receives a frequency control signal the level the buffer from the address generator 40. Within a set Tuning interval represents the oscillator 45 its output frequency the higher one, the higher the level value supplied to it is. The tuning interval is determined so that at its upper edge, the reading frequency is higher than a maximum expected write frequency to the write bus 43 and lower at the bottom than a minimum expected Write frequency. As a result, at high count the data read faster from the buffer 41, when she the write bus 43 are replenished, and at low Level they are read slower, so that in both cases the sheath fluid level to a mean value tends towards.

0026If the reading frequency a "continuous" function of the count is, as in this way a substantially constant data rate be achieved on the read bus 44th It is conceivable, however, Also, only two or three possible discrete frequency values provide for the oscillator 45, of which the oscillator 45 the respective highest setting, when the count of a exceeds the upper limit value and the lowest setting, when the count falls below a lower limit.

0027The data 3 shown schematically in Fig. Processing System includes a plurality of data sources 47, 47 ', ... the via a shared write bus 43 data to each a buffer memory associated with them 41, 41 '... transferred. Each data source 47, 47 ', ... is connected to the trigger input 15 of its associated address generator 40, 40 ', ... connected, to cause this to provide a write address, when the data source 47, 47 ', .. data via the bus wants 43 into the buffer 41, 41 ', ... write.

0028The level output 32 of each address generator 40, 40 ', ... is connected to an input of a comparator 48, 48 ', ... connected, at whose second input a reference value is applied. If for example, the count value of the address generator 40 exceeds the reference value, the comparator 48, a blocking signal to the Data source 47, which prevents them from making any further data on the write bus to send 43rd In this way, gets to the the buffer 41 connected data sink 42 time in the buffer work through 41 accumulated data. Since during this time the data source 47 is blocked, it does not compete with other Data sources 47 ', ... to transmission capacity on the Bus 43, which improves the transfer efficiency of the latter.

0029used a further embodiment of the address generator 40 Data processing system can also be explained using the block diagram of Fig. 3, it differs However, in their mode of action of the treated previously. In this further embodiment supports any Data sources 47, 47 ', ... at least two different Transmission modes, a first mode in which data values are transmitted individually and a second, in the each formed from a predetermined plurality of data values Packets are transmitted. If the on write 43 available transmission capacity allows, is to use the single transfer mode in general, since this shorter delay times in the transmission of Data to the sink allows a packet mode. If the transmission capacity the bus 43 is scarce, because many data sources access it, this means that assigned in the Address generators 40, 40 ', ... drop the meter readings. The comparators 48, 48 ', ... are used here to the Data sources 47, 47 ', ... each of single packet transmission switch when a critically low count is undershot.

0030Also in a data processing system in which only one single data source to a buffer on a write is connected, it can be useful to different transmission provide. In such a system, for example, a 48 3 serve comparator in the way of the comparator of FIG. To to generate a control signal to the data source a limit value is exceeded, the use of packet mode prohibits and it exempts falls below the limit, whether the packet mode to use or not. In such a system, the data source via the Entscheitung the use of the packet mode, if necessary, with respect to a vorgepufferte with her, to the buffer 41 to the data volume of to meet. Thus, the data source, if temporarily with her a high data rate is obtained by using the packet mode push up the level of the buffer 41st This is particularly useful when using this level as described by way of example in Fig. 2, the speed controls over the data to the sink with the will.

0031Although in connection with the above Ausführngsbeispiel thereof the talk is that the level register 30 with every rewrite only the buffer 41 is incremented, of course a decrement possible. However, then you have every time Read from the buffer 41, the level register 30 are incremented.