Nova Patents
EP1443560A2

Multi-chip electronic package having laminate carrier and method of making same

Abstract

A multi-chip electronic package which utilizes an organic, laminate chip carrier (2) and a plurality of semiconductor chips (3) positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes (4) and dielectric layers and couples the chips (3) to underlying conductors (8) on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.

EP1443560A2, drawing sheet 1
Sheet 1 of 12

Term

Term ended

Projected expiry passed 28 January 2024, 2.7 years ago.

  1. Priority
  2. Filed
  3. Published
  4. Projected expiry
  5. Today

19 claims: 2 independent, 17 dependent

  1. 1
    A multi-chip electronic package (1) comprising:an organic, laminate chip carrier (2) including a plurality of electrically conductive planes (4) spacedly positioned therein and separated by respective layers of dielectric material, said chip carrier (2) including a plurality of electrical contacts (6) on a first surface thereof and a plurality of electrical conductors (8) on a second surface thereof, selected ones of said electrical contacts (6) being electrically coupled to selected ones of said electrical conductors (8);and a plurality of semiconductor chips (3) spacedly positioned on said first surface of said organic, laminate chip carrier (2) and electrically coupled to selected ones of said electrical contacts (6) so as to be coupled to said selected ones of said electrical conductors (8).
  2. 16
    A multi-chip electronic package assembly (1) including:a circuitized substrate including a plurality of electrically conductive members thereon;an organic, laminate chip carrier (2) including a plurality of electrically conductive planes spacedly positioned therein and separated by respective layers of dielectric material (5), said chip carrier including a plurality of electrical contacts (6) on a first surface thereof and a plurality of electrical conductors (8) on a second surface thereof, selected ones of said electrical contacts (6) being electrically coupled to selected ones of said electrical conductors (8) ;a plurality of semiconductor chips (3) spacedly positioned on said first surface of said organic, laminate chip carrier (2) and electrically coupled to selected ones of said electrical contacts so as to be coupled to said selected ones of said electrical conductors;and a plurality of electrically conductive elements electrically connecting said selected ones of said electrical conductors on said second surface of said organic, laminate chip carrier (2) to respective ones of said electrically conductive members on said circuitized substrate.
Independent claims2