Audio and video decoding method and device, video driver circuit

The present invention relates to video driver circuits ( "Video Driver Circuit "in English), that is to say the circuits for decoding and displaying audiovisual programs coded in the form of a stream of digital data encoded according to a predetermined compression standard.

It finds applications in the video decoder having a personal video recorder functionality (PVR, English "Personal Video Recorder"). In such decoders, a recording of programs is performed on a digital mass storage medium (or DSM, standing for "Digital Storage Media") such as hard disk, tape Digital Video, DVD ( "Digital Versatile Disk"), etc ...

The affected decoders include set-top boxes ( "Set-Top Box" in English) providing the interface between an arrival signals digital broadcast in real time via satellite, cable or broadcast digital terrestrial (DVB or, standing for "Digital Video Broadcasting") a hand and an analog TV the other. Such a case is a decoder stand-alone device ( "Stand-alone"). But the invention also applies to decoders built into a digital TV or a digital device playback / recording such as a DVD player, a video cassette player Digital ( "Digital Video Cassette Recorder"), or similar.

A top box receives one or more programs in the form a compressed digital data stream, that is to say whose frames video (ie, images) and audio frames are coded so as to reduce the volume of data disseminated. For example, the encoding complies with the specifications of the MPEG-2 standard (ISO / IEC 13818-2) below MPEG standard ( "Motion Pictures Expert Group"). This standard defines a technique data compression coding of moving pictures and sound (Including digital television). According to the vocabulary of the standard MPEG, the stream of compressed digital data stream is called Transport ( "Transport Stream"). This stream contains audio data packets and video packet data.

In the present description, the term "presentation" when used in connection with a program, indicates the audio data restitution and decoded video, under respectively audible and visible form by user. The term "reading" ( "playback" in English), used in conjunction with a program, more specifically refers to the decoding and display of program from a recording of the program on a hard disk. The term display ( "display" in English) is used particularly for designate the presentation of video frames, while the word "play" is more particularly used to refer to the fact of presenting the audio frames.

The diagram of Figure 1 illustrates the decoding principle implemented in the first generations of set-top boxes which do not incorporate PVR functionality. A demultiplexer 71 receives one or more flows transportation, transmitted in real time via a transmission channel determined (Satellite, cable, DVB). It ensures demultiplexing (and possibly the descrambling) of this flow, and delivers a stream of audio data packets and a stream of video data packets. The flow of audio data packets is transmitted to an audio decoder 72 for decoding audio, while the flow of video data packets is transmitted to a video decoder 72 for decoding video. In other words, the demultiplexer plays the role of source data decode.

The diagram of Figure 2, in which the same elements as in Figure 1 bear the same reference numerals, illustrates a decoding principle set work in those enclosures known decoders that offer functionality PVR. The flow of audio data packets and video data packets issued by the demultiplexer 71 may be stored on a medium digital mass storage such as hard disk 74. Then, from the 74 hard drive, they can be inputted from the audio decoder 72 and video decoder 73, respectively, for decoding. In this case, a chapter MPEG standard recommends to play hard disk as a source of data to be decoded.

For new generations of set-top boxes, hard disk can offer a number of features including:<ul><li>decoding and presentation of a program broadcast in real time and simultaneous recording on the hard disk of another program broadcast real time, both contained in one or more received transport stream (s) the top box;</li><li>recording a program broadcast in real time when support press "Pause" presentation courses and recovery without interrupting the presentation with a delayed ( "Time Shift" in English), by reading the program on the hard disk, when you press the "Play" button;</li><li>loading scrambled programs according to the model says "the push "(" Push Mode "in English) that are made available only after, for example, the user acknowledgment of the corresponding access rights (For video on demand);</li><li>the implementation of advanced playback modes ( "trick modes", in English), that is to say a reading at a speed different from a speed Nominal (x1) forward, including fast forward ( "fast forward") and playback in reverse ( "rewind") at high speed or not;</li><li>etc ...</li></ul>

Processing a transport stream comprises essentially two tasks: firstly preparing data decoding and supply a MPEG decoder; and secondly the decoding and presentation of images, and of audio, which are achieved by the MPEG decoder.

The MPEG standard has been designed on the assumption that it is the source of data defining the timing of the treatment and provides clock reference. To display live broadcast programs, timing has thus become the MPEG decoder by the demultiplexer which provides demultiplexing the transport stream. The flow of images is present in the stream video data packets in proper order for the decoding time real and display the rated speed. The temporal reference system is then based on the program clock reference ( "Program Clock Reference "or PCR) present in the transport stream. The timestamps time of presentation ( "Presentation Time Stamp" or PTS) also present in the transport stream, also enable synchronization stream audio and video frames frames. The priority for the process decoding is to ensure that real-time constraints are respected, and no hardware resource (eg a file or a buffer) is in overflow status ( "overflow").

In the case of reading a program from the hard drive, apparent from the aforesaid prescription of the MPEG standard that is reading data on the hard drive that needs to clock the processing of data decode. However, data can get variable speed, depending access the hard disk that are made, these accesses can be performed Burst mode ( "Burst Mode" in English). In other words, the notion of real time is lost. On the other hand, we see that the hard drive is in him even a buffer that can compensate for situations overflow.

In addition, it may be desirable to perform the decoding in multiple parallel streams corresponding to several respective programs (Known feature "multi-decoding"), even with only one MPEG decoder. In particular, it allows the transition from a real-time presentation to a hard disk playback without loss of time due to a reset MPEG decoder (which may take several seconds). In a manner more Overall, this allows the end last after two program sequences Artifact-free, in particular for smooth insertion in a program or other pre-recorded commercials (known functionality "Seamless Splicing ").

In some cases, it is also desirable to use several MPEG decoder for decoding and displaying multiple programs simultaneously and / or for the display of a program simultaneously that displaying a still image.

Finally, the implementation of advanced playback modes is penalized by the real time aspects that constrain the decoding according to recommendation above the MPEG standard.

This is why the invention is to propose a principle decoding that overcomes the disadvantages and / or achieve all or Part of the above aims.

To this end, a first aspect of the invention provides a method of decoding according to claim 1.

audio data stream portions and video data stream which are loaded into the buffers are preferably portions of packet data flow, and / or data stream portions in clear (That is to say descrambled).

The pre-buffering ( "Pre-Buffering" in English) resulting from passage of flux in the buffers between the source or sources of data decoding (which are the demultiplexer and / or hard drive) and data consumers (that is to say the one or more audio decoders, and or video decoders), allows to break with the treatment process such it is implemented in the video driver circuits of the prior art. It allows and to achieve the objects of the invention in a manner that will appear on reading the detailed description that follows.

The fact that the buffers are loaded along the lines of pull prevents overflow risk of these memories. The fact they are discharged following the model of push guarantees the supply input data decoders. The fact that the memory management buffers is clocked by the (or) decoder (s) video helps regulate effectively the data stream to be decoded, which is particularly advantageous in playback mode on the hard drive.

A second aspect of the invention relates to a decoding device according to claim 10.

A third aspect of the invention relates to a video drive circuit comprising a device according to the second aspect.

Finally, a fourth aspect of the invention relates to a set top box comprising a circuit of the third aspect.

Other features and advantages of the invention will still on reading the description which follows. This is purely illustrative and should be read with reference to the accompanying drawings in which:<ul><li>Figure 1 and Figure 2, already discussed, are diagrams which illustrate the principle of the decoding of a stream of audio packets and a stream of video packets according to the prior art;</li><li>Figure 3 is a simplified diagram of an exemplary set top box incorporating a circuit according to the invention; </li><li>Figure 4 is a diagram illustrating an exemplary architecture material of a circuit according to the invention;</li><li>FIG 5 is a diagram showing the detail of an example of audio / video decoder included in the circuit of Figure 4;</li><li>Figure 6 is a diagram illustrating an example of software architecture means ensuring the recording and playback of programs on the Hard disk ; and,</li><li>FIG 7 is a diagram which illustrates the principle of decoding a stream audio and a stream of video packets packets according to the invention.</li></ul>

Figure 3 is a block diagram of a set top box 1 incorporating a video driver circuit according to the invention. The housing 1 comprises Example entries such as 2, 3 and 4, an input / output 5, and outputs such as 6a, 6b, 7a, 7b, 7c, 8 and 9.

The inlet 2 is intended to be connected to a parabolic antenna for receiving a digital satellite television signal. Input 3 is intended to be connected to an optical fiber for receiving a digital signal cable television. The inlet 4 is intended to be connected to an antenna for receiving a digital signal terrestrial television (DVB). Finally, input / output 5 for receiving or delivering a stream of packets transportation (audio or video) or TP_In TP_Out respectively from a other equipment, such as a DVD player, or for any other equipment, respectively.

The output 6a delivers an analog video signal video_out, which is a coded signal to RGB, YUV, Y / C (S-video) or CVBS ( "Composite Video Baseband Signal "), and is intended to be connected to the video input of a TV. The output 6b delivers for its equivalent signal which is example a CVBS signal or Y / C.

The output 7a delivers analog audio signals and Audio_Out_L Audio_Out_R intended to be provided to analog audio inputs, respectively left and right of the TV. 7b and 7c outputs deliver digital audio signals, for example encoded SP_DIF and PCM, respectively.

In addition, the outputs 8 and 9 respectively deliver a signal Vsync vertical synchronization and horizontal synchronization signal Hsync of the image display, and are intended to be connected to inputs Related TV.

To ensure the descent rate of the received digital signals on the inputs 2, 3 and 4, the top box 1 includes tuners respectively 2a, 3a, and 4a. It also comprises means ensuring the channel decoding the received signals, which include, for example, downstream of each of the tuners 2a, 3a, and 4a:<ul><li>an analog-digital converter respectively 2b, 3b and 4b;</li><li>a demodulator respectively 2c, 3c and 4c, ensuring respectively demodulating QAM, QPSK and COFDM; and,</li><li>an error corrector filter (FEC) respectively 2d, 3d and 4d.</li></ul>

The signals supplied by these channel decoding means are transport stream ( "transport stream") within the meaning of the MPEG standard. They each contain a multiplex of audiovisual programs, plus various data such as subtitles, teletext data, and / or user data including information on weather, program descriptions, etc ...

The top box 1 also includes a digital way mass storage 20, which is here a hard drive. Alternatively, it may be a DVD-ROM or DVD-Ram.

The top box 1 further includes a system memory 30 and a shared memory 31. In one example, the system memory 30 is a 32-bit memory which includes a ROM / SFlash 30a, a memory SRAM device 30b, and 30c respectively both SDRAM and 30d. In one example, the shared memory 31 is a memory 16-bit 133 MHz (megahertz) which includes one or two SDRAM memory 16 Mbps (megabits) or SDRAM 64 or 128 Mbits. Of Preferably, this memory supports 64 and 128 bit configurations.

The top box 1 also includes a video driver circuit 10, which is operable to perform the decoding and presentation of images and audio from the received transport stream, but also the registration of one or several programs on the hard disk 20, and playing a program recorded thereon.

For the presentation in real time and offline reading a program, the video driver circuit 10 provides the source decoding, which includes functions including demultiplexing / descrambling, for MPEG decoding, formatting video data in PAL, SECAM or NTSC, and formatting digital audio data into analog format. It also ensures the recording and reading of data on the hard disk 20.

The hardware architecture of the circuit 10 is detailed in the scheme of 4.

The circuit 10 comprises a central calculation unit 11 which is eg ST20 circuit STMicroelectronics. This is a RISC processor 32-bit, 166 MHz. It comprises a processor core ( "core" in English) of ST20C2 + type with 8 KB (kilobytes) of instruction cache, 8KB data cache and 8 KB of embedded SRAM.

An interconnecting plane 12 (bus) as the known data bus under the name STBus realizes the interconnection of various elements of circuit 10 to communicate with the unit 11. Alternatively, it may be the bus known under the name of SuperHyway, particularly if the unit 11 is based on a microprocessor core of SH40 type STMICROELECTRONICS.

The unit 11 is bidirectionally coupled to bus 12.

In addition, a manager of DMA ( "Direct Memory Access") to use or general manager GPDMA (standing for "General Purpose DMA controller") 121 is bidirectionally coupled to bus 12 to govern the channels materials between different hardware elements of the circuit 10. Recall DMA is a hardware channel between hardware or software entities circuit.

The circuit 10 also includes an audio / video decoder 13, e.g. MPEG-2 MP @ ML type decoder ( "Main Profile at Main Level"), endowed with advanced display modes such as fast forward ( "fast forward"), and the reverse smooth display ( "smooth rewind").

As detailed by the diagram of Figure 5, the decoder 13 includes, connected internally by an ad hoc interconnection plan: <ul><li>an audio decoder 130;</li><li>a video decoder 131;</li><li>a subtitle decoder 132;</li><li>a display composer 133 to manage the insertion of subtitles with furthermore an image overlay functionality ( "On-Screen Display "OSD) on 2-8 bits;</li><li>a shared memory interface 134 enabling it to communicate with the shared memory 31 of the top box; and,</li><li>buffers 135 FIFO ( "First-In First-Out") also CD_UNIT called in the MPEG standard.</li></ul>

The interface 134 is coupled bidirectionally, on the one hand, to shared memory 31 which is external, and secondly to the bus 12. buffers 135 are also coupled to bus 12 to receive data to be decoded.

Returning to Figure 4, circuit 10 also includes a decoder 22 teletext data connected to the bus 12 to receive the data to be decoded.

The circuit 10 also includes a video encoder 21 ( "Encoder Display" or DENC) coupled to the audio / video decoder 13. The video encoder 21 is to function to format the decompressed video data to PAL, SECAM or NTSC, depending on the type of the TV screen. That is why it is also called video encoder PAL / SECAM / NTSC. It generates signals analog video RGB, YUV, Y / C, and / or CVBS that are issued on outputs 6a 'and 6b' of the circuit 10. The video encoder 21 also generates signals vertical and horizontal synchronization of the image display, respectively Vsync and Hsync, which are issued on outputs and 8 'and 9' of the circuit 10. It is noted that these signals are intended to be supplied to the TV to which the audiovisual program is presented.

The outputs 6a ', 6b', 8 'and 9' of the circuit 10 are intended to be connected partying, respectively 6a, 6b, 8 and 9 of the circuit 1 (see Figure 3).

In addition, circuit 10 includes a carriage block 14 having a transport stream multiplexer 141 (or tsmux), transport interfaces Programmable ( "Programmable Transport Interface" or PTI), here three such interfaces 142, 143 and 144, and a descrambling module 145. ITP are coupled bidirectionally to the bus 12. In addition, the multiplexer 141 is coupled to bus 12 to receive the data extracted from HDD 20.

PTI serve to treat each one of the transport streams received via the inputs 2 ', 3' and 4 'of the circuit 10, or read on the hard disk 20, or alternatively the transport stream packets TP_In (from outside of the case 1) received through an input / output 5 'of the circuit 10. Advantageously, the Having multiple PTI (i.e. three in the example shown) allows the simultaneous treatment of several different transport streams.

The inputs 2 ', 3' and 4 'and the input / output 5' are intended to be connected, in case 1, the 2, 3 and 4 inputs and input / output 5, respectively (See Figure 3).

Each ITP 142, 143 and 144 provides treatment with multiple functions. Firstly, it ensures the selection of a data packet determined program transport stream Treaty (demultiplexing) generating of transport stream of packets each corresponding to a program determined. Also, it provides the index of the transport stream packet that is to say, the labeling of events with the packet number in which these events occur. In that the interface is programmable enables flexible implementation of this indexing, in particular on manufacturer's requirements for conditional access. Then, each PTI directs audio packets, video, teletext and subtitles, to appropriate decoder. Finally, it provides filtering and data acquisition distribution (tables), including program-specific information ( "Program Specific Information" or PSI).

In one example, each of the TNP 142, 143 and 144 supports a flow 120 Mbit / s. This easily allows the treatment of a stream of 15 Mbit / s for a fast forward mode display at x6 speed (that is to say six times nominal speed x1).

The descrambling module 145 ensures that multiple descrambling transport stream treated by the PTI. This unscrambling can be achieved according to a DVB mode, DES or ICAM, for example.

Optionally, the transport block 14 communicates with at least one of the inputs 2 ', 3' and 4 'via a low level interface 15 ( "Low Level Interface" or LLI). The interface 15 also provides the interface between the transport block 14 and the input / output 5 'of the circuit 10 via an interface parallel / series, for receiving the transport stream packets or supra TP_In for outputting the transport stream packets TP_Out also supra.

The circuit 10 also comprises an interface 16 for the disk access Hard 20. This is such a type of ATA interface ( "AT Attachment") also known as ITE label, for example an ATA-5 interface. In Alternatively, it is a UDMA-like interface. Through the interface 15, the hard drive can be accessed in read and write by the CPU 11 calculation and the 121 GPDMA manager.

The circuit 10 also includes an external memory interface 17 ( "External Memory Interface" or EMI) to communicate with the memory 30 system.

It also includes a set of 18 integrated interfaces for Communication with peripheral devices including, for example, five UART, six benches of parallel I / O, two card interfaces chip, four PWM channels ( "Pulse Width Modulation"), a serializer teletext, a multi-channel infrared transmitter and receiver, and a modem interface analog front (to the internet). An interface 181 type IEEE 1284 of the assembly 18 is also coupled to the low-level interface 15 to allow the reception and transmission of TP_In respectively and flow TP_Out via the parallel / serial interface.

Also, an engine 19 scrambling / descrambling local respectively data recorded on / retrieved from the hard disk 20 permits manage security against piracy of data stored on the hard drive. In one example, this engine makes the local data scrambling stored on the hard disk, to ensure access functionality conditional and prevent piracy.

Finally, circuit 10 includes an audio subsystem 23, a DSP with ( "Digital Signal Processor") 231, for generating audio signals from all common audio formats. This subsystem 23 is connected to outputs 7a ', 7b' and 7c 'of the circuit 10 via a unit 24 digital-analog converters (CNAs) for the outlet 7a '(with such a converter for each the left and right channels).

Thus, in an example:<ul><li>exit 7a 'delivers analog signals and Audio_Out_L Audio_Out_R presented above;</li><li>exit 7b 'delivers a digital audio signal type known as name of PCM ( "Pulse Code Modulation"), namely a form of audio coding uncompressed digital that is used especially in CD-Audio and DVD; and,</li><li>the output 7c 'delivers a digital audio signal type known as S / P DIF name ( "Sony / Philips Digital Interface"), ie a type of digital audio transmission using a coaxial connector.</li></ul>

The outputs 7a ', 7b' and 7c 'of the circuit 10 are intended to be connected to outputs respectively 7a, 7b, and 7c of the top box 1.

The video driver circuit 10 is, for example, designed as a system on a chip ( "System On a Chip" or SOC) technology with 0.18 microns. It can be integrated in a PBGA388 type of housing.

The diagram of Figure 5 shows an example of software architecture means the video driver circuit 10 that provide registration and reading on the hard disk 20. Conventionally, this architecture is presented in a layered model.

The lowermost layer 204 is a physical layer corresponding to the hardware architecture of the circuit 10, on which stacks the different software layers.

The higher layers form what is called a manager pipeline 210 ( "Pipeline Manager"). The pipeline includes a manager registration manager 211 ( "Record Manager"), manager of Reading 212 ( "Playback Manager"), an index manager ( "Index Manager ") 213, and a data manager 214 (" Data Manager ").

The lower layers (below the pipeline manager 210 but above the physical layer 204) comprises a module recording 221, an indexing module 222, a file system 223, an MPEG sequencer ( "MPEG Scheduler") 224, and a read module 225. In addition a DMA manager ( "DMA manager") is above 226 sequencer 224 and the module 225.

In the figure, unidirectional data exchange or bidirectional and / or commands between the entities of handler 210 pipeline between themselves or between these entities and those of the layers bass, are symbolized by vertical arrows.

The modules 221, 222 and 226 use a lower layer 227 said layer demultiplexing coded micro-architecture (or "TC code," set for "Transport Controller Code"). In other words, it is the driver ( "Driver" in English) performing the function of a programmable demultiplexing circuit Basic control code.

The file system 223 is based on the low-level driver software 228 hard drive ( "HDD Low Level Driver").

In an exemplary implementation of the invention, the sequencer 224 is based on four modules providing, separately, four tasks respective related to MPEG decoding. This is a header search module 231, a decoding module 232, a memory manager frame 233 and a display unit 234.

We will now describe in detail the operation of the modules 231 234 and 226, knowing that these modules are implemented in the form of software.

header search module 231

Preferably, the programs are stored on the hard disk 20 under the scrambled form ( "scrambled") of origin, either in the transport stream complete if all the multiplexed programs are stored together, either level of a partial transport stream if the transport stream of a single program is stored. Alternatively, the programs are stored in the form of a flow elementary packet ( "Packetized Elementary Stream" or PES) comprising audio data packets, video or data in a single program. In all cases, no indexing information such as the location of images are recorded on the hard drive. The content of the (or) program (s) Registered (s) is better protected against hackers.

However, this implies the implementation of a mechanism specific for playback. This mechanism has the function to analyze ( "parse" English) flow content stored on the hard drive to determine the images of the location, by detecting the header of the packets comprised in the flux. This mechanism is implemented by the header search module 231.

An MPEG video stream is composed of MPEG sequences, each composed of groups of pictures (GOP) within the meaning of the MPEG standard. Each GOP is composed of compressed images. Each image is composed of slices ( "slices" in English). Each slice is itself composed of macro blocks of 16x16 pixels each. Finally, each macroblock includes six 8x8 pixel blocks each.

The header search module operates in a manner very close to the header search functionality described in the standard MPEG. Its main function is to copy in software structures adapted all the information from the header fields of a MPEG sequence, until the wafer level.

During decoding, the header search module may, parallel, on the one hand, play video elementary data entries in a elementary stream buffer FIFO, and, secondly, detect boot code ( "Start Code") and report to the MPEG sequencer that such code has been detected and that the following data are available buffer.

Start codes that are detected are:<ul><li>the boot code of an image (code 0x00);</li><li>the startup code of the first tranche of the image (0x01 code);</li><li>all other start codes other than those of the other tranches image (codes 0xB0 0xFF).</li></ul>

In other words, the header search module detects all codes start other than the slice start codes except first tranche of an image (0x02 codes 0xAF).

The processing algorithm implemented by the search module header is very simple. When a start code is detected, the code of Startup is analyzed. then there are three cases:<ul><li>whether the boot code is a code of the MPEG standard but is not not a code among the codes 0x02 0xAF: then the boot code is stored in an appropriate software structure, it is reported that this information has been received and is available, and proceeded to search for another code starting ;</li><li>either the boot code is not a code of the MPEG standard: it is then reported to the MPEG sequencer that something is wrong, and it is process looking for another start code;</li><li>either the boot code is a code among the codes 0x02 0xAF: then it is reported to the MPEG sequencer that all information is available to carry out the decoding of an image (ie, all information down to the slice). Note that it is not, then, automatically process looking for another start code. In Indeed, it is the MPEG sequencer to control the search for a next image. This reflects the operation of the MPEG sequencer according to the Model drawing ( "Pull Mode").</li></ul>

The software structures mentioned above are described in the MPEG standard, to which the reader is invited to refer to more information. An overall structure or main structure of header research contains the position of the last start code detected in the flow as well as ad-hoc flag to signal that structure specific has been received or not.

Next to this, the header search module comprises:<ul><li>means for locating the position (ie, address) of a code of starting in a elementary stream buffer, using a 24-bit counter which is reset at each reset briefs buffers and indicating the number of bytes of the stream that were analyzed;</li><li>means for detecting that a discontinuity has been determined indicated at the entrance of the elementary stream buffer (e.g. when switching from one data stream coded source to another, or during playback mode changed);</li><li>means for extracting specific user data MPEG movie (which are detected between two start codes determined) and to store them in a special buffer called acquisition memory buffer. This acquisition memory buffer is allocated dynamically in order to overcome the fact that the size of the user data is not defined in advance. Possibly, this buffer acquisition may be a ring buffer, for compatibility with other modules; and,</li><li>means for defining the image type to decode and display in a specific protocol (called display protocol). These means are not not essential, but they facilitate and define the appropriate way of how an image to be decoded, synchronized and displayed. by Type images such means, including the fact that an image is progressive or not, the number of fields to be displayed by frame, the polarity of the fields (up to three fields to the maximum, each field being a top field ( "Top Field") or a lower field ( "bottom Field ")), the number of crop vectors (" Pan and Scan Vectors ") valid contained in the frame (up to four), and how cropping vectors are received and are to be used. In a way Advantageously, the image type is defined by a single parameter, which is a Input value ( "Entry V alue") in a table which condenses and unifies all information on the type of image.</li></ul>

232 decoding module

The main function of this module is to generate each instruction for decoding an image, from the header information that has been extracted by the header search module 231.

The module 232 receives calls only MPEG manager 224. The main following calls will now be explained:<ul><li>prepare a decoding instruction and request the provision by the manager of frame memories 233 to address a memory frame store where the image to be reconstructed, and the address of the (or) Memory (s) frame which is (are) stored (s) reference images necessary for this reconstruction;</li><li>store instruction;</li><li>skip an image;</li><li>reset the decoder on reboot or when errors fatal decoding;</li><li>locate and check the position of the decoder and the late data in the elementary stream buffer.</li></ul>

Regarding the preparation of the decoding instruction, the determined parameters are extracted from the header fields of the packet flow and data are formatted according to the registry plan ( "Register Map") of decoder. These include the flow types, namely MPEG-1 or MPEG-2, the horizontal and vertical picture settings, the image encoding type, the width and height of the image into macro-blocks, etc.

To decode an image, frame memories are needed to ie at least a reconstruction buffer, a memory buffer and a trailing buffer (for predicted images P type). It is at this point that the decoding module allocates image to be decoded the frame memory manager 233. As the decoding has not yet started, the manager 233 marks the reconstruction buffer as locked and considers that the image is available only when decoding is completed. If an error occurs during decoding, 232 manager can not ignore the image insofar no other process can not be used. The decoding module 233 is certain to get a frame memory when an application in the Manager 233. In effect, MPEG sequencer 224 ensures that there is at least one free frame memory or marked as such in Manager 233 before preparing the decoding instruction.

Also, the decoding module 232 is operable to verify that the internal RAM contains good quantization tables. In the MPEG data stream, three different types of quantization table can use: the default tables, which are not defined in the stream; the tables defined in the sequence; and specific tables for each image. If the good tables are not available, the module 232 calls the reloading tables by establishing a flag to this effect, and a pointer to the ad-hoc structure: the tables by defects in the table the sequence identifier ( "Sequence Extension") or table in the extension image ( "Picture Extension").

Concerning the location of the position of the decoding module within the elementary stream buffer, it is noted that the process used is similar to that described for the module search header 231, except that only the position of the last data in the video elementary stream buffer is given. Since there is another meter that indicates the size of the buffer for video elementary stream, it is thus possible to obtain a good estimate of the position of the module decoding.

Instruction on storage, it should be noted that all required parameters are stored at the same time when the MPEG sequencer 224 requests the decoding process starts. When the storage is completed, the actual decoding task is started immediately, without waiting for a vertical synchronization event. AT Note that this is when a new search header is started automatically, which mainly explains the research module Header 231 is restarted when a new portion of stream audio or video data is received in the stream buffer elementary.

Also, before starting the actual decoding, position decryption module is used for, first verify that the module and decoding information obtained from the header search module 231 are in phase with the image decoding module will decode, and secondly, to approximately locate the position of the image, and to associate with the frame (which can be used to start to decode Operational back, if the data is always available in the buffer).

Referring now jump of an image, it will be appreciated that when the MPEG sequencer 224 requires the jump of an image, this action is Immediate and a search header is launched at the same time maintain synchronization of two modules 231 and 232.

finally about resetting the 232 decoding module, Note that, in case of reset (complete or partial), all pointers position in the video elementary stream buffer are reset at the same time. In addition, all memory registers are left such that and maintain the same content as before. This is not a problem insofar as they are all controlled as needed. No side effect was observed in practice.

frame memory manager 233

This module serves to manage the frame memories used for image decoding. When the flow of images include type I frames (intra-coded), P-type (predicted frames), and type B (bidirectional predicted frames), it is therefore planned four memories frames at a minimum:<ul><li>one to store the image already decoded and that is being display;</li><li>two others to store two reference images ( "Predictors") necessary, at most, to reconstruct the image to be decoded; and,</li><li>the last to store the image decoding, being reconstruction.</li></ul>

The frame memory manager 233 also has the function of manage the image display order, depending on the direction of the display (in forward or reverse). To this end, it implements advantageously a virtual time base, rather than using a base time based on the presentation time stamps (PTS) associated the video frames, which would pose great difficulties when playing on Hard disk.

Virtual time base is based on a time reference Virtual respectively associated with each video frame, and when affected Video frame arrives decoder input 13. These references are made by a code number for example of 32 bits, the value is initialized by example h80000000 (80000000 in hexadecimal) at reception a read command. This initialization value to reference equivalent to about a year of frames in both forward and reverse.

These virtual time references are also used to determine which frames are the oldest among those stored in the frame memories, to determine the frame memories that can be overwritten as needed.

In practice, the frame memory manager 233 is configured the form of a table that contains the essential information for decoding and display of images. This information is:<ul><li>the maximum number (eg, 8-bit) memories frames that can be managed by the manager 233;</li><li>all image settings, such as the width of the image, image height, the presence of PTS, the presence of crop vectors ( "Pan and scan"), etc., arranged in a suitable structure;</li><li>the identifier (ie, an address pointer, for example coded on 8 bits) of the frame memory containing the decoded picture that is being display;</li><li>the identifier (eg 8-bit) of the frame memory containing the reference image before, if necessary (that is to say for a decoded picture which is of type P or type B);</li><li>the identifier (eg 8-bit) of the frame memory containing the rear reference image, if necessary (for image decode which is of type B);</li><li>the identifier (eg 8-bit) of the frame memory to contain the rebuilt image;</li><li>a virtual time reference (eg coded on 32 bits) associated with the current image display; and,</li><li>virtual time references (eg coded on 32 bits each) respectively associated with each of images that can be contained in the frame memories. There is therefore a number of such virtual timestamps equal to the maximum number of memories frames. These references are assigned at the time of decoding. They allow the display module 234 to know what image extract frame memories to display the images in the correct order.</li></ul>

display module 234

This module has the function, primarily, to manage the control the display of decoded images, ensuring the necessary conversions between the respective parameters of the decoded images and the display screen.

The images of the parameters are provided by the module 234 frame memories manager 233. These include the width and the height of the image, the position of luminance buffers and chrominance in memory, the display protocol from the list of Crop vectors ( "Pan and Scan vectors"), the reduced display area defined by said vectors, the aspect ratio of the image (eg 4/3, the PAL format). A priori, the decoded images are stored in the memories frames as macro blocks for 4: 2: 0.

The display parameters are supplied to the module 234 by the encoder of display 21 (Figure 4), in particular. These parameters include in especially the height and width of the screen, the offset of the viewable area of the screen aspect ratio of the full viewable area (eg 16/9) and the time interval between two fields.

But the module 234 also is operable to manage the interleaving or deinterlacing ( "interleaving / de-interleaving") images. In general, images of audiovisual programs that are currently broadcast are interlaced images.

If the display screen is an interlace display, and if the speed of Reading is the rated speed (x1), there is no need to change interleaving frames. It just should check that the polarity frames corresponds to that of the display screen.

But when the playback speed is different from the nominal speed, and / or when the interleaving of frames must be modified because the frames are progressive, it is advantageous to use a virtual time base to manage frames display with proper polarity.

buffer management module (DMA Manager) 226

The principle of the memory management elementary stream buffers who provide pre-buffering of the packets and audio data packets video data is illustrated by the diagram of Figure 7.

There is a set of buffers 70. These memories buffers are adapted to store portions of an audio data stream, or portions of a video stream. That is why they are called as memories elementary stream buffers. Note that the data stored in these buffers are encoded data, that is to say compressed according to a compression standard such as MPEG. Their size is sufficient to store a portion of sufficient flow for decoding. For those for storing portions of the flow video data, in particular, the size is sufficient to store at least one group of pictures (GOP) within the meaning of the MPEG standard. Preferably they are allocated, for example in the memory system 30, in the number chosen by the user. The number of buffers is, however, advantageously limited to a maximum number, for example twelve (that number dependent on available memory resources).

One or more streams of audio data and one or more flow video data, respectively corresponding to one or more programs specific audiovisual, are obtained from one or more sources respectively. These flows are preferably packetized elementary streams (PES) within the meaning of the MPEG standard. The data are typically plaintext data (that is to say, unscrambled).

In Figure 7, there was thus shown a flow of data packets Audio 81 and a video data stream packets 82 obtained from a demultiplexer corresponding to the transport block 14 of Figure 4, and more exactly one of the PTI 142, 143 or 144 of this block. For example, the flow 81 and 82 can be obtained by demultiplexing and descrambling of a stream 83 encoded data that is to say compressed (for example a stream of transport within the meaning of the MPEG standard) previously received by the demultiplexer 14, and transmitted to the set top box via a transmission channel determined (satellite, cable or DVB). Alternatively, they may be obtained by demultiplexing and descrambling the transport stream 84 received by the demultiplexer 14, which is comparable to the transport stream 83 but is read on the hard disk 20. Such transport stream may have been previously stored on the hard disk 20 after being transmitted to the housing via a decoder determined transmission channel (satellite, cable or DVB).

Similarly, there is also shown a flow of data packets 85 audio and video stream packets 86 obtained from disk hard 20 (or other digital support mass storage). For example, these flows 85 and 86 are read directly on the hard drive. In this case, they by eg previously stored on the hard disk, especially in the as an elementary stream (PES) packets as defined in the MPEG standard, after being produced by the demultiplexer 14 from a transport stream such as stream 83 supra.

In all cases, portions of the stream of audio data packets and portions of the stream of video data packets are loaded in a set of buffers 70. The fact that this flow portions packages means that it has a priori no information on the location of the audio frames and video frames (pictures) in the buffers. We will see later that portions of the analysis stage well buffered stream provides this information. The fact that buffered data is compressed data but not clear a real disadvantage with respect to the prevention of hacking programs, insofar as the buffering takes place at a stage close to the decoding.

Advantageously, the loading of the buffers 70 can be directed by the management module 226 (DMA manager), depending on model the draw ( "Pull Mode", in English). This way, the risk of exceeding capacity ( "Overflow") type buffers is avoided.

Then, the audio and video data are provided from said input buffers in the audio decoder 130 and decoder Video 131, respectively. Advantageously, this supply is controlled 226 by the DMA manager, following the model of push ( "Push Mode"). Nevertheless, it does not result in a risk of overflow FIFOs 135 (or CD_UNITs) decoders, as we shall see later that this is precisely decoders that control the supply. In addition, the risk Unlike "underflow" capacity ( "underflow" in English) of decoders is substantially limited due to the pre-buffering of packets.

Note that the set of buffers 70 may receive compressed data from several sources simultaneously. It's the case especially when the demultiplexers (PTI) 142, 143 and / or 144 of the block Transport 14 (4) deliver substantially simultaneously several streams audio data packets and multiple streams of video data packets correspondents. This is also the case when a demultiplexer delivers a stream audio data packets and a stream of video data packets corresponding, substantially the same time that another flow of packets audio data stream and a corresponding video data packets are read on the hard disk 20 via the interface 16.

In addition, several audio decoders such as decoder 130, and / or several video decoders such that the decoder 131 may be provided.

The rule applied by the DMA manager 226 is that, in a given moment, an elementary stream buffer of the assembly 70 is associated to at most one data source and at most one consumer data (audio or video decoder). In other words, a single path between a source and decoder requires a specific buffer.

In the end, the video data and audio data is thus provided decoded using the audio decoder 130 and video decoder 131, respectively.

Advantageously, when data from the hard drive 20, the DMA manager 226 is controlled by the video decoder 131. Says otherwise, the video decoder of the decoder 13, which is master circuit video driver 10 in playback mode on the hard drive, that is to say when the decoding data from the hard disk 20. Thus, the decoder video 131, which defines the general timing of the video driver circuit 10. To this Indeed, the video decoder 131 uses the corresponding events pulses of the vertical synchronizing signal of the display (ie, the signal Vsync) to define a virtual time base. He asks the data decode the hard drive via the DMA manager 226 that handles requests necessary to control elementary stream buffers by which data decoding pass. The available queries are, example:<ul><li>a request for controlling data loading in a determined buffer;</li><li>a request to control the stopping of loading data into determined a buffer;</li><li>a request for controlling the delivery of data by a determined buffer;</li><li>a request to order the stopping of issuing data determined a buffer; and,</li><li>a request to control the stopping of loading data into a buffer and the provision of data by the memory buffer, and to control the reset pointers to this memory buffer.</li></ul>

Combinations of these five applications to manage all situations in order to obtain data from the demultiplexer (or one of demultiplexers) or directly from the hard disk, and deliver them to the decoder (Or a decoder) for decoding.

Note that a synchronizing mechanism adapted, allows the audio processing process to synchronize with the process of video processing.

The actual time base corresponds to a period of the signal Vsync by raster (image) displayed. The base introduced virtual time is defined by the parameter: "number of past images per period of the signal Vsync" thereby including managing various playback speeds. Within the meaning of this definition, means looking picture, an image that was displayed or skipped.

For example, if the playback speed is the nominal speed (speed x1), the "number of past images per period of the signal Vsync" equals unity. This means that the number of times of the virtual clock is equal to number of periods of the signal Vsync. The virtual clock will align on the actual clock. If the playback speed corresponds to a display Image N (speed x N), where N is an integer determined, then it N means that images are passed to each period of the signal Vsync, or although N periods of the virtual clock signal have occurred during a period of the signal Vsync.

So during a freeze frame control ( "freeze"), or order in advance / decline of an image or a jump or a loss video synchronization, the operation consists in the parameter "number Past images per period of the signal Vsync "to 0 in the first case, and the increment / decrement by one in the other cases.

Each arrival of a pulse of the signal Vsync (that is to say, each vertical synchronizing display event, as noted VSYNC in the literature) corresponding to the virtual time base, the decoder 13 checks the state of the buffers 70. If they are empty, there request to the pipeline manager 210 to provide data to buffers 70. The pipeline control 210 while a manager HDD access 20 that provide data to the demultiplexer 14, which then provides them to the decoder 13 via the buffers 70, all being clocked.

The frames of the presentation speed can be handled by the module display 234 using a parameter in the form of a fraction type M / Q where M denotes the number of images and Q the number of events of vertical synchronizing the display (ie, the number of pulses of the signal Vsync). Preferably, the M / Q fraction is reduced, that is to say that the numbers M and Q are relatively prime. This speed is controlled by the user. Playback controls between that for this purpose act directly on the video decoder 131 (see Figure 7). The commands are, for example, Playback forward at the rated speed or at an accelerated speed, Freeze, reading backward at an accelerated speed or not, the image display, etc.

Preferably, the buffers 70 are managed so linear, in particular circular. However, when the user enters a control reverse playback (for an image display in reverse), the buffers 70 are not linear. In that case Indeed, the decoder will lock on an elementary stream buffer determined, and it can randomly access the data it contains.

In one advantageous embodiment, each memory buffer 70 includes a first and a second memory bank. It is thus perform an analysis of a first portion of the data stream stored in the first memory bank of a specific buffer, at the same time is carried decoding audio frames or video frames, respectively, contained in a second portion of the same stream Data that is stored in the second memory of said memory bank buffer.

This analysis is performed by the header search module 231 described above. It consists of identifying a random access point ( "Random Access Point "or RAP) of a group of decoded frames and determine the least for each of the frames of said group, including information the frame address in the buffer memory, a time stamp presentation (PTS) associated with the presentation frame order running before. In the case of a video frame coded according to the MPEG standard, these information further includes type I, P or B picture.