Compensating method for a pll circuit functioning according to the two-point-modulation and pll circuit provided with a compensating device

Translation of description of equivalent WO 03032493 A2

description

Matching method for operating according to the two-point principle PLL circuit and PLL circuit with a Abgleichvor- direction

The invention relates to a calibration method for operating according to the two-point principle PLL circuit and designed according to the principle of two-point modulation PLL circuit with a matching engine.

A low-complexity implementation of a transmitter concept for transceivers in mobile radio systems offer channels which have a are working according to the known principle of two-point modulation border modulator. A PLL (Phase Locked Loop = tracking synchronization) circuit is in this case used as a frequency synthesizer and used for phase or frequency modulation of a high frequency signal.

A memorizing of the modulation signal into the PLL circuit is usually carried out over a contained in the feedback branch of the PLL loop programmable frequency divider. A digital modulation signal is used and set one for continuously reprogramming the digital frequency divider. This form of modulation which is also called a one-point modulation, is known for example from the patents US 4,965,531, US 6,008,703 and US 6,044,124.

In order to achieve a low noise of the PLL circuit, the bandwidth of the circuit is designed to be considerably smaller than it is required for transmission of the modulated data. Therefore, in addition to the used purely digital modulation and an analog modulation to compensate for the beschränk- th bandwidth. The simultaneous injection of a digital and an analog modulation signal in a PLL circuit is called a two-point modulation.

Memorizing the digital modulation and the analog signals are at two different points of the PLL circuit. It is essential for the functioning of the two-point modulation is that, besides the temporal phasality a high degree of conformity of the amplitudes of the two modulation signals used is needed. Due to Herstellungsto- the components for the analog modulation tolerances, however, variations occur in the modulation steepness and the height of the amplitude modulation. For this reason, it is necessary to carry out an amplitude comparison between the analogue and the digital modulation signal according to the preparation of the PLL circuit.

Shall also temperature effects are taken into account, such a balance before each transmission must be performed.

A two-point modulator and a method for phase and frequency modulation with a PLL circuit is described in the German patent application DE 199 29 167 AI. The modulation takes place here on the one hand at a point of the PLL circuit on which there is a high-pass transmission characteristics for the modulation frequency. In addition, the modulation is performed at a second point in the PLL circuit, on which there is a low-pass transmission characteristics for the modulation frequency. Keep the modulation with low pass response characteristic is performed digitally in a frequency divider in the feedback path of the PLL circuit.

A known method of adjusting a PLL circuit with two-point modulation is to annul the two-point modulation of the circuit in the steady state shape and with an external measurement receiver emitted

to receive signal and demodulate. Depending on the demodulation result obtained an adjustment of the digital and analog modulation signals is carried out. Due to the non-linear behavior of the vibration generating member - a voltage controlled oscillator VCO (Voltage Control led Oscillator) - the PLL circuit with respect to frequency as a function of control voltage, this adjustment, however, must be performed for each channel. For a larger number of channels This results in a correspondingly long measurement time. In addition, the compensation information must be stored in a memory. A further disadvantage is to be seen in that the influence of temperature changes in this process is not considered.

Receiving and demodulating the signal generated by the PLL circuit can also be performed by the receiving part of the transceiver. As a result, however, the circuit complexity increases disadvantageously, because this complete second PLL circuit in the receiver would be required.

The object of the invention is to provide a calibration method for a PLL circuit to which a faster and more accurate amplitude balance between the digital and the analog modulation signal can be achieved. Furthermore, the invention aims to provide a PLL circuit having a matching device in which a faster and more accurate adjustment of the amplitude modulation signals can be achieved with a relatively simple circuit construction.

This object is achieved by a calibration method having the steps according to patent claim 1 and by a PLL circuit with a calibration apparatus comprising the features according to patent claim 9. At an adjustment method for operating according to the principle of two-point modulation PLL circuit, the PLL circuit is controlled by impressing a first digital modulation signal to a first frequency. Subsequently, a second digital modulation signal is impressed into the PLL circuit, the PLL circuit adjusts to a different second frequency from the first frequency. A difference signal, which is characteristic for the digital modulation signals through the two induced change of a control signal of a frequency-generating unit of the PLL circuit is generated and coupled out of the PLL circuit. The difference signal is compared with a signal which is characteristic of a modulation shift of an analogue modulation signal, compared and dependent on the determined deviation in the comparison of the modulation is changed so that the deviation is eliminated.

Thereby, in a comparison process of the invention is reached are that demodulating the output signal generated by the PLL circuit is omitted for reconciliation purposes, since everything is done for balancing on a deviation between two digital modulation signals, which is represented in a characteristic of the deviation difference signal. Further may be achieved that a relatively accurate and fast matching can be performed.

An advantageous embodiment of the inventive adjustment method is characterized in that the first digital modulation signal is impressed that the PLL circuit is controlled at a first frequency, the integration, which by subtracting a frequency of a variably selectable, digital modulation amplitude of a channel center frequency det is , then Provided by imprinting the second digital len modulation signal, the PLL circuit is controlled at a second frequency, which is formed by adding the frequency of the variably selectable, digital modulation amplitude and the channel center frequency, a Preferred embodiment is characterized in that one of the analog modulation signal corresponding voltage value for comparison with is the differential signal corresponding to the voltage value multiplied by the factor of the second This can be achieved that the Differenzsignai corresponding analog voltage value can be relatively large and thus differences between the digital modulation and the analog modulation can be relatively precisely balanced.

According to a preferred version of a main path of the PLL circuit is connected to a contributing control signal generating trimming path parallel. In this case, an advantageous variant of the method is characterized in that the adjustment path is activated at least during the impressing of the second digital modulation signal.

Furthermore it can be provided in an advantageous manner that the main path of the PLL circuit is disabled after impressing the first digital modulation signal by a generated from a first charge pump in the main path current to zero is set. It is thereby achieved that a the first digital modulation signal voltage corresponding to a tuning input of a VCO while the following steps (the second and optionally Einprägeschritt matching step) remains substantially constant.

Maintaining the generated voltage at the first Einprägeschritt to the tuning input of the VCO may also be implemented in other ways generally. A further advantageous embodiment is characterized in that the main path of the PLL circuit after impressing the first digital modulation signal is held active, and a current is set by the charge pump in the main path of the PLL circuit such that the voltage at the tuning input of the VCO is maintained substantially constant. This can be achieved by changing the

(Generated during the first Einprägeschrittes) voltage at the tuning input of the VCO is prevented due to leakage currents in the main path during of matching.

Another aspect of the invention relates to a PLL circuit which is designed for impressing an analogue and a digital modulation signal according to the principle of two-point modulation. A main path of the PLL circuit is a compensating path connected in parallel, comprising a coupling-out means for generating a difference signal which is characteristic of the change of a control signal of a frequency generating unit in impressing different digital modulation signals in the PLL circuit. Further, the trimming path comprises a comparison unit for comparing the difference signal with a comparison signal which is characteristic of a modulation shift of an analogue modulation signal and a modulation unit, which changes the modulation amplitude in response to an output signal of the comparison unit.

The inventive PLL circuit with the main path and the parallel connected compensating path, a relatively simple and low cost circuit structure is realized with which a faster and more accurate adjustment of the digital and the analog modulation signal may be performed.

In an advantageous embodiment may be provided that via a first switch, the differential signal can be applied to a modulation input of a VCO of the PLL circuit. Furthermore it can be provided that the adjustment path having a second switch in its closed

Position abuts the comparison signal at an input of the comparison unit.

Further advantageous embodiments of the adjusting method and the PLL circuit are given in the subclaims.

The invention is explained in greater detail using an exemplary embodiment with reference to the drawing. Show it:

Fig. 1 is a block diagram of a PLL circuit according to the invention with an adjusting device, and

Fig. 2 is a schematic flow diagram of the inventive adjustment method.

A working according to the principle of two-point modulation PLL circuit 1 (FIG. 1) is electrically connected to a modulation device 2 and a trimming path. 3 The PLL circuit 1 has, in its main path includes a phase detector (PFD = Phase Frequency Detector) 11, a first charge pump (CP1 = Charge Pump 1) 12, a first loop filter (LP1 = Loop Filter 1) 13 and a voltage controlled oscillator (VCO = Voltage Controlled Oscillator) 14. The loop filter 13 is designed as a low-pass filter, whereby high-strength-frequency signal components are smoothed. The VCO 14 represents the vibration generating component in the PLL circuit 1 and has a summation point 141 and a frequenzer- generating unit 142. Via a feedback path extending from the output of VCO 14 to an input of the PFD 11 and in which a programmable frequency divider (DIV = Divider) 15 is arranged, the PLL circuit 1 is closed. The DIV 15, for example, as a fractional-N Frequency divider to be executed, whereby a frequency division is enabled by a non-integer number.

For the preparation of a modulation signal MS, the modules 2 lationsvorrichtung a programming unit 21 and a di- gital-to-analog converter (DAC = Digital Analog Converter) 22.

Parallel with the main path in the PLL circuit 1 of the trimming path 3 is connected. The compensating path 3 includes a second charge pump (CP2) 33 and a charge pump 33 downstream second loop filter (LP2) 34th Furthermore, a comparison unit 31 and an analog modulation unit 32 in the compensating path 3 is arranged. Depending on the performed adjustment procedure, the comparing unit 31 and the analog modulation unit 32 is electrically connected via a first switch 35 with a modulation input ME of the VCO 14 of the PLL circuit. 1 Via a second switch 36 the output of the analog modulation unit 32 to a second input of the comparison unit 31 is fed back. This signal path between the modulation unit 32 and the comparing unit 31 further includes a multiplier 37th

In the two-point modulation of the PLL circuit 1 is impressed on an analog and a digital modulation signal via the modulation device 2nd Since the analog modulation signal as opposed to the digital modulation signal having no tolerances due to its discrete nature, drift and is subject to tolerances, it is necessary to compare the two modulation signals with regard to their amplitudes.

A modulation signal MS, which is designed in the embodiment as a digital signal, is lying at a summation point 4 on one of the PLL frequency synthesizer based Carrier signal TS added. The resulting signal 5 is applied to an input of the programming unit 21st

The programming unit 21, which is executed in the embodiment as a sigma-delta modulator produces at its output a first digital modulation signal 6 which is applied to a second input of DIV 15th The digital modulation signal 6 suffer from a division ratio 1: N_X An, wherein Ni represents an integer. Characterized the modulation signal MS is embossed with a specific modulation by the (variable) frequency division ratio over the DIV 15 in the feedback path. At the output of 15 DIV a first frequency division signal 7 is generated, which is applied to the first input of the PFD eleventh

At a second input of the PFD 11 is a reference signal with a respective reference frequency F_REF at. The reference frequency F_REF can be produced for example by a quartz oscillator, not shown. Thereby, a signal is generated at the output of the PFD 11, which characterizes the frequency and / or phase difference between the reference signal and the first frequency division signal 7th This output signal 9 of the PFD 11 is used to drive the charge pump 12th In the charge pump 12, a current is generated which is dependent on the signal 9, with which the charge pump 12 is driven. With the electricity generated in the charge pump 12, the loop filter 13 is charged. The output signal of the loop filter 13 is a voltage signal and is applied to the tuning input of the VCO 14 to TE.

At the output of the VCO 14 output signal AS is generated that is present at the first input 15 of the DIV and which is modulated by the first digital modulation signal 6th The adjustment process is explained below using the PLL circuit of Figure 1:

In a first step, the first digital modulation signal 6 with a first constant divider ratio l: Nχ entered. The dividing ratio l: Nχ is such that the PLL circuit 1 adjusts to a first frequency fi, the channel center frequency f a less a digital modulation shift .DELTA.f_Di_G equivalent.

By the PLL circuit 1 on the frequency F_x = F - .DELTA.f_Di_G is adjusted, arises at the tuning input of the VCO 14 TE, a voltage value Vi that corresponds to this frequency Fi, for example in the case of a linear frequency-to-voltage characteristic of the VCO 14 to this frequency, F_x is proportional.

During this Einregeins the PLL circuit 1 to the frequency Fi of the trimming path 3 is Turns off, wherein the second loop filter (LP2) 34 is precharged to the fixed voltage value of zero. The switches 35 and 36 are in the positions shown in Figure 1, referred to with two switches 35 and 36 as closed.

After adjusting the PLL circuit 1 on the frequency F_x is completed, it is deactivated in a second step, the main path in the PLL circuit 1 by the current from the charge pump 12 is set to the fixed value is zero and the loop is opened with it. In this case, it is ensured by the integrating behavior of the loop filter 13, that the voltage V_x at the tuning input TE of the VCO 14 or to a summation point 141 remains virtually unchanged. This applies at least for the duration of the subsequent reconciliation process. Further, now, the trimming path 3, that is, the second charge pump 33 and the second loop filter 34, and activated by the control loop on the trimming path 3 closed. The switch position of the switch 35 and

36 remains unchanged.

Subsequently, the programming unit 21 is reprogrammed so that at the output of the programming unit 21 a second digital modulation signal 6 'is generated which a second constant divider ratio of 1: N₂ indicates.

The second division ratio 1: N₂ is set such that the output signal AS at a second frequency F VCO 14₂ = F + .DELTA.f_Di_G having. The PLL circuit is thus at the second frequency F₂ adjusted. As at the tuning input TE still bears the voltage value Vi, arises on Modulationsseingang ME of the VCO 14, a voltage value V₂ a, of the double digital modulation 2Δf_Dι_G equivalent.

This voltage value V₂ results from the fact that the output frequency of the VCO 14 of the second frequency F₂ corresponds to the PLL circuit 1 is adjusted. At the frequenzer- generating unit 142 is therefore a control signal SS, the voltage V₃ this frequency F₂ generated. Because of the summation condition at the summing point 141 as well as the fixed voltage V_x at the tuning input TE, therefore, a voltage value is obtained at the modulation input ME V₂(2Δf_Di_G) = V₃(F + .DELTA.f_Di_G) - Vχ (f - .DELTA.f_Dig).

For comparing the difference signal 9 'at the output of the second low-pass filter 34 with an analog modulation signal, the modulation signal MS is in a third step, converted by the DAC 22 to an analog modulating signal 8, and is located at a second input of the analog modulation unit 32 at. The analog modulation signal 8 causes a frequency F₃ = F + Δfa_{n / A} at the output of the VCO. The frequency of these F₃ corresponding voltage value at the modulation input ME needs half as large as the voltage value in the balanced state V₂ be. To compare with the voltage value V₂ is this

Voltage tapped at the output of the modulation unit 32 and applied to a doubling in the multiplier 37 as a comparison signal 8 'seinheit to a second input of the comparability 31st

The voltage value V₂ of the difference signal 9 'is simultaneously applied to a first input of the comparison unit 31, which is embodied in the exemplary embodiment as a comparator. The switch positions remain unchanged, that is, the comparison unit 31 and the analog modulation unit 32 are decoupled by the switch position of the first switch 35 from the modulation input ME of the VCO 14th

One determined in the comparison unit 31 deviation between the voltage value V₂ of the difference signal 9 'and the corresponding voltage value of the comparison signal 8' is eliminated by the modulation of the provided at the output of the analog modulation unit 32 analog modulation is onssignals changed.

Alternatively, the differential signal 9 'corresponding voltage V₂ , Are, for example, stored by a capacitor at the input of the comparator unit 31 and are subsequently compared with the voltage value of the comparison signal 8 '.

After the calibration process is completed, the switch 35, the switch is switched, 36 are opened and the charge pump 33 and the loop filter 34 is disabled. The main path of the PLL circuit 1 is activated.

The PLL circuit 1 for the two-point modulation is now balanced and can start operating. The digital and analog modulation signal superimposed on it and it arises as a result of the described calibration process a frequency-independent transmission characteristic of the PLL circuit

1.

The generation of the comparison signal 8 'can be carried out also in the comparison unit 31 or in the analog modulation unit 32nd

Is used as the modulation signal MS to an analog signal, the modulation device 2 may for example also be carried out such that the DAC 22 is not needed but instead a corresponding signal conversion is performed in the digital modulation path.

The balancing of the voltages applied to the comparison unit 31 signals can for example be an iterative process. In this case, an approximate balance of modulation amplitudes takes place with alternating wise update the comparison signal 8 'and review the then obtained, modified output signal of the comparison unit 31. Upon submission of eliminating Spannungsdif erence to the comparison unit 31 the balance between digital and analog modulation is achieved.

It may also be provided that is kept active during the trimming, the main path of the PLL circuit 1 by the first charge pump 12 is operated with a small current. Due to the reduced current of the first charge pump 12 of the main path of the PLL circuit 1 can not follow the modulation, and the voltage at the tuning input of the VCO 14 TE remains constant. This can be achieved that a voltage loss at the tuning input TE of the VCO 14 are conditionally compensated by leakage currents, which may occur in a deactivated main path. In FIG. 2 is a schematic Abiaufdiagramm the adjusting method is shown. In the first process step Sl, the PLL circuit 1 (FIG. 1) 1 to a frequency f = f - .DELTA.f_Di₃ controlled by the first digital modulation signal is impressed 6 in the main path of the PLL circuit. 1 In the following second step S2 the second digital modulation signal 6 'is impressed into the PLL circuit 1 and the PLL circuit to the frequency F₂ = F + .DELTA.f_Di_G adjusted. An output 9 is coupled out of the PLL circuit 1 and a difference signal 9 'generated which for the digital by the two modulation signals 6 and 6 characteristic' caused voltage change of a control signal SS at the input of the frequency generating unit 142 is. The differential signal 9 'is the analog modem dulationssignal 8 proportional comparison signal 8' compared in process step S3. The determined at the comparing deviation between the difference signal 9 'and the comparison signal 8' is eliminated by the analog modulation amplitude is varied according to the step S4.