Method and system for synchronizing operation of remote timer with central control unit

This invention relates generally to the keeping of time in a computer system and, more particularly, to synchronization of a clock at a remote site with a master clock.

The improved price-performance of digital technology has made possible the advent of digital media broadcasting. The reduced cost of microprocessors, digital memory, and related devices has made it possible to place computers in set-top boxes (STBs) and related devices to receive digital cable or digital satellite television signals and decode those signals into audio-visual programs.

The advent of digital television broadcasting and the proliferation of STBs also makes it possible to enhance viewers' television experiences. In addition to transmitting video and audio data, digital media broadcasting allows additional data to be transmitted to the STBs with which users can interact. By analogy, users can interact through an STB with data transmitted via the digital media broadcast the way a computer user can interact with data available over the Internet. For example, digital television subscribers are already acquainted with an electronic program guide (EPG) function which enables users to select and tune to particular programs and/or read about the programs being shown at present or at later points in time.

The EPG is a rudimentary example of an interactive television application exploiting the capability of the digital broadcast medium to transmit additional content and for the STB to execute this additional content. The computer functionality of STBs also makes other interactive television applications possible. With appropriately configured STBs, users potentially can play along with game shows, take tests in on-line distance learning courses, bid in on-line auctions, and otherwise actively engage the content being broadcast. STBs thus allow users to have highly interactive television experiences.

One type of additional content application which is desirable in such a broadcast environment is one which provides functionality synchronized with video or audio content on a broadcast channel. In the examples of interactive game shows, on-line distance learning testing, and on-line auctions, it would be highly desirable to provide application-specific behaviors in an STB which are correlated to associated video and audio streams being broadcast. However, providing application-specific behaviors appropriately coordinated with video and audio streams presents a number of concerns.

An important concern is in synchronizing and maintaining the synchronization of a clock used to drive an interactive application to ensure that the application performs as desired by the creators and broadcasters of the application. In the examples listed above, manifest problems can result if a local clock driving an interactive application is out of synchronization with a master clock at a broadcast site. Users playing along with game shows might not be given the time to answer questions indicated by a host displayed on the screen. Students taking on-line tests might be given time to answer a question after the correct answer already had been displayed. Bidders in on-line auctions could win against higher bidders or lose against lower bidders because of timing inequalities among the bidders' systems. Clearly, maintaining synchronization of the local clocks regulating users' interaction with the interactive applications is an important concern.

Conventionally, timing of users' local clocks is regulated using a number of methods. A first method embeds synchronization points within the application data content to asynchronously initiate the additional content. For example, Society for Motion Picture and Television Engineers (SMPTE) time codes or frame numbers, counted from a selected reference point, can be used to trigger additional content as shown in FIGURE 1A. An application or program 100 is embedded with a number of trigger points 102. An application (not shown) executing the program 100 then monitors the video time codes 104 or frame numbers 106 and, using conventional conditional logic, determines when a trigger point 102 has been reached. The application (not shown) can then execute specific program logic to generate the change in appearance or behavior associated with the trigger points 102. This method is self-contained in that the encoded synchronization points can initiate display of the additional content. However, this method does suffer a disadvantage in that it consumes a significant amount of programming logic and a corresponding amount of program memory within the STB to operate. It also will be appreciated that, if there is a miscommunication in transmission of the reference point, none of the synchronization points will execute at the appropriate time.

A second method shown in FIGURE 1B involves a control operator 120 transmitting control signals at a broadcast site from which a program 122 is being transmitted can transmit control signals 124 to initiate the additional content. The control operator 120 might engage a semi-automatic computer application (not shown) to monitor the program 122 and view previously conceived timelines. Using such a system, the control operator 120 in real time could actuate a control device to insert trigger signals 124 into the broadcast stream at the appropriate times. The application executing the program 122 receives these trigger signals 124, interprets the instructions encoded therewith, and then effects the desired change in behavior or appearance of the program related to the additional content. The code needed to initiate the additional content may have been previously stored in the program memory, or may be transmitted along with the trigger signals 124. This method is used in the Advanced Television Enhancement Forum ("ATVEF") standard for interactive television over analog channels.

This second approach has the potential advantage of using less computer memory resources than does the first method. Nonetheless, this approach presents its own concerns. First, sending trigger signals 124 requires human intervention during the broadcast. Further, real-time bandwidth capable of supporting this remote control of the content is required. Second, in a digital media broadcast environment, even if the trigger signals 124 are sent at the appropriate times, limitations of the digital broadcasting medium may make it impossible to control when the trigger signals 124 will be received. In digital broadcasting, data blocks of video data, audio data, and other data, such as these trigger signals 124, all must be multiplexed for transmission. Unlike in an analog environment where signals can be added to a broadcast feed at a desired time, multiplexing of the digital signals can result in signals such as the trigger signals 124 being transmitted at different times. This results in a potentially ever-shifting offset between the transmission of the trigger signals 124 and their receipt. In other words, the process of multiplexing the trigger signals into the digital broadcast stream results in signal jitter which, in turn, results in clock phase jitter at sites receiving the timing signals.

To help reduce phase jitter, STBs can be equipped with their own slave clocks to be synchronized to a master clock at a broadcast site. However, placing slave clocks in the STBs may not solve the problems previously described. To keep manufacturing costs low, slave clocks may incorporate inexpensive parts. As a result, the slave clocks might exhibit significant clock drift on the order of one part in a thousand. Consequently, an application running on an STB with such a clock could be off by nearly two seconds by the end of a half-hour program, and that is assuming the slave clock was perfectly synchronized at the outset of the program. A potential solution to redress timing drift in the slave clocks is to periodically synchronize the slave clocks to the master clock. This solution, however, presents additional concerns.

FIGURE 2 shows a graph 200 plotting timing of local timing signals 210 versus timing of master clock signals 220 in an ideal system. In the ideal system, the slave clock is synchronized with the master clock and the slave clock rate accurately tracks the master clock rate. A master clock generates a regular sequence 230 of master clock signals 240. At a receiver equipped with a slave clock, a sequence 250 of slave clock signals 260 is generated. As can be seen from the graph, the slope of the lines representing the sequences 230 and 250 shows that the clocks track at the same rates. A difference between them is an offset 270 representing a propagation delay resulting from a time it takes for a synchronization signal from the master broadcast site to be received and processed. This offset 270 typically is negligible because it is small, is consistent across the network, and corresponds with a similar offset in broadcast of other video and audio content. In other words, in the ideal system shown in the graph 200, the slave clock signals 260 track the master clock signals 240 save for an acceptable propagation delay offset 270.

However, in a practical environment, such an ideal system as that described in the graph 200 of FIGURE 2 does not exist. FIGURE 3 shows a graph 300 of one possible scenario in which a slave clock does not accurately track a master clock. Again, the graph 300 plots timing of local timing signals 310 versus timing of master clock signals 320. In this system, the slave clock signals 360 are initially synchronized to the master clock signals 240. However, with the progression of time, a sequence of the slave clock signals 350 proceeds differently than that of the sequence of master clock signals 330. In particular, the slave clock in this example runs faster than the slave clock. Accordingly, any difference caused by a propagation delay offset 370 subsequently closes over time as the slave clock time sequence 350 overtakes the master clock time sequence 330 as shown by an intersection 380 of the sequences. Thus, presuming a propagation delay continues with the accompanying video and audio content, the timing of the program on the receiving device driven by the slave clock signals 360 will be out of synchronization with the program. The time signals triggering events will come earlier and earlier until the application may become unworkable.

One solution to a timing creep problem as shown in FIGURE 3 is to regularly resynchronize the slave clock with the master clock. Although the slave clock rate may not accurately track the master clock rate, regular resynchronization of the clocks can reduce the discrepancy to a manageable level. Unfortunately, in a digital broadcast environment where timing signals have to be multiplexed, resulting jitter can undermine the synchronization process.

FIGURE 4 shows a graph 400 illustrating the synchronization problems caused by jitter in the master clock signals caused by multiplexing or other effects. The graph 400 plots an absolute time 410 on the horizontal axis and a time generated/received 420 on the vertical axis. The sequence 450 of slave clock signals 460 runs at a consistent rate. Unfortunately, as described in connection with FIGURE 3, this rate may be wrong. However, attempting to synchronize the sequence 450 of slave clock signals 460 with the gerrymandering sequence 430 of master clock signals 440 would present problems of its own. Jitter in the master clock signals 440 results in a jagged sequence 430 of the master clock signals 440. Resynchronizing the slave clock signals 460 over a long term might result in an average whereby the slave clock rate more accurately tracks the master clock rate. However, synchronizing at times shown would result in ongoing jitter in the slave clock signals 460. Such jitter could result in abrupt changing of program attributes. Moreover, if a program event is keyed to be triggered only if computer program execution had commenced before a particular time is reached, a forward adjustment of the slave clock time signals 460 could result in that program event being ignored. Such triggering of program events is described in a co-pending patent application entitled "METHOD AND SYSTEM FOR FLEXIBLE TIME-BASED CONTROL OF APPLICATION APPEARANCE AND BEHAVIOR," bearing attorney docket number N.89070.

Undesirable effects of jitter also can be considered mathematically. At a time <i>T</i> the master clock emits a reference signal <i>M</i>₀. After a delay resulting from propagation delay and jitter, the signal is received by the slave clock as <i>M</i>'₀. The delay can be considered as having two components, a mean delay <i>P</i> and the deviation from the mean resulting from jitter <i>J</i>₀ . Therefore, the master clock signal received by the slave clock can be written as:<maths id="math0001" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">M'</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">M</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext> +P+ J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub></mrow></math><img file="EP1380918A2_D0001.tif" /></maths> The slave clock time when the signal is received is <i>S</i>₀. Thus, the apparent error <i>E</i>₀ between the slave clock time and the master clock time can be written as:<maths id="math0002" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><msub><mrow><mtext>-M</mtext></mrow><mrow><mtext>0</mtext></mrow></msub></mrow></math><img file="EP1380918A2_D0002.tif" /></maths> However, considering the error components in the received master clock signal <i>M'</i>₀, the actual error <i>E'</i>₀ inherent as a result of the error components in the received master clock signal <i>M'</i>₀ can be derived to be:<maths id="math0003" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E'</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>-</mtext><msub><mrow><mtext mathvariant="italic">M'</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>-</mtext><msub><mrow><mtext mathvariant="italic">M</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>-</mtext><mtext mathvariant="italic">P</mtext><mtext>-</mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub></mrow></math><img file="EP1380918A2_D0003.tif" /></maths><maths id="math0004" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E'</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>-</mtext><mtext mathvariant="italic">P</mtext><mtext>-</mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub></mrow></math><img file="EP1380918A2_D0004.tif" /></maths> Correcting the slave clock to account for this error, as visually can be appreciated from FIGURE 4, incorporates jitter into the slave clock signal <i>S</i>₀. Mathematically, adjusting the slave clock signal <i>S</i>₀ as result of the apparent error <i>E'</i>₀ directly incorporates the jitter <i>J</i>₀ into the adjusted slave clock signal <i>A</i>₀:<maths id="math0005" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">A</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>-</mtext><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>0</mtext></mrow></msub></mrow></math><img file="EP1380918A2_D0005.tif" /></maths> Put another way, substituting in the equations shows this adjustment to the slave clock incorporates into the adjusted slave clock signal <i>A</i>₀ a degree or error between the perceived error <i>E'</i>₀ and the actual error <i>E</i>₀:<maths id="math0006" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E'</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext> - </mtext><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext> = </mtext><msub><mrow><mtext mathvariant="italic">- P - J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>.</mtext></mrow></math><img file="EP1380918A2_D0006.tif" /></maths> In other words, the slave clock will be behind (slow) by the amount of the propagation delay, as expected, but also behind or ahead by the amount of the jitter <i>J</i>₀.

As previously described, jitter continues and varies with time, resulting in potentially runaway error. If the slave clock signal <i>S</i>₀ is set at the receipt of the first synchronization at a time <i>T ,</i> at time <i>T</i> + δ the master clock emits a reference signal with time signature <i>M</i>₁ = <i>M</i>₀ + δ resulting in perceived signal <i>M'</i>₁:<maths id="math0007" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">M'</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext> =</mtext><msub><mrow><mtext mathvariant="italic">M</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>+δ+</mtext><mtext mathvariant="italic">P</mtext><mtext>+</mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>,</mtext></mrow></math><img file="EP1380918A2_D0007.tif" /></maths> The elapsed time at the slave clock <i>D</i>_0⇒1 between the first perceived master clock signal <i>M'</i>₀ and the second perceived master clock signal <i>M'</i>₁ incorporates jitter affecting both perceived signals<maths id="math0008" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">D</mtext></mrow><mrow><mtext>0⇒1</mtext></mrow></msub><mtext> =</mtext><msub><mrow><mtext mathvariant="italic">M'</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>-</mtext><msub><mrow><mtext mathvariant="italic">M'</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext> =</mtext><mtext mathvariant="italic">δ</mtext><mtext>+</mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext mathvariant="italic">-J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>,</mtext></mrow></math><img file="EP1380918A2_D0008.tif" /></maths> The error in the unadjusted slave clock time <i>E</i>₁ incorporates the elapsed time :<maths id="math0009" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext> = (</mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext> + </mtext><msub><mrow><mtext mathvariant="italic">D</mtext></mrow><mrow><mtext>0⇒1</mtext></mrow></msub><mtext>) </mtext><msub><mrow><mtext mathvariant="italic">- M</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>.</mtext></mrow></math><img file="EP1380918A2_D0009.tif" /></maths> Substituting shows the effects of the ongoing jitter:<maths id="math0010" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext> =(</mtext><msub><mrow><mtext mathvariant="italic">S</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext> + δ + </mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext> - </mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>) - (</mtext><msub><mrow><mtext mathvariant="italic">M</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext> + δ)</mtext></mrow></math><img file="EP1380918A2_D0010.tif" /></maths><maths id="math0011" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext> = </mtext><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext> + </mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext> - </mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>.</mtext></mrow></math><img file="EP1380918A2_D0011.tif" /></maths> Thus, if the slave clock is set according to the error determined from the first reference signal, the measured differential error at the second reference signal <i>E</i>₁ - <i>E</i>₀ will be the sum of the jitters of the first and second signal <i>J</i>₁ -<i>J</i>₀. Therefore, while the mean differential error between any two reference signals will be zero (the expected value of (<i>J</i>_i+1 -<i>J</i>_i)), the variance of the differential error (the expected value of (<i>J</i>_<i>i+1</i> - <i>J</i>_i )² ) is increased by a factor of two.

Thus, there is an unmet need in the art for methods and systems for maintaining time on a slave clock accurately tracking a master clock time where reference signals received by the remote clock are subject to propagation delays and jitter.

Embodiments of the present invention facilitate synchronizing a slave clock with a master clock to avoid the effects of jitter in transmitted master clock signals. Effects of jitter are reduced by collecting a set of master clock time signals and averaging an error between the slave clock time signals and the master clock time signals. Repeating this process allows for correcting the slave clock time signals to correspond with the master clock signals over time without introducing abrupt timing shifts caused by jitter.

More specifically, embodiments of the present invention provide a method, a computer readable medium, and a system for synchronizing a slave clock time with reference time signals received from a master clock. Using embodiments of the present invention, a first basis set of reference time signals received from a master clock is collected. A first comparison set of slave time signals from a slave clock is identified such that each of the slave clock time signals in the first comparison set corresponds with receipt of each of the reference time signals in the first basis set. A difference between each of the reference time signals in the first basis set and the slave time signals in the first comparison set is calculated. An average difference between each of the reference time signals in the first basis set and the slave time signals in the first comparison set is then calculated and a slave time kept by the slave clock is adjusted by the average difference. Embodiments of the invention can be configured to respond to a stop indicator signaling that the slave clock time should be stopped. Upon the stop indicator being rescinded, the slave clock is synchronized to a master clock reference signal and then resynchronized over time as previously described.

In accordance with further aspects of the invention, the synchronization process repeats using subsequently collected second basis and second comparison sets of time signals. The slave time can be adjusted incrementally, such as by portions of the average difference. Also, over time cumulative average differences can be calculated to facilitate slave time adjustment. Intervals between synchronizations can be selected to reduce overhead of continual or constant synchronization. Embodiments of the invention allow for a slave clock to be associated with a local device and a master clock associated with a remote device, allowing synchronization of local devices across a network. The local device can receive reference signals from a wired or wireless network which can be a media broadcast network.

The preferred and alternative embodiments of the present invention are described in detail below, by way of example only, with reference to the following drawings, in which:- <ul id="ul0001" list-style="none" compact="compact"><li>FIGURE 1A is a timeline of timing reference signals for a hypothetical prior art interactive software application using embedded timing reference signals;</li><li>FIGURE 1B is another timeline of timing reference signals for a hypothetical prior art interactive software application using asynchronously broadcast timing reference signals;</li><li>FIGURE 2 shows a graph plotting master clock generated timing reference signals and slave clock generated timing reference signals in a hypothetical conventional system where the slave clock rate accurately tracks the master clock rate;</li><li>FIGURE 3 shows a graph plotting a master clock generated timing reference signals and slave clock generated timing reference signals in a hypothetical conventional system where the slave clock rate inaccurately tracks the master clock rate;</li><li>FIGURE 4 shows a graph plotting master clock generated timing reference signals affected by jitter as received at a remote location and slave clock generated timing reference signals in a hypothetical conventional system;</li><li>FIGURE 5 is a flowchart of a routine using an embodiment of the present invention for adjusting a slave time kept by slave clock;</li><li>FIGURE 6 is a flowchart of a routine using a second embodiment of the present invention for adjusting a slave time kept by a slave clock in an environment where the slave time can be stopped by a received signal; and</li><li>FIGURE 7 is a block diagram of a data processing/media control system for broadcasting master reference time signals and/or for receiving and responding to time reference signals according to an embodiment of the present invention.</li></ul>

By way of overview, embodiments of the present invention provide a method, a computer readable medium, and a system for synchronizing a slave clock time with reference time signals received from a master clock. Using embodiments of the present invention, a first basis set of reference time signals received from a master clock is collected. A first comparison set of slave time signals from a slave clock is identified such that each of the slave time signals in the first comparison set corresponds with receipt of each of reference time signals in the first basis set. A difference between each of the reference time signals in the first basis set and the slave time signals in the first comparison set is calculated. An average difference between each of the reference time signals in the first basis set and the slave time signals in the first comparison set is then calculated and a slave time kept by the slave clock is adjusted by the average difference. Embodiments of the invention can be configured to respond to a stop indicator signaling that the slave clock time should be stopped. Upon the stop indicator being rescinded, the slave clock is synchronized to a master clock reference signal, then resynchronized over time as previously described.

Embodiments of the present invention reduce variance of actual error between the master clock signals and the slave clock signals. Variances in a slave clock rate and a master clock rate can be adjusted by periodically synchronizing the slave clock to the master clock. Thus, to focus on the manner in which embodiments of the present invention reduce undesirable effects of jitter, it is assumed that the master clock and the slave clock track at the same clock rate.

As previously explained, where the master clock emits a reference signal <i>M</i>₀ , the signal is received by the slave clock as <i>M</i>_<i>'</i>₀, and a relative delay consists of a mean delay <i>P</i> and the deviation from the mean resulting from jitter <i>J</i>₀, the master clock signal received by the slave clock can be written as:<maths id="math0012" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">M'</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">M</mtext></mrow><mrow><mtext>0</mtext></mrow></msub><mtext>+</mtext><mtext mathvariant="italic">P</mtext><mtext>+</mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>0</mtext></mrow></msub></mrow></math><img file="EP1380918A2_D0012.tif" /></maths> If the master and slave clock have the same rate, then the absolute offset between them <i>E</i>'_i is constant, and so the expected value of<maths id="math0013" num=""><math display="block"><mrow><mtext>〈</mtext><msub><mrow><mtext mathvariant="italic">E</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><mtext>〉=〈</mtext><msub><mrow><mtext mathvariant="italic">E'</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><mtext>+</mtext><mtext mathvariant="italic">P</mtext><mtext>+</mtext><msub><mrow><mtext mathvariant="italic">J</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><mtext>〉=</mtext><mtext mathvariant="italic">E'+P</mtext></mrow></math><img file="EP1380918A2_D0013.tif" /></maths> can be estimated by averaging <i>E</i>_<i>i</i><maths id="math0014" num=""><img file="EP1380918A2_D0014.tif" /></maths> Averaging <i>n</i> values reduces the variance of <i>E</i>_<i>i</i> by 1/n. It will be appreciated that the mean delay incorporates and thus accounts for the clock offset.

Also as previously described, the mean delay is caused by the time required to create, multiplex and broadcast the reference signal. Within a network, broadcast propagation time between a broadcast site and individual receiving locations will vary from one to another. However, considering transmission speeds, this variation is small relative to the mean delay. Practically, because the mean delay at any one receiving location is constant, and the variation of the mean delay across a network is small, the imprecision introduced by ignoring the mean delay suitably is neglected. Alternatively, however, if the mean delay can be measured or estimated, the mean delay can be compensated by appropriately adjusting the value of the reference time in the synchronization signal.

In one presently preferred embodiment, the synchronization signal is transmitted once every two seconds. The apparent offset is measured for four consecutive received sync signals, and the offsets averaged. The clock is then set according to the average offset value. One minute later, the process is repeated. Therefore, once started, synchronization takes no longer than ten seconds to occur, and is updated at least once every 70 seconds. If the master and slave clock do not have the same rate, <i>E'</i>_<i>i</i> is a function of time, and the averaging process yields an time-averaged value for <i>E'</i>. However, for practical devices, the difference in rates is not sufficient to introduce a significant error when re-synchronization occurs each minute.

FIGURE 5 shows a flowchart of a routine 500 for synchronizing a slave clock according to an embodiment of the present invention. At a block 504 a first reference time signal from the master clock is received. At a block 506, the slave clock time is synchronized to the master clock time contained in the first reference signal. At a block 508, an error accumulator, which is used to accumulate total error between master clock reference time signals in the basis set and the slave clock time signals in comparison set, is set to zero. At a block 510, a master clock reference time signal is read and an error representing a difference between the master clock reference time signal and a slave time signal generated at a time corresponding to receipt of the master clock reference time signal is calculated and added to an accumulator total.

At a decision block 512, it is determined if enough master clock reference time signals and slave time signals to form the desired basis set and comparison set, respectively, have been compared and their differences accumulated. If not, the routine 500 loops to the block 510 to read the next master clock reference time signal and add to the cumulative error stored in the accumulator. If enough master clock reference time signals and slave time signals to form the desired basis set and comparison set, respectively, have been compared and their differences accumulated, at a block 514 a mean error is computed and applied to adjust the slave clock.

At a block 516, a next master clock reference signal is received and counted but substantively ignored. At a decision block 518, it is determined whether enough master clock reference time signals have been ignored so as to warrant another synchronization process. If so, the routine 500 loops to the block 508 to zero the accumulator and continue with the synchronization process previously described. If not enough master clock reference time signals have been ignored, the routine 500 loops to the block 516 to continue receiving, counting, and substantively ignoring the content of the signals. It will be appreciated that the waiting process manifested in blocks 516 and 518 could also be performed by a timer rather than by counting a number of reference signals.

Referring now to FIGURE 6, a second embodiment of the present invention accounts for situations in which, at a broadcast site, it is desired to stop the running of the slave clocks at remote locations. For example, if in the midst of a game show broadcast a news bulletin is issued, the broadcaster may wish to pause the game. The broadcaster may appropriately desire that slave clocks be stopped so that when the game show broadcast resumes, users also can resume their interaction with the game with appropriate synchronization. The broadcaster can stop the slave clocks by transmitting a stop indicator such as a status flag or status bit associated with the master clock reference time signals. Suitably equipped STBs or other receivers receiving the stop indicator cease execution of the slave clock. When the stop indicator is reset, cleared, or otherwise rescinded, the slave clock is resynchronized with the master clock, and a continuing resynchronization process resumes.

FIGURE 6 shows a flowchart of a routine 600 for synchronizing a slave clock according to a second embodiment of the present invention incorporating the previously described stop indicator. At a block 604 a first reference time signal from the master clock is received. At a block 606, the slave clock time is synchronized to the master clock time contained in the first reference signal. At a block 608, an error accumulator, which is used to accumulate total error between master clock reference time signals in the basis set and the slave clock time signals in comparison set, is set to zero. At a block 610, a master clock reference time signal is read and an error representing a difference between the master clock reference time signal and a slave time signal generated at a time corresponding to receipt of the master clock reference time signal is calculated and added to an accumulator total.

At a decision block 612, it is determined whether a stop indicator is received indicating the master clock is paused. If so, at a block 614 a master clock reference time signal is read and at a decision block 616 it is determined if the stop indicator has been rescinded indicating if the master clock is still paused. If the master clock is no longer paused as indicated by rescinding of the stop indicator, the routine 600 loops to the block 606 to resynchronize the slave clock. If the master clock is still paused, the routine 600 loops to the block 614 to read the next master clock reference time signal.

At the decision block 612, if it is determined that a stop indicator has not been received indicating the master clock is not paused, at a block 618 an error representing a difference between the master clock reference time signal and a slave time signal generated at a time corresponding to receipt of the master clock reference signal is calculated and added to an accumulator total. Operation of the error accumulator is equivalent to that described in connection with the routine 500 (FIGURE 5). At a decision block 620, it is determined if enough master clock reference time signals and slave time signals to form the desired basis set and comparison set, respectively, have been compared and their differences accumulated. If not, the routine 600 loops to the block 610 to read the next master clock reference time signal. If enough master clock reference time signals and slave time signals to form the desired basis set and comparison set, respectively, have been compared and their differences accumulated, at a block 622 a mean error is computed and applied to adjust the slave clock.

At a block 624, a next master clock reference signal is received and counted but substantively ignored. At a decision block 626, it is determined whether a stop indicator has been received indicating the master clock has been paused. If so, the routine 600 loops to the block 614 to read a next master clock reference time signal. If not, at a decision block 628, it is determined whether enough master clock reference time signals have been ignored so as to warrant another synchronization process. If so, the routine 600 loops to the block 608 to zero the accumulator and continue with the synchronization process previously described. If not enough master clock reference time signals have been ignored, the routine 600 loops to the block 624 to continue receiving, counting, and substantively ignoring the content of the signals. Again, it will be appreciated that the waiting process manifested in blocks 624 and 628 could also be performed by a timer rather than by counting a number of reference signals.

Further alternative embodiments allow other functionality. In one alternative embodiment, the slave clock can accumulate a series of values for the clock offset <i>E'</i>_<i>i</i>. This offset can be used to further smooth the variance of error between the master clock and the slave clock. In addition, adjustments could be applied to the slave clock incrementally over a period of time instead of all at once. For example, the average difference calculated between the basis set and the comparison set could be divided into a number of units and applied in increments of that same number.

In yet another alternative embodiment, the slave clock can accumulate a series of values for the clock adjustment <maths id="math0015" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext mathvariant="italic">E</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP1380918A2_D0015.tif" /></maths>_<i>i</i>, and estimate therefrom the rate difference between the slave and master clock. Once determined, this rate difference can be utilized to refine the clock adjustment. For example, if the slave clock operates more slowly than the master clock, an actual offset between the clocks at two consecutive signal times is given by<maths id="math0016" num=""><math display="block"><mrow><msub><mrow><mtext mathvariant="italic">E'</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><msub><mrow><mtext>​</mtext></mrow><mrow><mtext mathvariant="italic">+1</mtext></mrow></msub><mtext>=</mtext><msub><mrow><mtext mathvariant="italic">E'</mtext></mrow><mrow><mtext mathvariant="italic">i</mtext></mrow></msub><mtext>+γ</mtext></mrow></math><img file="EP1380918A2_D0016.tif" /></maths> An averaging procedure consistent with that previously described results in the computation:<maths id="math0017" num=""><img file="EP1380918A2_D0017.tif" /></maths> Using this computation, an estimation of <i>E'</i>₁ + P can be corrected for the drift between the clocks.

FIGURE 7 shows a computer system 700 operable for generating programs at a broadcast location or for executing programs using embodiments of the present invention. Particularly, the system 700 could be a STB or other receiver responsive to master clock time reference signals as previously described.

The computer system 700 is operable for controlling a display 702, such as a television, and an audio subsystem 704, such as a stereo or a loudspeaker system. The computer system 700 receives input from or sends output through a network 706, such as a broadband data network. The computer system 700 also receives or sends user input from a wired or wireless user keypad 708, which may be in the nature of a keyboard, STB remote, or other device.

The computer system 700 receives input from and sends output to the network 706 via an input/output controller 710, which directs signals to and from a video controller 712, an audio controller 714, and a central processing unit (CPU) 716. In the case of a STB, the input/output controller 710 suitably is a multiplexer for routing video data blocks received from the network 706 to a video controller 712 in the nature of a video decoder, audio data blocks to an audio controller 714 in the nature of an audio decoder, and for routing other data blocks to a CPU 716 for processing. In turn, the CPU 716 communicates through a system controller 718 with input and storage devices such as read only memory (ROM) 720, system memory 722, system storage 724, and input device controller 726.

The CPU is driven by a clock 717. In a receiver or STB, the clock 717 is a slave clock which can be synchronized with master clock reference time signals according to embodiments of the invention as previously described. For example, computer program code instructions could be stored in the system memory 722 and executed by the CPU 716 to apply corrections to the slave clock. Alternatively, in a system at a broadcast location, the clock 717 suitably is a master clock from which master clock reference time signals are transmitted over the network 706. It will be appreciated that the system 700 also can include devices or be programmed with instructions to respond to and generate stop indicators signaling when the master clock is paused.

While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the scope of the invention. Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.