Systems and methods for electrically isolating portions of wafers
Abstract
Systems for electrically isolating portions of wafers are provided. A representative system (200) includes a first wafer (201) and a first conductor (202) formed at least partially through the first wafer. A first conductor insulating layer (204) is formed at least partially through the first wafer. The first conductor insulating layer engages the first conductor and is disposed between the first conductor and material of the first wafer. A first outer insulating layer (210) also is provided that is formed at least partially through the first wafer. The first outer insulating layer is spaced from the first conductor insulating layer. Both the first conductor insulating layer and the first outer insulating layer are formed of dielectric material. Methods and other systems also are provided.

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Every citation, both ways
| Document | Relation | Office | Category | Cited during | Relevant claims |
|---|---|---|---|---|---|
| WO0165598A1 | Cites | World Intellectual Property Organization (WIPO) | XY | Search report | 1-3,8 |
| US3769562A | Cites | United States of America | A | Search report | 1-3,5,6,8 |
| US5998292A | Cites | United States of America | YA | Search report | 4-7,9,10 |
| PARK T ET AL: "DOUBLE TRENCH ISOLATION (DTI): A NOVEL ISOLATION TECHNOLOGY FOR DEEP-SUBMICRON SILICON DEVICES", DIGEST OF TECHNICAL PAPERS OF THE SYMPOSIUM ON VLSI TECHNOLOGY. KYOTO, MAY 17 - 19, 1993, SYMPOSIUM ON VLSI TECHNOLOGY, NEW YORK, IEEE, US, 17 May 1993 (1993-05-17), pages 137 - 138, XP000462937 | Non-patent | – | – | Search report | – |
| PATENT ABSTRACTS OF JAPAN vol. 2000, no. 16 8 May 2001 (2001-05-08) | Non-patent | – | – | Search report | – |
8 members in 3 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 35792 | United States of America | – | |
| 3579201 | United States of America | A |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| US2003077877A1 | United States of America | A1 | |
| EP1306901A2 | European Patent Office (EPO) | A2 | |
| JP2003151978A | Japan | A | |
| US6750516B2 | United States of America | B2 | |
| US2004192029A1 | United States of America | A1 | |
| EP1306901A3This record | European Patent Office (EPO) | A3 | |
| US7115505B2 | United States of America | B2 | |
| JP3955810B2 | Japan | B2 |
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| Application deemed to be withdrawnWithdrawn18D | 18D | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWNSTAA | STAA | |
| Designation fees paidAKX | AKX | |
| Request for examination filed17P | 17P | |
| Designated contracting statesAK | AK | |
| Request for extension of the european patentAX | AX | |
| Search report despatchedORIGINAL CODE: 0009013PUAL | PUAL | |
| Designated contracting statesAK | AK | |
| Request for extension of the european patentAX | AX | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI |
Numbers
- Publication
- 1306901
- Application
- 22571939
Titles3
- German
- Systeme und Verfahren zur elektrischen Isolierung von Teilen von Halbleiterscheiben
- English
- Systems and methods for electrically isolating portions of wafers
- French
- Systèmes et procédés pour isoler électriquement des portions d'une pastille semi-conductrice
Classification
- CPC, 8
- H10W90/00
- H10W20/023
- H10W20/20
- H10W44/212
- H10W90/722
- H10W90/297
- H10W20/217
- H10W20/212
- IPC, 5
- H01L23 52
- H01L21 3205
- H01L21 768
- H01L23 48
- H01L25 065
Designated states30
- Contracting states, 24
- Austria
- Belgium
- Bulgaria
- Switzerland
- Cyprus
- Czechia
- Germany
- Denmark
- Estonia
- Spain
- Finland
- France
- United Kingdom
- Greece
- Ireland
- Italy
- Liechtenstein
- Luxembourg
- Monaco
- Netherlands (Kingdom of the)
- Portugal
- Sweden
- Slovakia
- Türkiye
- Extension states, 6
- Albania
- Lithuania
- Latvia
- North Macedonia
- Romania
- Slovenia