Receiver, especially for mobile radio communication

Translation of description of equivalent WO 0203558 A2

p0001description

p0002Receiving means, in particular for mobile radio

p0003The invention relates to a high frequency receiving device, in particular for mobile communication.

p0004The mobile communications standard GSM (Global System for Mobile Communi- cation) is widely used in Germany and Europe and other countries. The existing GSM networks have a high surface coverage.

p0005For transmitting large amounts of data over the air, a new standard in Europe under the name Universal Mobile Te lecommunication System (UMTS) and International under the name IMT-2000 (International Mobile Telecommunication System 2000) is known. While the mobile devices for the GSM standard are also referred to as a device of the second generation, the mobile units are designed for UMTS beziehungswei- se IMT-2000 standard known as mobile devices of the third generation.

p0006To allow a smooth transition from GSM to UMTS standard, it makes sense that the new devices of the third generation, to a nationwide network coverage is assured with UMTS dominate, even the GSM standard.

p0007Important development goals in circuit design for receiving devices in mobile communications are a high integration density to ensure a small footprint, low power consumption, to ensure a long battery operation, backward compatibility with previous standards as well as avoiding or suppressing unwanted signals, for example by crosstalk chen. It is known to derive from a reference clock any desired clock rate with consuming feasible, working with Bruchzahl- ratios PLL synthesizers.

p0008Object of the present invention is to provide a receiving device, especially for mobile, to indicate which is suitable for the described devices of the third generation and in which the avoidance or suppression of unwanted signals is enhanced.

p0009According to the invention, the object of a receiving device, in particular for mobile, solved

p0010- A first mixer, the input of which a received signal is fed and at the output side is a first intermediate frequency signal can be tapped off,

p0011- A first phase locked loop which is connected to the first mixer, and which is a first reference clock supplied,

p0012- An analog / digital converter which is connected to the output of the first mixer and to which a first converter clock is supplied,

p0013- A reference generator for generating a reference clock, the reference clock is an integer multiple of the first reference clock and the first converter clock is an integer multiple of the reference clock.

p0014The invention is based on the principle to provide a clock distribution concept in which the analog / digital converter and the mixers are supplied by a reference clock, the respective necessary converter clock or reference clock can be formed by multiplication or division with whole numbers.

p0015It is thus a derivative of the reference frequency for the PLL stages or phase locked loops indicated that is easy to implement and use of frequency synthesizers which operate with fractional numbers avoids. This simple, possible integer by multiplying or dividing dissipation of transducer bars and reference clocks for the PLL stages of mixers allows the realization of a reception device with low energy consumption, smaller chip area and cost savings.

p0016Activation of the AD or DA converter by integer derivative of the converter clock from a quartz-stabilized reference clock has the advantage of low jitter in the AD or DA conversion.

p0017a second mixer is provided to which a second intermediate frequency signal is supplied to the input side and on the output side, a transmission signal can be tapped off, - in an advantageous embodiment of the present invention is

p0018- A second phase locked loop with the second mixer connected to which is a second reference clock supplied, - a digital / analog andler, which a second converter clock is supplied, connected to the input of the second mixer,

p0019- Where the reference clock is an integer multiple of the second reference clock and the second converter clock is an integer multiple of the reference clock.

p0020The driving of transducers and PLL stages of mixers in a transmit path with a clock, which is also apparent in each case by multiplication or division by a whole number of the reference clock, to realize a particularly energy-saving and space-saving circuit construction of a receiving device with transmitter supply allows.

p0021In a further advantageous embodiment of the present invention, the first reference clock is equal to the second reference clock and the first converter clock equal to the second converter clock. This is a particularly simple circuit complexity construction indicated in low energy consumption and a reduction with respect to mutual interference between the transmitting and receiving branch.

p0022In a further advantageous embodiment of the present invention, the analog / digital converter, a first digital mixer downstream of which a first interpolator is connected downstream, and the digital / analog converter, a second digital mixer upstream of the upstream of a second interpolator is.

p0023The digital mixer are mainly used for AUTOMATIC^hto frequency control. The analog / digital converter, which can be configured for example as a ΣΔ converter and may include which low-pass characteristics, causes a reduction of the clock. To convert the reduced by the analog / digital converter, derived from the reference clock converter clock to a desired clock for digital processing of the data, the first interpolator is provided. The first interpolator can be made up of several, each simply constructed sub-interpolators.

p0024The desired clock rate, for example, the bit rate of a spread signal, the so-called chip rate, being, which is to the spreading factor higher than the bit rate of the data sequence. This is a code division multiple access (Code Division Multiple Access, CDMA) can be supported in a simple manner.

p0025In the second mixer and the digital / analog converter having transmitting branch of the receiving device, a second interpolator be fed spread signal is relative to its clock interpolated so that the input of the digital / analog converter is a clock rate available in the digital / analog converter is interpolated onsfaktor with its predetermined interpolation. In a further advantageous embodiment of the present invention, the analog / digital converter, a first digital filter and the digital / analog converter to a second digital filter. Digital filters such as are customary in ΣΔ converters, reducing the converter clock for example, by a factor of 8 or other powers to the base. 2

p0026In a further advantageous embodiment of the present invention, the first and the second interpolator each multiple, serially arranged on sub-interpolators. The implementation of the clock after the first digital mixer ^ or before the second digital mixer in the respective desired bit rate of the spread signal can be implemented with little effort and good transmission characteristics of the desired signal characterized in that a respective duty cycle is implemented in a sub-interpolator having a fraction of small numbers, such as 4, 5, 1, 3, 8, 13.

p0027The modular principle with several serially arranged sub- interpolators has the advantage that with very little effort to adapt to each required bit rate of the spread signal is possible, for example for the Chinese TD-SCDMA system with an additional division by. 3

p0028In a further advantageous embodiment of the present invention, the reference clock has a clock frequency of 13 MHz. This is particularly advantageous in that the present circuit principle for mobile phones of the third generation of the same reference clock can be used as it has been commonly used for mobile devices of the second generation. This leads to a particularly small space and energy requirements of the circuit. Thus, also is a simple integration of a transmitting and receiving device that can support both GSM standard and the UMTS standard, indicated. In a further advantageous embodiment of the present invention, the clock frequency of the reference clock is 40 MHz. This has the advantage that do not fall in an embodiment of the transmission path as a superheterodyne transmitter having an intermediate frequency of 190 MHz, the harmonics of the reference clock in the intermediate frequency band.

p0029Further details are given in the dependent nsprüchen.

p0030The invention is described in several exemplary embodiments with reference to the drawings in greater detail.

p0031Show it:

p0032Figure 1 shows the basic circuit arrangement of a receiving device according to the invention,

p0033Figure 2 is a further development of the receiving device of to FIG 1 and

p00343 shows a further embodiment of the present

p0035The invention according to Figure 1, applied to a UMTS transceiver.

p00361 shows a receiving device having transmitting part, wherein a receive path and a transmit path having a transmit-receive circuit U SE are connected to an antenna ANT. It shows the upper branch in Figure 1 the E pfangspfad while the lower branch represents the transmit path. A received signal RX is the input side led to a first mixer Ml, with which it is mixed down using an additional, locally generated oscillator frequency to an intermediate frequency level with a first intermediate frequency IFL. The first intermediate frequency signal IFL is then an analog / digital converter AD supplied, having a first digital filter DF1. Both the first mixer Ml and the 1 1 Φ ß 1 1 1 1 g g 5H

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p0093forth; the space required for the operation of the second PLL stage is connected to the second mixer M2 P L2 T3 clock second mixer is determined by dividing by an integer in the divider stage TL2 from the reference clock RT forth.

p0094The circuit shown in Figure 1 has the advantage that the multiplication or dividing stages to supply the relevant blocks are simply constructed with a reference clock, as they require no realizations of Bruchzahl- ratios. This also provides a low power consumption and a small chip area. When the analog / digital converter AD, for example, a Ta "^ - reduction ratio of 8 has what may be caused by the contained in the analog / digital converter AD digital filter DF1, then a correspondingly reduced clock rate than the first digital mixer DM1 the first Interpolatorstu e IPL supplied. This realizes the implementation of the reduced stroke in the desired bit rate of the spread signal which is UMTS at 3.84 MHz and 1.28 MHz for China. the modular design of the first and second interpolator IPL, IP2 allows to interpret, for example one of the sub- interpolators for a factor of 3 or one-third, which can be bridged depending on the destination or specification in a simple manner. Preferred divider ratios of the sub-interpolators are, for example, 8/5, 4/5, 3/5 , 1/5, 8/13 and 1/3. the total divider ratio of the first interpolator IPL is calculated by multiplying the divider ratios of the sub- interpolators.

p0095For the US systems CDMA 2000 and IS-95, which spread signal with bitrates (chip rates) of 3.6864 Mcps (mega chip per second) or 1.2288 Mcps work can with Subinter- interpolator divider ratios of 6 / 5 and 4/5 or 6/5 and 2/5 in a simple manner a circuit adjustment can be achieved. <img id="imgf000011_0001" he="170" wi="255" file="imgf000011_0001.tif" img-format="tif" img-content="drawing" orientation="landscape" inline="no" />

p0096clock Tl, T2, as well as a divider T, a voltage controlled oscillator VCO and a loop filter F.

p0097Just as the receiving side and the transmission side in square is draturkomponenten I divided Q. Here controllable signal conditioning amplifier PA and low-pass filter TP are provided at the transmitting end and the receiving end. Due to the measures provided for in the intermediate frequency quadrature components of the signal I, Q are two second mixer M2, M2 'are provided which a generated by the second phase locked loop PLL 2 and amplified in an amplifier V local-oscillator signal once the correct phase and once at 90 ° phasenvers^tis fed up. The outputs of the second mixer M2, M2 'is connected an adder, which has additional, controllable power amplifier PA and band-pass filter BP downstream. Furthermore, a directional filter FI is provided for isolation of transmitters and receivers.

p0098The reference generator RG according to Figure 2 has a clock frequency of 13 MHz. The divider TLL for dividing down the reference clock RT in an integer division has a divider ratio of 13 or 65, so that, having as desired, the first and second mixer Ml, Ml ', M2, M2' a step width of 1 MHz or 200 KHz , At the receiving end, the Sub-interpolators the first interpolators have ipl, ipl 'division ratios of 8/5, 4/5 and 8/13, so that a bit rate of the spread signal at the output of the first interpolator of 3.84 MHz can be generated. The creation of a Spreizsignal- bit rate of 1.28 MHz, as is required, for example, China may be implemented with a fourth sub-interpolator with a divider ratio of 1/3. Of course, the individual sub-interpolators have other divider ratios. The multiplier MP1 for providing a clock converter comprises a factor of the third Since the analog / digital converter AD, AD 'are each a clock reduction of 2³ = 8 points out, at whose output a reduced clock speed of 13 MHz ^• 3/8 = to 4.875 MHz. The described surrounded Sub-interpolator divider ratios then provide a spread with a bit rate of 3.84 MHz.

p0099Ξendeseitig the bit rate of the spread signal of 3.84 MHz by reverse divider ratios of the sub-interpolators of the second interpolator IP2, IP2 'of 5/8, 5/4 and 13/8 is converted into a clock frequency of 4.875 MHz, which of the interpolation 8, the digital / analog converter DA, DA 'exhibit, and the converter clock 3-13 MHz give the desired clock rate.

p0100The circuit of Figure 2 allows a simple, realizable with a small area requirement receiver with transmitter part, because the conventional GSM system clock can be of 13 MHz, which can be generated by conventional crystals, used further. Thus it is possible with the receiving device with transmitting part according to Figure 2, to receive the same time in the GSM mode while being sent in the UMTS mode, or vice versa.

p0101Figure 3 finally shows an embodiment of the receiving device according to Figure 1, trained for a UMTS receiver with transmitter part. In contrast to the receiving device according to Figure 2 is a heterodyne architecture is designed with an intermediate frequency of 190 MHz at 3 in the transmission part. Thus, since two mixer or Freguenz- converter stages M2, M3, M3, another PLL synthesizer PLL3 'are executed, for the third mixer M3, M3' needs.

p0102In deviation from the circuit of Figure 2 is in the

p0103Circuit of Figure 3 not an integer multiplier to derive the converter clock for the analog / digital converter AD, AD 'and the digital / analog converter DA, DA' required because the reference clock is 40 MHz and directly usable as converter clock. The division factor, which is an integer, for deriving the reference clocks for the phase detectors PD of the PLL stages pIII, PLL 2, PLL3 which the dividers TLL, <img id="imgf000014_0001" he="169" wi="253" file="imgf000014_0001.tif" img-format="tif" img-content="drawing" orientation="landscape" inline="no" />

p0104clock-distribution by integer divisor and the direct reference clock supply to the converter stages allows a very energy-saving mode is active, a small chip area requirement of realizations of the circuit and a low interference level on the IC. In addition, the converter stages can advantageously with a stroke reduction or clock interpolation of 2³ or other powers to the base 2 work, which enables a simple realization of the converter circuits.

p0105Finally, the modular design of the first and second interpolators have ipl, ipl allows ', IP2 and IP2' a simp; hey

p0106Adapting the circuitry to the different bit rates in different countries of the spread signals in code division multiple access CDMA.

p0107The measures provided for Sub-interpolators in the interpolators of the receiving device can work with the known multi rate processing.

p0108The receiving devices described are designed so that unwanted noise are greatly reduced or do not fall into the high-frequency or intermediate-working bands.

p0109As the clock rates are relatively low, the power consumption remains low.

p0110However, the clock speeds are high enough to allow a multi-channel receiver of the receiving device and a favorable reduction factor of 8 in the AD converters.