High accuracy timing model for integrated circuit verification

Description of equivalent WO 0188766 A2

HIGH ACCURACY TIMING MODEL FOR INTEGRATED CIRCUIT VERIFICATION

BACKGROUND OF THE INVENTION

CROSS-REFERENCES TO RELATED APPLICATIONS

0004This application claims the benefit of U.S. Provisional Patent Application No.

000560/203,748, filed May 12, 2000, entitled "High Accuracy Timing Model for

0006Timing/Power Verification."

FIELD OF THE INVENTION

0008The present invention is directed toward the field of electronic design automation ("EDA") tools, and more particularly to timing and verification techniques using a variable current source.

ART BACKGROUND

0010One aspect of integrated circuit design involves determining timing parameters

0011and power consumption to characterize the chip. Currently, large scale integrated circuit

0012("LSI") and very large scale integrated circuit ("VLSI") designs are transitioning from

0013deep submicron to ultra deep submicron ("DSM/UDSM") feature sizes. With this

0014transition, timing and power verification becomes more critical to achieve high electrical

0015performance with complex integrated circuit designs. In addition to feature sizes, the

0016accuracy of timing and power verification is also critical due to the ever-increasing size of

0017integrated circuit designs. Furthermore, fast and accurate power and timing verification

0018techniques are critical to meet the time to market product window demands on today's

0019integrated circuit designs.

0020In general, the timing parameters define how signals propagate from one section of

0021the chip to another. For example, timing parameters define rising signal and falling signal propagation times from drive circuits to receiver circuits in LSI/VLSI circuits. Currently,

0022timing and power information is generated based on an instance based delay and power

0023calculation. The delay and power calculation is formulated from a fixed library. Specifically, the library defines the pin-to-pin delay and output rise and fall times from a fixed reference lookup table of input signal slew rates and output loading capacitances.

0024Using a fixed base library, output rise and fall times are specified based on input signal

0025slew rates and fixed output loading capacitances.

0026To generate the library for timing verification, a load capacitance and input signal

0027slew rate are used to derive the change of output voltage from the change of input voltage.

0028However, this simple technique does not account for circuit level and device level non¬

0029linear characteristics. To further simplify the analytical requirements, the output signal

0030curve of a device is specified as a linear sweep. With the continuing rapid advances in

0031lithography, and as transistor dimensions become smaller, this output signal curve is

0032dominated to a much larger extent by the transistors' nonlinear region of operation.

0033This prior art technique causes errors in computing both the driving instance delay

0034and the RC network propagation delay. Specifically, these prior art linear sweep

0035techniques cannot match actual signal curves for circuits and thus introduce unacceptable

0036error for the delay calculation. For example, the linear sweep technique does not account

0037for resistive shielding effects. The resistive shielding effects are caused by the resistive

0038element in the RC network. These resistive shielding effects are amplified in

0039DSM/UDSM designs. Thus, using these linear sweep techniques, the actual signal delay

0040may be significantly different then the delay predictions. Accordingly, a new driving

0041methodology is required to properly calculate delay and power results that accurately

0042reflect the nonlinear behavior particularly found in DSM/UDSM designs. In the DSM/UDSM designs, modeling the circuits output strength based on the

0043change of the circuit's output voltage is critical to correctly calculating timing delay

0044parameters and power consumption. Because traditional linear voltage sweep techniques

0045cannot match the actual signal curves and circuits, and thus introduce unacceptable error

0046for delay and power calculations, there is a need to more accurately model circuit

0047characteristics based on the change of the output (driving) voltage.

SUMMARY OF THE INVENTION

0049A variable current source model accurately determines timing delays for designs

0050of circuits implemented in integrated circuits. A design for an integrated circuit specifies

0051a resistive-capacitive ("RC") network, such as a wiring network that interconnects circuits

0052in an integrated circuit. The RC network couples a driving point and a receiving point. A

0053circuit specified in the design, such as a gate level circuit implemented in a standard cell,

0054drives the RC network at the driving point. The variable current source model determines

0055driving currents for the circuit at the driving point based on the RC network and a

0056characterization of the circuit. A timing delay between the driving point and the receiving

0057point is determined by simulating the drive of the RC network with the driving current at

0058the driving point.

0059In one embodiment, the variable current source model operates as follows. A

0060plurality of time instances, which correspond to a plurality of output voltages to the

0061circuit, are specified. An initial drive current is selected, and a drive voltage,

0062corresponding to the drive current, is determined by simulating the driving of the RC

0063network at the driving point with the initial drive current. A load capacitance for the

0064circuit is dynamically determined. In one embodiment, the load capacitance is determined from the charging and discharging of the RC network from the drive current. For each time instance, a new drive current for the circuit is determined from the drive voltage and

0065the load capacitance from the previous time instance. A receiving voltage for each time

0066instance is determined from the drive voltage and a transfer function for the RC network.

0067The drive voltages and receiving voltages are used to generate the timing parameters of

0068the RC network.

0069In one embodiment, a circuit characterization model is generated to determine, for

0070each time instance, a new drive current from the drive voltage and the load capacitance

0071from a prior time instance. The circuit characterization model depicts relationships

0072among input signal slew rates, load capacitances, drive currents and drive voltages for the

0073circuit. In one embodiment, the model is accessed to extract a drive current based on the

0074drive voltage, effective capacitance, and the input signal slew rate selected.

0075The variable current model has application for calculating power, including peak

0076power, as well as analyzing cross talk and IR drop.

0077BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates one embodiment for characterizing the timing parameters of a

0078circuit.

0079Figure 2 illustrates another embodiment for characterizing timing parameters in an

0080integrated circuit.

0081Figure 3 A illustrates a circuit that models the variable current source at a first time

0082instance. Figure 3B illustrates a circuit that models the variable current source at a second

0083time instance.

0084Figure 3C illustrates a circuit that models the variable current source at time instance "n."

0085Figure 4 illustrates an example driver circuit for circuit characterization of the

0086present invention.

0087Figure 5 illustrates a V-I curve for an example gate level circuit.

0088Figure 6 illustrates a three dimensional graph that depicts the relationship between

0089driver voltage, Vd, driver current, I , and load capacitance, C_L*

0090Figure 7 is a flow diagram illustrating one embodiment for generating timing

0091parameters using the current based model of the present invention.

0092Figure 8 illustrates a drivability RC network for use in the determining the timing

0093parameters of the present invention.

0094Figure 9 illustrates an RC network transfer function for use in the determining the

0095timing parameters of the present invention.

0096Figure 10A illustrates an example circuit for cross talk analysis from the driver

0097circuits.

0098Figure 10B illustrates modeling gate level circuits with current sources for cross

0099talk analysis. Figure IOC illustrates an example circuit for cross talk analysis from the receiver

0100circuits.

0101Figure 10D illustrates modeling gate level circuits with current sources for cross talk analysis.

0102Figure 11 illustrates a circuit model for IR drop analysis.

0103Figure 12 illustrates a general-purpose computer system for executing the EDA

0104software of the present invention.

DETAILED DESCRIPTION

0106The disclosure of U.S. Provisional Patent Application No. 60/203,748, filed May

010712, 2000, entitled "High Accuracy Timing Model for Timing/Power Verification" is

0108hereby expressly incorporated herein by reference.

0109Timing Parameters Calculation:

0110Figure 1 illustrates one embodiment for characterizing the timing parameters of a

0111circuit. The circuit includes a driver circuit 110 and a receiver 130, interconnected by a

0112resistive-capacitive ("RC") network 120. In one embodiment, the RC network comprises

0113interconnect lines, consisting of metal or polysilicon, deposited on one or more layers of

0114an integrated circuit. The driver 110 is intended to represent a broad category of circuits

0115that provide driving sources (e.g., charging/discharging paths) at an output stage.

0116Similarly, the receiver 130 is intended to represent a broad category of circuits that

0117receive the signals and propagate them through circuits (e.g., logic gates).

0118In one embodiment for defining timing parameters, the delay of the circuit

0119includes both the driving instance delay and the RC network propagation delay. As used

0120herein, the driving instance delay is the timing delay exhibited by a circuit (e.g., driver

0121110), and is measured as the time difference between the input of a signal to a circuit and

0122the output of the circuit in response to that input. As used herein, the RC network

0123propagation delay is defined as the signal delay measured from the output voltage of a

0124circuit driver (e.g., driver 110) and the input voltage of a receiver (e.g., receiver 130) as

0125propagated through a wiring interconnect network (e.g., RC network 120). The voltage signals input to a circuit are characterized by input signal slew rate. In general, the input signal slew rate measures the rate at which the voltage rises from

012610% of V_dd to 90% of V_dd or falls from 90% of V_dd to 10% of V_dd. For the example in Figure 1, the driving instance delay is the time delay exhibited by driver 110 to propagate a signal as measured by the time difference required to generate a voltage, V_d, at the

0127output of driver 110 from an input voltage in input vector 105. The gate level circuit

0128(e.g., driver 110) may include one or more inputs. The input vectors represent the

0129combinations of different inputs states. The example of Figure 1 has only one input

0130signal that transitions from 0 to 1 or from 1 to 0, thereby causing the output signal to

0131switch from 1 to or 0 to 1, respectively. For the simplified driver circuit of Figure 1,

0132which includes only one input, input vectors 105 include one input waveform that

0133transitions from a low logic level to a high logic level, and a second input vector that

0134transitions from a high logic level to a low logic level. As described below in conjunction

0135with Figure 2, the circuit may include multiple inputs, and the input vectors may include

0136different combinations of signal transitions for the multiple inputs.

0137The signals in the input vectors 105 are characterized, in part, by input signal slew

0138rates. In one embodiment, the signals of input vectors 105 drive the driver circuit 110

0139with one or more predefined input signal slew rates. Those input signal slew rates are

0140typically generated from the output stage of another circuit that drives driver circuit 110.

0141Figure 2 illustrates another embodiment for characterizing timing parameters in an

0142integrated circuit. A circuit 200 includes a standard cell 210 coupled to a standard cell

0143230 through IC interconnect network 220. The IC interconnect network consists of wires

0144deposited on one or more metal or polysilicon layers of an integrated circuit. The

0145standard cells (210 and 230) implement one or more "gate level circuits." As is well known, the "gate level circuits" may include circuits that employ buffers, memory, logic

0146gates, flip-flops, clock circuits, etc. As shown in Figure 2, input vectors 240 are input to standard cell 210 to drive the one or more logic circuits implemented in the standard cell. Although shown in Figure 2 as a single combination, the input vector 240 includes a "series" of input signal combinations for the logic circuits, as appropriate. Also, the

0147circuit may be characterized with multiple input vectors, such that different input vectors

0148have different input signal slew rates. The driving instance delay for standard cell 210 is

0149measured from the voltage signals of the input vectors 240 that drive the standard cell 210

0150to the output drive voltages, labeled V_dι ... V_dn on Figure 2. The RC network propagation

0151delay for circuit 200 is measured from the output drive voltages, V_dl ... V_dn, which drive

0152the IC interconnect network 220, to the input receiver voltages, V_rl ... V_rn of the standard cell 230. In one embodiment, the EDA software generates timing parameters for an

0153integrated circuit on a "net" by "net" basis. The circuit 200 of Figure 2 depicts a single

0154net.

0155Variable Current Source Model:

0156The present invention utilizes a variable current source to determine timing and

0157power parameters. The effective current, output from a circuit under analysis, is

0158determined for multiple time intervals. In turn, this effective current is used to drive the

0159RC network at each time instance. The response of the RC network for a given current,

0160I_ef , gives the voltage changing at the driver point, which, in turn, yields a new effective

0161capacitance for the RC network at each time interval. Based on the new effective

0162capacitance and voltage at the driver point, a new effective current is determined and

0163applied to the RC network. As described more fully below, the current, which varies at

0164each time interval, drives the RC network and affects the equivalence capacitance of the RC network as seen from the driving point. For purposes of nomenclature, the term "dynamic capacitance" refers to the equivalent capacitance of the RC network at each time interval (i.e., the capacitance is dynamic because it changes based on the current

0165charging and discharging of the RC network and the voltage changing at the driving point of the RC network). For the example of Figure 1, the effective current, 1_, is computed for the driver circuit 110 at each time interval. In turn, this effective current is used to drive

0166the RC network at each time instance, and an effective capacitance is calculated at each

0167time instance.

0168Figure 3 A illustrates a circuit that models the variable current source at a first time

0169instance. At shown in Figure 3A, a first current, I_1} for circuit 300 generates an effective

0170current, I_eff, for a capacitance 305. The capacitance 305 represents the equivalent

0171capacitance of an RC network (e.g., interconnect network in an integrated circuit). The

0172first current, Ii, represents the current at a first time instance. In one embodiment, the

0173current, Ii, is determined by characterizing a driver circuit. For example, the current, I_ls

0174may be characterized based on an input voltage to the driver circuit.

0175Figure 3B illustrates a circuit that models the variable current source at a second

0176time instance. At shown in Figure 3B, a second current, I₂, for circuit 320 and the first

0177current, I_ls are combined to generate an effective current, l_eft, for a capacitance 310. The

0178second current, I , reflects the changing of the current applied to the RC network at the

0179second time instance. Figure 3C illustrates a circuit that models the variable current

0180source at time instance "n." For time instance "n", the effective current is a sum of the

0181previous currents, 1_\ to I(_n-i), applied to the RC network at each time instance to generate a

0182new effective current, I_eff- One or more of the current may be a negative current (i.e.,

0183current flowing in the opposite direction). The new effective current is applied to the new capacitance 340, and voltage at the driving point is calculated based on the current applied to the RC network and the impedance.

0184As illustrated in the example of Figures 3A-C, the iterative technique of calculating current based on the voltage, and thus the changing capacitance, at multiple time instances for a circuit under analysis may be modeled as a variable current source.

0185The variable current source of the present invention accounts for the true behavior of a

0186driver circuit under analysis by considering the non-linear voltage-current (V-I)

0187characteristics of the switching transistors of the circuit. Thus, the variable current source

0188technique accurately captures the resistive shielding of the RC network.

0189Circuit Model Characterization:

0190The techniques of the present invention characterize the voltage and current (V-I)

0191characteristics of driver circuits based on the input signal slew rates and the load

0192capacitances. Figure 4 illustrates an example driver circuit for circuit characterization of

0193the present invention. A driver circuit (inverter) 400 receives, as input, a voltage, Vj_np_ut, and generates, as an output, drive voltage, V_d, and drive current, I_d. Also as shown in

0194Figure 4, the drive voltage, V_d, and drive current, I_d, drive a capacitive load, C_L. The

0195input voltage, Vj_nput, exhibits an input signal slew rate. For the example input voltage of

0196Figure 4, the input signal slew rate is the rate the voltage transitions from a high logic

0197level to a low logic level (e.g., 90% to 10% of V_dd).

0198In one embodiment, the output voltage, VD, is divided into discrete time instances

0199in order to characterize the inverter circuit 400. Specifically, a time difference, referred to

0200as t(delta), is specified to define the time between a plurality of time instances for

0201characterization of the circuit. For example, multiple time instances may be defined for the circuit output voltage, V_D, with the granularity of t(delta), as it transitions from 0 to V_dd. Figure 4 also shows a change in voltage, V(delta), for the elapsed time, t(delta), for

0202the circuit output voltage, V_D.

0203In one embodiment, the EDA software conducts an analysis on gate level circuits (e.g., inverter 400) in order to characterize the circuit for use in timing and power

0204calculations. Specifically, output voltage verses current characterization is defined for

0205multiple input slew rates for input voltages, Vjnput, and multiple load capacitances, C .

0206Figure 5 illustrates a V-I curve for an example gate level circuit. The vertical axis plots

0207voltage, N_d, and the horizontal axis, extending to the left, plots current, I_d. As shown by

0208the example plot in Figure 5, as the voltage, V_d increases from 0 volts, the current

0209increases to a point, label 500 in Figure 5. At point 500, the current begins to decrease as

0210the voltage increases. Figure 5 also plots the voltage, V_d, with respect to time.

0211Figure 6 illustrates a three dimensional graph that depicts the relationship between

0212voltage, V , current, I_d, and load capacitance, C_L. AS shown in the three dimensional

0213graph of Figure 6, the current, Id, is dependent upon both the voltage, V_d, and the load

0214capacitance, C_L- In addition, the current, I_d, voltage, V_d, and the load capacitance, C_L are

0215dependent upon input signal slew rates (not shown). In one embodiment, the data

0216depicted in Figure 6 is generated for multiple signal slew rates. The data depicted in

0217Figure 6 is referred to herein as the "Circuit Model Characterization Data." The Circuit

0218Model Characterization Data for multiple signal slew rates is referred to herein as a

0219library of the Circuit Model Characterization Data. The EDA software of the present

0220invention generates Circuit Model Characterization Data for each input to output pin pairs

0221for gate level circuits employed in an IC design under analysis. In one embodiment, the EDA software utilizes SPICE or HSPICE to generate the Circuit Model Characterization Data. For this embodiment, the gate level circuit is simulated, using HSPICE software, to generate the V-I relationships for multiple input

0222signal slew rates and multiple load capacitances. Although the present invention is

0223described using HSPICE to generate the Circuit Model Characterization Data, any circuit simulation technique may be used without deviating from the spirit or scope of the

0224invention.

0225Numerical Analysis for Computing Voltage. Current & Effective Capacitance:

0226Figure 7 is a flow diagram illustrating one embodiment for generating timing

0227parameters using the variable current source model of the present invention. The circuit

0228under analysis is characterized, so as to extract the voltage-current (V-I) characteristics for

0229the circuit based on an input slew rate (block 700, Figure 7). In one embodiment, the

0230input slew rate is defined from the previous net calculation for a "net" that drives the

0231circuit under operation. A granularity of time, t(delta), is selected to execute the process,

0232and the time, T, is set to zero (block 705, Figure 2). The process is initialized by setting

0233the voltage, V_d(0) and the effective capacitance, C_ef(0), to extract an initial current for the

0234iterative process (block 710, Figure 7). A current, I_d(T), is extracted from the circuit

0235model characterization data based on the voltage, Vd(T-t(delta)), and the effective

0236capacitance, Cef (T-t(delta)) (block 720, Figure 7). For the first iteration, the current,

0237I_d(T), is extracted based on the initial voltage, V_d(0) and initial effective capacitance,

0238C_eff(0). As discussed above, the circuit model characterization data identifies a current, I_d,

0239for a corresponding V_d, C_eff, and input signal slew rate for the circuit under analysis. The RC network under analysis is reduced for computation purposes. In one

0240embodiment, the RC network is reduced to a network response function (e.g., transfer

0241function) representation, G(s), for the corresponding RC network. Also, the impedance of RC network at the driving point, Z(s), is computed. The RC network response at the driving point is described more fully below in conjunction with a discussion of Figure 8, and the RC network response at the receiver point is described more fully below in

0242conjunction with a discussion of Figure 9. The new current, I_d(T), for the new time

0243instance, T, is applied to drive the RC network (block 720, Figure 7). From the RC

0244network impedance at the driving point, Z(s), the V_d., for time T, is computed using the I_d

0245for time T as follows:

0246Vd(s) = I(s) * Z(s)

0247(block 740, Figure 7). From the new voltage, V_d, for the time instance at time T, the

0248process calculates an effective capacitance, C_eff(T), using the current, I_d(T), the voltage,

0249V_d(T) and the time of the instance, T (block 750, Figure 7). Specifically, the effective

0250capacitance, C_eff(T), is calculated from the expression:

0251Id(T) = Vd(T) * Ceff(T)/T

0252Ceff(T) = Id(T) * T/Vd(T)

0253The new effective capacitance Ceff(T), combined with the voltage, Vd, at the

0254driving point, affects the new effective driving current. The calculated voltage at the

0255driving point of the RC network is applied to the network transfer function, G(s).

0256Specifically, to calculate the timing delay (i.e., RC network propagation delay) for the

0257circuit and RC network under analysis, the voltage at the receiver, V_r(T), is calculated

0258from the voltage at the driver output, V_d(T), using the RC transfer function G(s) as

0259follows: Vr(T) = Vd(T) * G(s)

0260(block 760, Figure 7).

0261The process is repeated using the new current to drive the RC network to obtain a new voltage and a new effective capacitance. If the driver output voltage, V_d, for the next

0262time instance, T, is greater than the target voltage level (e.g., Vdd/2), then the process is

0263complete (i.e., all the necessary parameters have been calculated to compute the timing

0264delay and power consumption) (block 780, Figure 7). Alternatively, if the driver voltage,

0265V_d, for the next time instance, T, is less than or equal to the target voltage level (e.g.,

0266Vdd/2), then the process calculates a new time from the relationship T = T + t (delta),

0267where T is the time accumulated for the time instance, and t(delta) is the time increment

0268for the process. The process begins the next cycle by extracting, from the circuit model

0269characterization data, a new I_d(T) based on the drive voltage and effective capacitance

0270from the previous cycle (i.e., V_d(T-t(delta)) and C_eff(T-t(delta)) (block 720, Figure 7).

0271With the new current, I_d(T), a new drive voltage, V_d(T), is calculated (block 740, Figure

02727); a new effective capacitance, C_eff(T), is calculated (block 750, Figure 7); and a new

0273receiver voltage, V_r(T), is calculated (block 760, Figure 7).

0274The process of Figure 7, which includes, for each iteration, extracting current

0275based on voltage and capacitance for an input signal slew rate, results in an operating

0276curve for the gate level circuit and RC network under test. For example, Figure 6 depicts

0277the relationships between V_d, I_d and CL for an input signal slew rate. Using this Circuit

0278Model Characterization Data, the process of Figure 7 selects points on the V l-C

0279coordinates to characterize the operation of the gate level circuit driving the RC network. Figure 8 illustrates an RC network impedance for use in determining the timing

0280parameters of the present invention. The RC network impedance 800 is reduced to the function Z(s). Specifically, the function Z(s) is the impedance, both real and complex, as

0281seen from the input of the RC network. As shown in Figure 8, the voltage, V_d(s), is

0282measured from the driving point of the RC network, and the current I_d(s), is measured as

0283the current flowing into the input of the RC network.

0284Figure 9 illustrates an RC network transfer function for use in determining the

0285timing parameters of the present invention. The RC network transfer function 900 is

0286reduced to a transfer or response function, G(s). The G(s) represents the voltage

0287propagation through the resistance, capacitance and inductance of the RC network.

0288Specifically, the transfer function, G(s), defines the output voltage, Vr(s), based on the

0289input voltage, Vd(s), for a specified time, T.

0290Dynamic Capacitance:

0291The techniques of the present invention capture "dynamic capacitances" as the

0292variable current source charges the RC network. In one embodiment, the dynamic

0293capacitance may be calculated for each time instance (i.e., each stage of the iterative

0294process). The dynamic capacitance, C_d, may be defined by the expression:

0295<img file="EP1292906A2_D0001.tif" />

0296Where,

0297C_d is the dynamic capacitance,

0298Ij is the driver current in each step,

0299Tj is the time in each step, and

0300V is the voltage. Timing Delay Calculations:

0301The variable current source technique has applications for calculating timing

0302delay. For the embodiment of Figure 7, the receiver voltage, V_r(n), is calculated for each step. To calculate the timing delay, including the driving instance delay and the RC network propagation delay, the time difference between the input voltage to the gate level

0303circuit (e.g., Vj_nput in Figure 4) and the input voltage to the receiver, Vr, is computed. In

0304this manner, a timing delay calculation is determined for each net based on the time

0305difference between the input set of vectors to the gate level circuits and the corresponding

0306input sets of voltages at the receiver.

0307Power Calculation:

0308The present invention has application for calculating power consumption in an IC

0309design. As discussed above, instantaneous current change is calculated for a design.

0310Using the instantaneous current change, power consumed in the IC may be estimated. For

0311example, average current, I_avg, is calculated as follows:

0312<img file="EP1292906A2_D0002.tif" />

0313The average power, P_avg, is calculated from the average current, I_avg, as follows:

0314¹ p avg = J T-avg *v v

0315The peak power is calculated based on maximum current as follows:

0316peak ^~~ J-max ' Where,

0317Ppe_ak connotes peak power,

0318I_max connotes maximum peak to peak current in the design, and

0319V connotes the voltage in the RC network. Cross Talk &amp; IR Drop Analysis:

0320The present invention also has application for use in cross talk and IR drop

0321analysis. In one embodiment, the EDA software stores information regarding mutual capacitance in a database. Using the current source model of the present invention, the

0322change in current, to either charge or discharge the RC network, is simulated to drive the

0323aggressor net (i.e., the source net for the crosstalk energy) and the victim net (i.e., the net

0324receiving the crosstalk energy from the aggressor net). Using the current source model,

0325delay due to the effects of mutual capacitance, or cross talk, is estimated easily and

0326accurately for different cases.

0327Figure 10A illustrates an example circuit for cross talk analysis from the driver

0328circuits. Using the variable current source techniques of the present invention to simulate

0329current for the gate level circuits, the example circuit of Figure 10A is simulated as the

0330example circuit of Figure 10B. Specifically, in Figure 10B, the gates level circuits 1010,

03311020 and 1030 are replaced with current sources 1060, 1065, and 1070, respectively.

0332Figure 10C illustrates an example circuit for cross talk analysis from the receiver circuits.

0333The variable current source techniques are used to simulate current for the gate level

0334circuits for driving a receiver as shown in Figure 10D. Using the peak-to-peak current

0335value, the noise influence on victim nets is estimated from the total coupling capacitance

0336and the peak current within the signal switch period.

0337The variable current source techniques of the present invention have application

0338for IR drop analysis. Using the driving point current change result, a linear network

0339model is built with resistance and capacitance mesh and sets of variable current sources.

0340For this embodiment, the linear circuit is used in the high level (full chip) IR drop analysis. By adding an instance on the resistive mesh of the power net, the peak drop is estimated from the peak current and total resistance, so the overall drop distribution is

0341drawn easily and accurately. Figure 11 illustrates a circuit model for IR drop analysis.

0342Computer System:

0343Figure 12 illustrates a general-purpose computer system for executing the EDA

0344software for timing and power verification of the present invention. A computer system

03451000 contains a processor unit 1005, main memory 1012, and an interconnect bus 1025.

0346The processor unit 1005 may contain a single microprocessor, or may contain a plurality

0347of microprocessors for configuring the computer system 1000 as a multi-processor

0348system. The main memory 1012 stores, in part, instructions and data for execution by the

0349processor unit 1005. The main memory 1012 may include banks of dynamic random

0350access memory (DRAM) as well as high-speed cache memory.

0351The computer system 1000 further includes a mass storage device 1022, peripheral

0352device(s) 1030, portable storage medium drive(s) 1040, input control device(s) 1070, a

0353graphics subsystem 1050, and an output display 1060. For purposes of simplicity, all

0354components in the computer system 1000 are shown in Figure 12 as being connected via

0355the bus 1025. However, the computer system 1000 may be connected through one or

0356more data transport means. For example, the processor unit 1005 and the main memory

03571012 may be connected via a local microprocessor bus, and the mass storage device 1022,

0358peripheral device(s) 1030, portable storage medium drive(s) 1040, graphics subsystem

03591050 may be connected via one or more input/output (I/O) busses. The mass storage

0360device 1022, which may be implemented with a magnetic disk drive or an optical disk

0361drive, is a non-volatile storage device for storing data and instructions for use by the processor unit 1005. In the software embodiment, the mass storage device 1022 stores the

0362software for loading to the main memory 1012.

0363The portable storage medium drive 1040 operates in conjunction with a portable non-volatile storage medium, such as a floppy disk or a compact disc read only memory (CD-ROM), to input and output data and code to and from the computer system 1000. In

0364one embodiment, the software is stored on such a portable medium, and is input to the

0365computer system 1000 via the portable storage medium drive 1040. The peripheral

0366device(s) 1030 may include any type of computer support device, such as an input/output

0367(I/O) interface, to add additional functionality to the computer system 1000. For example,

0368the peripheral device(s) 1030 may include a network interface card for interfacing the

0369computer system 1000 to a network.

0370The input control device(s) 1070 provide a portion of the user interface for a user

0371of the computer system 1000. The input control device(s) 1070 may include an

0372alphanumeric keypad for inputting alphanumeric and other key information, a cursor

0373control device, such as a mouse, a trackball, stylus, or cursor direction keys. In order to

0374display textual and graphical information, the computer system 1000 contains the graphics

0375subsystem 1050 and the output display 1060. The output display 1060 may include a

0376cathode ray tube (CRT) display or liquid crystal display (LCD). The graphics subsystem

03771050 receives textual and graphical information, and processes the information for output

0378to the output display 1060. The components contained in the computer system 1000 are

0379those typically found in general purpose computer systems, and in fact, these components

0380are intended to represent a broad category of such computer components that are well

0381known in the art. For the software implementation, the EDA software includes a plurality of

0382computer executable instructions for implementation on a general-purpose computer

0383system. Prior to loading into a general-purpose computer system, the EDA software may reside as encoded information on a computer readable medium, such as a magnetic floppy disk, magnetic tape, and compact disc read only memory (CD - ROM). In one hardware

0384implementation, the EDA software may comprise a dedicated processor including

0385processor instructions for performing the functions described herein. Circuits may also be

0386developed to perform the functions described herein.

0387Although the present invention has been described in terms of specific exemplary

0388embodiments, it will be appreciated that various modifications and alterations might be

0389made by those skilled in the art without departing from the spirit and scope of the

0390invention.