Semiconductor memory device

A semiconductor memory device has MIS transistors to constitute a memory cell array. Each of the MIS transistors has a silicon layer (12) in a floating state. Furthermore, the MIS transistor has a second gate (20), a potential of which is fixed in order to control a potential of the silicon layer by a capacitive coupling, in addition to a first gate (13), which forms a channel between a source region and a drain region (14,15) of the MIS transistor. The MIS transistor dynamically stores a first data state in which the silicon layer has a first potential set by impact ionization generated near a drain junction (14) and a second data state in which the silicon layer has a second potential set by a forward current flowing through the drain junction.