Twin monos memory cell and corresponding fabrication method

Presented in this invention is a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit and corresponding fabrication methods. Two aspects are described: i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate (142). The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel.