Semiconductor integrated circuit with reduced leakage current

A combination circuit (11) is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit (13) connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit (11) is set to an operative state by the control signal immediately before the flip-flop circuit (13) operates in response to the clock signal.