Program-controlled unit for simultaneous instruction execution

The present invention relates to a device according to the The preambles of claims 1, 22 and 28, that is, a program-controlled unit having a plurality of instruction execution units for the simultaneous execution of successive Commands of a program to be executed.

Such programmable unit is for example a superscalar processor. Superscalar processors have been many years in a variety of embodiments known and require no further description.

The simultaneous execution of multiple commands of the executed Program work superscalar processors in the same clock speed faster than normal (according to the Von Neumann principle working) processors.

However, the manufacture and operation are of a superscalar Processor also much more complex than it at a normal processor of the case. Among other must several, for example five instruction execution units (Compared to only one instruction execution unit in normal Processors) are provided, but rather required rarely all instruction execution units simultaneously will. This is because only certain commands can run a program at the same time; for example can commands on results of other commands recourse, not along with these other commands be executed. It may happen in extreme cases that of the existing instruction execution units only only is required, and any other by NOP instructions or the like can be placed in a passive state. These other instruction execution units provide in phases, where they are not needed, an unnecessary burden represent: they are not only superfluous, but at such times contribute by their presence and their operation to an energy consumption and heating of the program-controlled Unit and / or of the system containing these in which are higher than would actually be required. This has the consequence that in a superscalar processors in Compared to that in practice, against normal processors achievable performance increase disproportionately large Additional effort is required.

The present invention is therefore based on the object, the program-controlled unit according to the preambles of Claims 1, 22 and 28 in such a way that of the use of such program-controlled units to can reduce driving effort.

This object is achieved according to the in the claims 1, 22 and 28 claimed programmatically Units dissolved.

Drawing the program-controlled units inventive by the fact<ul><li>that an assignment device is provided which Commands to be executed regardless of their respective Position within the same time to be executed Commands comprehensive instruction sequences any instruction execution units may assign the implementation,</li><li>that the commands to execute a program memory retrieved and provided in a in the program-controlled unit, several independently writable and written readable memory blocks comprising latch be, and / or</li><li>that the programmable unit befehlbar by a command is an intermediate memory in which to execute the Commands after being read from a program memory are cached, or a particular Part of this buffer for a certain time or until the occurrence of a particular event is not to override.</li></ul>The fact that the program-controlled unit as claimed one having working assignment device, allows<ul><li>that in the program memory in which the program controlled by the Unit program to be executed is stored, Only the commands for those instruction execution units are stored, actually to run the program are required, and</li><li>in the definition of the commands executed together to be, no consideration has to be taken out, that a command be a jump destination of a jump instruction can, the first instruction of the same to be executed Commands comprehensive instruction sequence is.</li></ul>This allows the program memory can be made smaller or accommodate a more extensive program, and have less Data is read out from the program memory. this has the positive effect that the program-controlled unit without Loss of performance of the same small and simple can be constructed, consumes less power, and generates less heat.

The fact that the instructions to be executed in a Latches are written, the more independent from each other writable and readable memory blocks comprises, makes it possible that the data stored in the buffer memory Commands in an existing once instruction fetch unit the programmable unit of several subjected commands simultaneously occurring preprocessing can be. This proves, for example, but not exclusively as advantageous because no time Delay a previously not or only partially fixed Assignment of instructions to the instruction execution units, which will execute the instructions, can take place.

That the programmable unit befehlbar by a command is an intermediate memory in which to execute the Commands after being read from a program memory are cached, or a certain part of Buffer for a certain time or until the occurrence of not to overwrite a particular event, makes it possible that the number of accesses to the program memory is minimized.

Through the above measures can be the expense of the Preparation and operation of programmable units, the successive commands of an executed Program can run at the same time, are driven must hold less than is currently the case.

Advantageous developments of the invention are in the dependent claims, the following description and the figures removable.

The invention is described using an exemplary embodiment explained in more detail with reference to the figures. It show<dl tsize="8"><dt>figure 1</dt><dd>the basic structure of the described below program-controlled unit,</dd><dt>figure 2</dt><dd>an illustration of the consideration in the program-controlled Unit to use next command Abarbeitungs pipeline,</dd><dt>figure 3</dt><dd>a schematic illustration of the allocation of through the considered program-controlled unit to be executed Commands to the existing instruction execution units,</dd><dt>4A</dt><dd>the commands that the program-controlled at the considered Unit for the execution of a sample program are stored in the program memory have to,</dd><dt>4A</dt><dd>the commands in a conventional programmable Unit for the execution of the sample program are stored in the program memory need, and</dd><dt>figure 5</dt><dd>a possible structure of the part of the program-controlled Unit to which the allocator contains, by which the example in Figure 2 illustrated assignment is made.</dd></dl>

In the program-controlled unit described below If it is a digital signal processor having superscalar architecture. However, it is already at this Pointed out here that the described below Special features of the program-controlled unit even when other program-controlled units such as microprocessors Insert or microcontroller with superscalar architecture leave.

The basic structure of the considered programmatically Unit shown in Fig. 1 The considered programmatically Unit comprises a core CORE, a program memory PMEM, a data memory DMEM, a DMA controller DMA, multiple coprocessors COP, and a constant memory DOT, which on in the Figure 1 unspecified buses are connected together.

In the present case is particularly interested in the core CORE. The remaining Components of the program-controlled shown in Figure 1 Unit are of secondary importance: it may be provided outside the program-controlled unit be, or - apart from the program memory PMEM - accounts; Alternatively or additionally, the program-controlled Unit also contain other components.

The Core CORE fetches the commands to be executed from the program memory PMEM and executes them.

carried the fetching and executing the commands to be executed present comprehensive in a four pipeline stages pipeline. The four pipeline stages as shown in Figure 2 is an instruction fetch stage (instruction fetch stage) IF, an instruction decode stage (Instruction Decode stage) ID, a first instruction execution stage (first execution stage) EX1, and a second instruction execution stage (second Execution stage) EX2. It was already at this point Note that there is no limitation thereto; it can be provided more or fewer pipeline stages and / or a different distribution of the command processing made steps to be performed on the pipeline stages will.

includes The Core CORE<ul><li>a the instruction fetch stage IF realized instruction fetch unit,</li><li>corresponding to the number of simultaneously executable instructions Number of the instruction decode stage ID realizing instruction decode units,</li><li>corresponding to the number of simultaneously executable instructions Number of the first instruction execution stage EX1 realized first instruction execution units, and </li><li>corresponding to the number of simultaneously executable instructions Number of the second instruction execution stage EX2 realized second instruction execution units.</li></ul>

For completeness, it should be noted that the core CORE is a core with a dual Harvard Load / Store architecture is.

Such cores are - apart from the detail below described peculiarities - known, so that a Description of further details will be omitted.

The special features of the programmable unit are in example considered in the special training Instruction fetch stage; , in another pipeline structure of which, however, other pipeline stages realized Core components be affected.

The considered program-controlled unit, more specifically the instruction fetch unit of the same is characterized,<ul><li>that an assignment device is provided in it, which the commands to be executed regardless of their respective Position within the same time to be executed Commands comprehensive instruction sequences any instruction execution units may assign the implementation,</li><li>that it has an instruction cache,</li><li>that it is befehlbar by a command, a latch, in which the commands to execute after their cached read from a program memory be, or a certain part of the latch for a certain time or until the occurrence of a specific Event not to overwrite.</li></ul>

These features can be used individually or in any combination are used.

In the example considered<ul><li>includes a command has a length of 20 bits (normal command) or 40 bits (long command)</li><li>is the program memory PMEM in units of 80 bits read, and</li><li>can be performed up to five commands simultaneously, wherein the instructions independently normal commands or long commands can be and up to two load / store instructions (For example, move commands), up to two arithmethisch / logical Commands (eg, Add or Remove And commands) and a branch instruction (for example, a Jmp command) can include.</li></ul>

The comprehensive simultaneously executable instructions Command sequences are referred to as command bundles; the programmable unit performs the executed Commands in units of instruction bundles. Which Commands each include an instruction bundle, is under consideration Example, in the programming and / or in the for example, by a compiler, an assembler and / or a linker success in the implementation of program-controlled for Unit program written in an executable Program set.

The hereinafter called aligners allocator makes it possible that the program-controlled unit from the executed and stored in the program memory PMEM Program only in each case for those instruction execution units contains commands that actually for program execution are required, and for instruction execution units, are not needed, does not contain commands.

This is illustrated by an example in FIG. 3 The arrangement shown in Figure 3 shows the program memory PMEM, and by the numeral MOV1, MOV2, CMP1, CMP2 and BR designated five instruction execution units.

The sake of completeness it should be noted that the instruction execution units MOV1 and MOV2 instruction execution units are to run from the load / store instructions Instruction execution units CMP1 and CMP2 instruction execution units for execution by the arithmetic / logic Commands are, and the instruction execution unit BR a Instruction execution unit for executing a branch instruction is.

In the program memory PMEM are commands INS1, INS2 ... INS12 stored,<ul><li>the commands and INS1 INS2,</li><li>the commands to INS3 INS6,</li><li>the command INS7,</li><li>the commands and INS8 INS9, and</li><li>the commands to INS10 INS12 must be carried out simultaneously in each case, and wherein</li><li>the commands INS1, INS3, INS4, INS8, INS10 and INS11 Load / store instructions are,</li><li>the commands INS2, INS5, INS6, INS7 and INS12 arithmetic / logical commands, and</li><li>the command INS9 is a branch instruction.</li></ul>

The aligners can detect this and assigns the individual commands as shown in Figure 3 at the right time the correct instruction execution unit. Thereon as happens in detail, will be discussed in more detail below.

The aligners eliminates the need to command bundles to use with constant length. The instruction bundles must only one as many instructions as contained for execution the program is absolutely necessary; the inclusion of NOP instructions or the like is not required in each case for the Instruction execution units in the command bundles is - differently than usual - no longer necessary.

Without Aligner the instruction bundles must each one of appropriate number of existing instruction execution units include number of commands, since the assignment the instructions contained in the instruction bundles to Instruction execution units according to the position of carried out relevant instructions within the instruction bundles. That is, the first instruction of an instruction bundle is always by run a certain first instruction execution unit, the second instruction of each instruction bundle is always performed by a certain second instruction execution unit, the third instruction of an instruction bundle is always performed by a specific third instruction execution unit, etc.

By providing an aligner therefore reduces the Number of instructions stored in the program memory PMEM Need to get out of this and. This is exemplified in Figures 4A and 4B illustrates that a comparison of the commands, with or without provision of the aligner stored in the program memory PMEM and retrieved from this Need to become. It is illustrated in Figure 3 Example basis.

Figure 4A illustrates the contents of the program memory PMEM for the case that the above-described by the Aligner performed flexible assignment of commands to the Instruction execution units takes place; FIG 4B illustrates the content of the program memory for the PMEM Case that one of the position of the commands in the command Bundles abhängende fixed assignment of commands to the Instruction execution units takes place. Here denote B1 B4 to the respective instruction bundles, and NOP the (NOP) Commands illustrated in the case in Figure 4B additionally stored in the program memory and, for this PMEM Need to get.

As is apparent from Figures 4A and 4B, the number the PMEM to be stored in the program memory and from this to be fetched commands by the provision of an aligner reduced in the present example to less than half will.

This has the positive effect,<ul><li>that the program memory can be reduced PMEM and / or more extensive programs stored in this may be, and</li><li>that read less data from the program memory PMEM Need to become.</li></ul>

Further, it enables the provision of an aligner that the Jump target contained in the program jump commands any may command within a command bundles; without aligners may jump only on the respective first command an instruction bundles done. This difference allows a more efficient use of the instruction execution units: it is not necessary, a command together could be carried out with the previous commands, because the fact that it is a possible jump target is to move to the next instruction bundle, and thus only later perform as if it were theoretically possible.

Figure 5 shows the basic structure of the part of the program-controlled Unit, through which the executed fetched instructions from the program memory and PMEM Instruction execution units are assigned.

The arrangement shown is the instruction fetch unit or part thereof and includes a read unit RU, an instruction cache IC, an instruction-mapping unit IM, a Long instruction detecting means LWD, a p-bit logic PBL, and a control unit CTL.

Although this is still evident from the following explanations will emerge, the sake of completeness already noted at this point that the consideration of the program-controlled Unit aligners particular interest, through which to be executed by the programmable unit Commands individually each instruction execution units can be assigned, by the Instruction mapping unit IM, the long instruction-sensing device LWD, the p-bit logic PBL, and parts of the control unit CTL is formed.

The control unit CTL has several tasks. A first object is that they the fetching instructions from the Program memory PMEM controls. For this purpose, they are to the program memory PMEM the address Adr from, from which data to be read, and controls the (readout inducing) Read unit RU. A second object of the control unit CTL is that they assign the commands controls the instruction execution units. generated purpose it by evaluating information provided to it by the long instruction-sensing device LWD supplied and the p-bit logic PBL be, and other information that they themselves extracted from the commands, the mapping-setting data and outputs it to the mapping practically realizable Instruction mapping unit IM. The control unit CTL can or must also meet other objectives; hereupon will not be discussed in detail herein, however.

The read unit RU is a program to the memory PMEM Read signal Rd from when data is read out from this to, and causes which thereupon from the program memory taken PMEM output data in the instruction cache IC will. The read unit RU is the example under consideration by a Moore machine or - even better - by a Mealy automaton formed.

The instruction cache has the example under consideration a Storage capacity of 16 20-bit words (16 Normal commands) and is divided into several (in the example considered in four equal) blocks divided, each block as a cyclic Buffer is formed, and wherein the individual Blocks independently of one another and, if required, at the same time are written to and read.

The long instruction detecting means LWD checked whether the fetched from the program memory PMEM commands Run commands or long-commands, and outputs the result to the control unit CTL from. Whether a long command is present, can be in representing the example considered, in certain bits of the commands Data seen. This check is performed to Avoid delays preferably already during the Writing the instructions in the instruction cache IC. The from the program memory PMEM output data is in this case not only the instruction cache IC, but also the long-instruction detection device LWD supplied. The results Verification provides the example under consideration in the long-instruction detection device LWD stored until the control unit CTL requires the information in question.

The P-bit logic PBL examines the data stored in the instruction cache Commands, specifies which commands a Command bundle includes (what commands together simultaneously perform are), and transmits the result to the Control unit CTL. The commands to a command-Bundle belong, can be in the present example at a certain, hereinafter referred to as the P-bit bit of the Commands data representing seen. This P bit has example considered at the last command of each Command bundles the value 0, and in all other cases, the Value 1; if an instruction bundle with a single command contains, the P bit of this command on to 0. Of course, it would also be possible that the P-bit of the last instruction of an instruction bundle has the value 1, and in all other cases has to 0. It would also be conceivable that the P-bit of each instruction of a first Command bundles having a special value. To avoid of delays caused by the detection and evaluation the P bits could arise, the P-bit logic several working in parallel on sub-units; is present each block of the instruction cache IC own P-bit logical sub-unit assigned.

The control unit CTL also performs self checks at instructions to be executed by. In particular, it notes to which type of command it is the respective commands concerns. In the example considered, it checks whether it is a load / store instruction, an arithmetic / logic instruction, or is a branch instruction. The verification takes place here on the basis of the values ​​of two specific bits the data representing the commands.

Using the control unit CTL then available The information, namely<ul><li>the data obtained from the P-bit logic PBL information which stored in the instruction cache IC command together perform are (where the commands together to be executed are within the instruction cache IC)</li><li>received from the long-command detecting means LWD Information which commands together to be executed Normal commands, and what the commands together to be executed Long commands are, and </li><li>the self-identified information about which types of instructions it is in the run together commands</li></ul>the control unit CTL specify which instruction cache entry assign which command execution unit is.

The result of the decision are the example under consideration Data or signals for controlling the instruction mapping unit IMU existing multiplexers.

The Instruction mapping unit IMU provides the compounds between the instruction cache memory locations in which the commands together to be executed are stored, and the Instruction decode units ago that the instruction execution units, which execute the relevant commands have assigned (upstream) are. This is done under consideration Example by multiplexers. In the present case contains the Instruction mapping unit IMU a number of multiplexers, which is twice as large as the number of existing Instruction execution units. Each multiplexer has at least one of the number of instruction cache memory locations corresponding number of input terminals and an output terminal on. there<ul><li>are the input terminals of each multiplexer with all associated instruction cache memory locations, and</li><li>the output terminals of the multiplexer with each an instruction decode unit, said each Instruction decode unit assigned two multiplexers are,</li></ul>so that via the multiplexer each instruction cache entry are supplied to any instruction decode unit can.

That every instruction execution unit assigned two multiplexers are, is because each of the instruction execution units execute either normal commands or long commands can, and that normally commands a space in Instruction cache IC occupy, and long commands two memory slots the instruction cache IC occupy.

The instruction execution units, for in an instruction bundle no command is present, for the duration of Running this command bundles disabled or get Commands (for example NOP instructions) supplied, or whose Design the proper execution of the executed not affect the program or do not affect can. The latter may occur, for example, that multiplexers of Instruction mapping unit an additional having input terminal connected to a such an instruction storing memory device connected , and in that the multiplexers are driven, that they switch through the input terminal of this supplied data, if an instruction bundle is executed, the for Instruction execution units, which the multiplexer in question are assigned, does not contain any commands.

As previously mentioned, the program-controlled Unit befehlbar by a command, a Intermediate memory in which the commands to execute after cached being read from a program memory be, or a certain part of the latch for a certain time or until the occurrence of a specific Event not to overwrite. This may force be that short loops without a repeated reading the instructions from the program memory of the instruction Cache out run. This has the positive Effect that the number of read accesses to the program memory is minimized. The specified command is preferably already in the instruction fetch unit (for example, in the control unit CTL) decoded and executed; it could be provided to this command as a special type of command lead, which it would be seen easily that it is a special command.

By the above described specificities of the considered program-controlled unit can be - regardless of the details of the practical realization thereof - the expense of the production and operation of the program-controlled Units, the consecutive instructions a program to be executed can run simultaneously, must be driven low holding as has been the case is.

LIST OF REFERENCE NUMBERS

<dl tsize="4" compact="compact"><dt>Adr</dt><dd>Address for PMEM</dd><dt>BR</dt><dd>Instruction execution unit for Branch Commands</dd><dt>CMP1</dt><dd>Instruction execution unit for arithmetic / logic commands</dd><dt>CMP2</dt><dd>Instruction execution unit for arithmetic / logic commands</dd><dt>COP</dt><dd>coprocessor</dd><dt>CORE</dt><dd>Core</dd><dt>CTL</dt><dd>control unit</dd><dt>DMA</dt><dd>DMA controller</dd><dt>DMEM</dt><dd>data storage</dd><dt>DOT</dt><dd>Constant storage</dd><dt>EX1</dt><dd>first instruction execution stage</dd><dt>EX2</dt><dd>second instruction execution stage</dd><dt>IC</dt><dd>Instruction cache</dd><dt>ID</dt><dd>Instruction decode stage</dd><dt>IF</dt><dd>Instruction fetch stage</dd><dt>IN THE</dt><dd>Instruction mapping unit</dd><dt>INSx</dt><dd>commands</dd><dt>MOV1</dt><dd>Instruction execution unit for load / store instructions</dd><dt>MOV2</dt><dd>Instruction execution unit for load / store instructions</dd><dt>NOP</dt><dd>NOP instruction</dd><dt>PBL</dt><dd>P-bit logic</dd><dt>PMEM</dt><dd>program memory</dd><dt>Rd</dt><dd>Read signal for PMEM</dd><dt>RU</dt><dd>Read unit</dd></dl>