Degaussing circuitry

The present invention relates to a Demagnetizing circuit according to the preamble of Claim 1, identified by particular for demagnetization is color picture tubes used.

Color picture tubes must be demagnetized to a to obtain sufficient color purity. For this purpose, a demagnetizing used by the Switching on of the device in a decaying sent mains AC high amplitude. The by the demagnetizing during steady state operation of the Device leakage current flowing to the other hand, as low as possible be in order to limit the power dissipation.

In conventional demagnetization circuits is to Achieving the decreasing amplitude of the AC line current, a in series connected with the demagnetizing PTC resistor ( 'Positive Temperature Coefficient') used. In the PTC resistor is a resistor with a temperature-dependent resistance value, wherein in particular, the resistance value with increasing temperature increases. The resistance value of the PTC resistor is thus when switching of the corresponding device, ie in the cold State is very low, while at operating temperature is much higher.

The use of the PTC resistor is, however, inasmuch disadvantageous in that the during continuous operation each device on the demagnetizing and the PTC resistor flowing residual current a continuous power loss caused approximately 2W. This is especially in standby mode disturbing because just here the input power should be quite amazing. is the case of expensive televisions therefore the demagnetization, ie on the Demagnetizing winding and the PTC resistor flowing Current in continuous operation with additional circuitry (For example by means of a triac or an optocoupler) switched off.

The present invention is based on the object, a to provide degaussing, wherein with little circuit complexity of the desired Current characteristic can be achieved without continuous operation an appreciable power loss occurs.

This object is inventively achieved by a Demagnetizing circuit with the features of claim 1 dissolved. Define the dependent claims advantageous and Preferred embodiments of the present invention.

The invention uses degaussing no PTC resistor but the MOS or bipolar power transistors. With a low drive complexity can thus not only a degaussing with decaying amplitude are generated, but the Degaussing goes all the way to the demagnetization back to zero, so that no after a demagnetization Power loss occurs, which in particular in standby mode is the respective device advantageously.

The transistors via capacitive Circuit means, which in particular in the form of both Transistors jointly provided capacitive Voltage divider, or in the form of two separate capacitive Voltage divider can be configured. It is also in Ideally, the best known in MOS transistors Inverse diode exploited. When using bipolar transistors, are not accompanied by such an inverse diodes are provided, they must be additionally provided.

The envisaged the initially described prior art PTC resistor, by a current limiting Fixed resistor are replaced.

According to an embodiment of the present invention the drive complexity can be further reduced if the Source and gate terminals of the two MOS transistors are joined together so that the Degaussing circuit with purely capacitive Voltage divider can be operated.

According to a further embodiment of the present Invention, a degaussing suggested that the also after switching corresponding device a subsequent operation or Activation of the demagnetization made possible, so that even in the Continuous operation of each device demagnetization can be carried out. This is particularly desirable when the corresponding unit for a long time on Power remains and outside operating hours only on is connected standby.

In this embodiment, a further transistor, especially a small signal transistor, used to being this further transistor to actuate a further Degaussing a corresponding voltage can be applied must, which switches this transistor in the conductive state. This can be done for example by a voltage low in the standby state of the device and in the operating state is high.

The invention is particularly suitable for demagnetization of color picture tubes corresponding televisions. The However, the invention is not limited to this application but may be applied generally everywhere be where demagnetization by means of a Demagnetizing is perform.

The invention will in more detail below with reference to the accompanying drawings based on preferred embodiments explained.<sl><li>Fig. 1 shows the structure of a demagnetization circuit according to a first embodiment of the present Invention,</li><li>Fig. 2 shows various voltage potential profiles, and the course of the degaussing current in which, in Fig. 1 illustrated embodiment,</li><li>Fig. 3 shows the structure of a demagnetization circuit according to a second embodiment of the present Invention,</li><li>Fig. 4 shows the structure of a demagnetization circuit according to a third embodiment of the present Invention, and</li><li>Fig. 5 shows the structure of a demagnetization circuit according to a fourth embodiment of the present Invention.</li><li>In Fig. 1, an embodiment of the present Invention is shown in which for controlling the Degaussing two MOS power transistors are provided.</li></sl>

The degaussing circuit has two terminals AC1 and AC2 on for applying an AC voltage. between the two terminals AC1 and AC2 is a series circuit comprising a first MOS power transistor T1, two resistors R3 and R4 and a second MOS power transistor T2 connected. The resistor R3 serves for current limitation, while the resistor R4 to the ohmic resistance of a replacement for demagnetization provided demagnetizing equivalent. The drain terminals of the two transistors T1 and T2 are shown in Fig. 1 D, the source terminals S and the gate terminals G, respectively.

The two transistors T1 and T2 are each a capacitive voltage divider C1, C2 or C3, C4 driven. The capacitors C2 and C4 are each provided with a Control terminal ST connected, while the capacitor C1 and C3 to the gate terminal G and source terminal S of the Transistor T1 or T2 connects. To the capacitor C1 and C3 is a clamping diode D1 and D2, and a parallel discharge resistor R1 or R2.

With the control terminal ST of the output is a The bridge rectifier BR is connected, the inputs of which the two terminals AC1 and AC2 are connected. Of the Bridge rectifier BR guaranteed that the Control terminal ST exclusively positive mains half waves be applied. To the control terminal ST is also an Electrolytic capacitor C5 whose other end to Mass is connected. This electrolytic capacitor serves to the rectified by the bridge rectifier BR to smooth voltage. Both the bridge rectifier BR as and the electrolytic capacitor C5 form part of a AC adapter, which to the demagnetization as in join shown FIG. 1 is.

The function of the shown in Fig. 1 Degaussing circuit is described below with reference in Fig. 2 first to connect AC1 or the transistor T1 explained. In FIG. 2, the course of about Demagnetizing R4 flowing Degaussing current I1 as well as that shown in Fig. 1 Voltage potentials V1 and V3 in terms of the terminal AC1 applied mains half cycles shown.

When plugging in the power supply of the electrolytic capacitor C5 immediately charged to the peak value of the mains voltage. At the next zero crossing of the mains voltage is the Transistor T1 first conductive because between the through the Source terminal S of the transistor T1 and the positive pole of Electrolytic capacitor C5 lying capacitive Voltage divider C1 and C2 of the gate terminal G of the transistor T1 is biased positively relative to the source terminal S. The gate-source voltage Vgs of the transistor T1 is (at Neglecting the effect of limiting diode D1) Vgs = V3 * C2 / (C1 + C2).

The clamping diode D1 protects against exceeding the approved gate-source voltage and ensures regardless of the amount of the respective mains voltage consistent decay to give the Current amplitude of the demagnetization of a Half-wave to the other reduced.

The capacitors C1 and C2 should be dimensioned such that the transistor T1 already at the minimum mains voltage, wherein is to run the respective device, fully controlled by can be.

Now rises during a system half the at terminal AC1 voltage applied to its peak value at reduced the gate-source voltage of the transistor T1, because the Voltage across the capacitive voltage divider C1, C2 decreases. During the maximum power the voltage at terminal AC1 has the Value of the voltage potential V3 at the electrolytic capacitor C5 achieved since the peak value of V3 at terminal AC1 applied voltage. The voltage potential V1 on the other hand does not quite reach the peak value, since the lock transistor T1 shortly before reaching the peak starts. The voltage V1 is stabilized to a value at which the transistor T1 is just kept conducting. The degaussing I1 flows in the forward direction by the current-conducting path of the transistor T1 and on resistors R3 and R4, while the Demagnetization in the reverse direction through the Transistor T2 (by the integrated reverse conducting Inverse diode) flows.

After the peak value of the mains voltage is exceeded lowers the voltage applied to the terminal voltage AC1 again. The voltage V1 reserves initially substantially their Value. Only when the applied voltage at the terminal AC1 less than the voltage V1, the transistor T1 is again fully conductive, and the voltage V1 coincides with the on Terminal AC1 applied from voltage.

The same process is repeated with the next System half-cycle, which in this case, the operation with respect to present at the terminal in the lower voltage AC2 Circuit area, ie in the components T2, C3, and C4 and D2 and R2, happens. The voltage present at terminal AC1 Voltage remains at zero, while the terminal AC2 applied voltage according to a half sine wave changed.

During the subsequent half-cycles to repeat this Operations, except that the capacitors C1 and C3 through the Resistors R1 and R2, gradually discharged. The Voltages V1 and V2 therefore rise less and less far, so that formed by resistors R3 and R4 flowing Degaussing I1 gradually decreases. Especially take the voltages V1 and V2 and the Demagnetizing current I1 as shown in FIG. 2 exponentially AB (in Fig. 2 is merely V1 shown), said Period T of the demagnetization I1 at a 50Hz mains voltage 20ms is. In this manner, with the aid of shown in Fig. 1 of the initially demagnetizing described desired course of the demagnetization I1 achieved.

In Fig. 3 is a simplified embodiment of the present invention.

The resistors in the circuit, ie the current-limiting Resistor R3 and the resistance of the Demagnetizing, are evenly to the top and lower circuit part split (R3 = R4). The source and gate terminals of the two transistors T1 and T2 are connected with each other. for both transistors T1 and T2 a common capacitive voltage divider C1, C2 (with the Capacitor C1 parallel shelled limiting diode D1 and a parallel discharge resistor R1) provided, so that the circuit complexity for the Drive circuit from that shown in Fig. 1 Embodiment is halved.

In FIG. 4 is an embodiment to that shown in Fig. 1 corresponding exemplary embodiment shown, whereby Bipolar transistors are used in place of MOS transistors will. If the bipolar transistors are not already as de MOS transistors included reverse conducting inverse diodes, they have to be additionally provided. For this reason are shown in Fig. 4 additional diodes D3 and D4 with the bipolar transistors T1 or T2 connected. Since bipolar transistors have inherently a limitation of the base voltage, in contrast to FIG. 1 and FIG. 2, at least in Mains voltage narrow area on clamping diodes D1 and D2 can be omitted. The 4 additionally provided in FIG. Resistors R5 and R6 serve as a voltage divider for the Base voltage of the respective transistor T1 or T2.

In Fig. 5 is a demagnetization circuit is shown, even after turning on the mains voltage a subsequent demagnetization permits. With this Circuit is thus also during the operating time of the each device demagnetization possible.

In the embodiment shown in FIG. 5 are the Current limiting resistors R31 and R32 evenly on the split upper and lower circuit part. The gate terminals of the two transistors T1 and T2 are analogous to Fig. 3 connected to each other. The circuit for the Degaussing I1 runs in a corresponding Line half-wave from the first supply voltage terminal AC1 via the first current-limiting resistor R31, the first Transistor T1, the demagnetizing or their ohmic resistor R4, the second transistor T2 and the second current limiting resistor R32 to the second Supply voltage terminal AC2. In the subsequent Line half-wave of the current I1 flows in the reverse direction.

The controller, which of the exponential decay Degaussing I1 ensures there in this Embodiment, only from the capacitor C2, the Discharge resistor R1 and the clamping diode D1. Of the Capacitor C1 does not exist, since the gate-source capacitances of the two transistors T1 and T2 solely by the parasitic input capacitances of these transistors are formed.

In Fig. 5 the sake of clarity neither the Bridge rectifier BR still, the electrolytic capacitor C5 shown. When control terminal ST is used in this Embodiment, a terminal K1 to which the power supply the connection point between the bridge rectifier BR and the electrolytic capacitor C5 is to be connected. Of the Capacitor C2 is in contrast to the preceding then embodiments not directly connected to the Electrolytic capacitor C5 connected, but a additional resistor R7.

The junction of this resistor R7 to the Capacitor C2 is connected via a series circuit comprising a further capacitor C6 and the collector-emitter path a further transistor T3 is connected to ground. Of the Transistor T3 is a small signal transistor, which However, up to 300V must be voltages. At the Capacitor C6 is another discharge R9 parallel switched, in which between the connection point of the Resistors R7, R9 and ground a further resistor R8 is connected.

The function of the shown in Fig. 5 Degaussing circuit is as follows.

In the steady state after the first Demagnetization, ie, after turning on the power are the interconnected gate terminals G of the two MOS field-effect transistors T1 and T2 to the source potential discharged, so that the transistors T1 and T2 lock and no Degaussing I1 flows. The collector of the Transistor T3 is at a voltage slightly lower than the high voltage at the control terminal or on the terminal K1 is. The reduction in the voltage is done by out the resistors R7 and R8 voltage divider formed and ensures that the allowable voltage of the collector Transistor T3 is not exceeded.

Desired at a later date a further Demagnetization are performed, the transistor T3 must by applying an appropriate voltage to the base terminal K2 are switched to the conductive state. When in Fig. 5 embodiment shown, the transistor T3 as an npn transistor thus has a positive voltage to the terminal be applied. This may for example by a voltage happen, the low in the standby state and in Operating state is high. To generate this voltage is especially the switching power supply drive module TDA 16847, comprising of an output of performance measures on which by simple wiring a benefit, but not frequency- and line-voltage-dependent voltage may be generated.

By turning the transistor T3 whose collector is pulled to ground, the so resulting negative Voltage jump is transmitted through capacitor C6, so that the voltage potential at the junction of Capacitors C2 and C6 also almost to the Ground potential drops (since the capacitors C2 and C6 C2 "C6 are selected, the voltage is only slightly capacitively divided down). However, the voltage jump is also the capacitor C2 to the gate terminals G of the two Transistors T1 and T2 transmitted. The gate terminals However, clamped by diode D1 to ground potential. Of the Capacitor C6 is now via the resistor R7 loaded relatively quickly, so that the voltage at Connection point of the capacitors C2 and C6 increases. This Voltage rise is determined by the capacitive voltage divider, by the capacitor C2 and the parasitic gate capacitances the transistors T1 and T2 is formed on the transfer gate terminals G of the two transistors. On Exceeding the permissible gate voltage is determined by the limiting zener diode D1 avoided. The transistors T1 and T2 are now conductive and a running Demagnetization process on how he previously has been described.

The resetting of the drive circuit for a further Demagnetization is done by re-activating the Transistor T3. The charged capacitor C6 is then gradually discharged through the resistor R9. After unloading the capacitor C6 is the circuit again for a new Demagnetization ready.