Integrated circuit with a control circuit for controlling a driver circuit

The present invention relates to an integrated circuit with a connection for a digital signal, with a controllable driver circuit which has an input which is connected to the connection for the digital signal and an output for outputting the digital signal, and with a drive circuit, which has an input for a clock signal, for driving the driver circuit in dependence on the clock signal.

In the operation of integrated circuits, it is often necessary to generate or set a digital signal so that the timing of a switching edge of the digital signal is matched to a timing of a switching edge of a clock signal. For example, the digital signal is generated by an oscillator circuit. The frequency of the signal generated by the oscillator circuit is to be set so that it matches the frequency of the clock signal as the reference frequency, in particular so precisely that an existing phase shift remains the same.

For this purpose, an integrated circuit has, in addition to a connection for the digital signal, for example a controllable driver circuit which is connected to the connection for the digital signal and which is used for outputting the digital signal. The driver circuit is controlled by a control circuit which has an input for a clock signal.

The control circuit can be set, for example, in a certain range on the basis of a reference value, in order in particular to be able to compensate for influences from process fluctuations and temperature fluctuations. This means that in the course of the production of such integrated circuits, the respective reference values ​​are set separately for each of the integrated circuits and thus adapted. For this purpose, the reference value is changed in a suitable manner so that the different influences are compensated for. The control circuit is thus trimmed based on the reference value in such a way that the required signal synchronization is set.

To set the control circuit, the integrated circuit, which is part of an integrated memory, for example, is subjected to a test in this regard. This test is carried out externally, for example, using a test system provided for this purpose. Based on a test result, specifications for setting the control circuit are defined. For this purpose, the switching edges of the corresponding digital signal and the clock signal are compared with one another and compared in time by setting the control circuit. The accuracy that can be achieved is generally limited by tolerances of the test system used and of the entire test arrangement. This can have the consequence that a required product specification of the integrated circuit and thus of the integrated memory is not met.

The object of the present invention is to provide an integrated circuit of the type mentioned in the introduction, in which a time comparison of switching edges of the clock signal and the digital signal at the output of the controllable driver circuit can be carried out with a comparatively high accuracy in a test operation.

The object is achieved by an integrated circuit with a connection for a digital signal, with a controllable driver circuit which has an input which is connected to the connection for the digital signal and which has an output for outputting the digital signal, and with a drive circuit, which has an input for a clock signal, for driving the driver circuit in dependence on the clock signal; in which the integrated circuit has a comparison device which has a first input for the clock signal and a second input which is connected to the output of the driver circuit and which has an output for outputting an output signal; in which the output signal of the comparison device has a first state if a signal transition of the signal at the first input occurs before a signal transition of the signal at the second input; and in which the output signal of the comparison device has a second state if the signal transition of the signal at the first input occurs after the signal transition of the signal at the second input.

Advantageous training and further education are the subject of dependent claims.

A time comparison of the signal transitions or switching edges of the digital signal at the output of the driver circuit and the clock signal is carried out by the comparison device, which is part of the integrated circuit. The output signal of the comparison device indicates which of the signals at the inputs of the comparison device first has a signal transition. The output signal of the comparison device is present, for example, at a connection for an external analysis device. There, the state of an output signal taken from the comparison device is analyzed, whereupon the control circuit can be adjusted in the required manner on the basis of the analysis result.

Since the corresponding signal transitions are not measured and analyzed directly by an external test system when the time comparison of the digital signal and the clock signal is carried out, a higher accuracy of the measurement is achieved. Since the measurement takes place directly on the chip of the integrated circuit, the measurement accuracy is not limited by the tolerance of an external test system and the entire test arrangement.

A corresponding state of the output signal of the comparison device is advantageously stored in the comparison device. As a result, the output signal of the comparison device can be taken over a longer period of time, for example by the external analysis device. The output signal of the comparison device also has a static state, so that interference when the output signal is removed does not significantly falsify the comparison result.

The control function of the control circuit can be set, for example, on the basis of a reference value. So that the reference value only has to be set once, it is advantageous that the reference value is stored in a memory unit of the control circuit. The storage unit then has, for example, programmable elements in the form of laser fuses or electrically programmable fuses. The laser fuses are programmed by a so-called laser cutter to set the reference value.

The integrated circuit is, for example, part of an integrated memory, for example a so-called SDRAM (Synchronous DRAM). So-called DDR SDRAM (Double Data Rate SDRAMs) in particular have comparatively high switching and access speeds. Integrated memories of this type usually have, in addition to a clock signal, which is usually supplied externally, a data validity signal or Data clock signal ("data strobe"), which is present at an external connection, for example for reading data from the integrated memory. This data strobe signal is transferred from the integrated memory to the outside during a read access together with data signals to be output.

The switching edges of the data strobe signal are synchronized with the switching edges of the clock signal by means of a so-called DLL circuit ("delay-locked loop"). For example, the data strobe signal has a switching edge with the clock signal at the same time. The DLL circuit serves as a control circuit for a driver circuit that outputs the data strobe signal that is generated, for example, by an oscillator circuit and is present at the input of the driver circuit. A kind of internal clock signal is thus generated from the external clock signal via the DLL circuit and is applied to the driver circuit. A specific phase shift of the internal clock signal or of the data strobe signal can thus be set in relation to the externally supplied clock signal.

In one embodiment of the invention, the first input of the comparison device is connected to a first setting input of a trigger circuit and the second input of the comparison device is connected to a second setting input of the trigger circuit. The output of the comparison device is connected to an output of the flip-flop. The output signal of the flip-flop indicates which of the signals at the set inputs has a signal transition first.

In a development of the invention, the integrated circuit has a functional unit which is connected to the output of the comparison device and to the control circuit. The functional unit is used to set the control circuit on the basis of the state of the output signal of the comparison device. This makes it possible to set the control circuit using electrical signals, for example. Since the functional unit is part of the integrated circuit, no external connections of the integrated circuit have to be provided in order to carry out an electrical adjustment of the control circuit. In addition, shorter test times can be achieved, since several circuits can be trimmed in parallel. The functional unit can be used, for example, to program electrically programmable fuses that are contained in the control circuit.

In a development of the invention, the functional unit has a self-test unit with which successive states of the output signal of the comparison device can be analyzed. The self-test unit also serves for the gradual setting of the control circuit based on an analysis result. A completely independent trimming of the control circuit is consequently possible by means of the self-test unit. The self-test unit is implemented according to the principle of the "built-in self-test" (BIST). The test time of several integrated circuits to be tested can thereby be shortened considerably. Control circuits of several integrated circuits can be trimmed in parallel.

The invention is explained below with reference to the figures shown in the drawing. Show it:<dl id="dl0001"><dt>Figure 1</dt><dd>one embodiment of the invention,</dd><dt>Figure 2</dt><dd>an embodiment of the comparison device.</dd></dl>

FIG. 1 shows an embodiment of the integrated circuit according to the invention, which is arranged on a semiconductor chip 1. The integrated circuit is contained in a memory circuit of the DRAM type, for example in a DDR SDRAM. The integrated memory has a clock signal CK or a complementary clock signal CK, which is supplied via an external connection. The memory also has a so-called data strobe signal DQS, which is transmitted externally via an external connection together with data signals to be output from the memory. The data strobe signal DQS acts as a data validity signal or data clock signal of the memory for reading out data from the memory.

The integrated circuit also has a drive circuit 3, which is referred to as a DLL circuit. The connection 10 for the signal DQS is connected to an oscillator circuit 9. The control circuit 3 has an input 31 for the clock signal CK or<maths id="math0001" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>CK</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP1136834A2_D0001.tif" /></maths>. The control circuit 3 is used to control a controllable driver circuit 2, which has an input 21 which is connected to a connection 10 for the signal DQS, and an output 22 for outputting the signal DQS. The control circuit 3 generates a type of internal clock signal from the external clock signal CK or<maths id="math0002" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>CK</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP1136834A2_D0002.tif" /></maths> with a certain phase shift compared to this. The driver circuit 2 is thus driven by the internal clock signal. By means of the control circuit 3 or DLL circuit, signal transitions of the signal DQS are coordinated with signal transitions of the clock signal CK or CK, or the signal transitions are synchronized with one another. There is a certain phase shift of the signal DQS with respect to the externally supplied clock signal CK or<maths id="math0003" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>CK</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP1136834A2_D0003.tif" /></maths> adjustable. The signal DQS is transferred from the integrated memory to the outside during a read access together with data signals to be output.

The integrated circuit according to FIG. 1 also has a comparison device 4 which has a first input 41 for the clock signal CK or <maths id="math0004" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>CK</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP1136834A2_D0004.tif" /></maths> and has a second input 42 which is connected to the output 22 of the driver circuit 2. An output 43 of the comparison device 4 is used to output an output signal A. The output signal A has a first state "H" if a signal transition of the signal at the input 41 occurs before a signal transition of the signal at the input 42. Accordingly, the output signal A has a second state "L" when the signal transition of the signal at input 41 occurs after the signal transition of the signal at input 42. The comparison device 4 has a further output 44 which has a signal which indicates the reverse sequence of the signal transitions via corresponding states. Resetting the comparison device 4 is possible with a corresponding signal at a connection 45.

The clock signal CK or <maths id="math0005" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>CK</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP1136834A2_D0005.tif" /></maths> is connected to the input 41 of the comparison device 4 via a differential amplifier 11. The signal DQS is also via a differential amplifier 12 to which a reference potential V_ref is applied to the input 42 of the comparison device 4.

The integrated circuit also has a functional unit 5, which is connected to the output 43 of the comparison device 4 and to the control circuit 3. The functional unit 5 is used to set the control circuit 3 on the basis of the state of the output signal A of the comparison device 4. The functional unit 5 enables the control circuit 3 to be set by means of an electrical signal.

In the control circuit 3, a reference value is stored in a memory unit 8. The control function of the control circuit 3 can be set on the basis of the stored reference value. The memory unit 8 has programmable elements F in the form of programmable fuses. If programming of the memory unit 8 is carried out by the functional unit 5, the programmable fuses F are designed in a suitable manner as electrically programmable fuses.

In a further development of the integrated circuit, the functional unit 5 has a self-test unit 6 for analyzing successive states of the output signal A of the comparison device 4. Using the self-test unit 6, the control circuit 3 can be trimmed independently. It is no longer necessary to take the comparison result via an external connection or perform the setting of the control circuit 3 via an external connection. The self-test unit 6 is suitable for performing a step-by-step setting of the control circuit 3 on the basis of an analysis result.

FIG. 2 shows an embodiment of the comparison device 4. This has a flip-flop 7 with a first setting input 71 and a second setting input 72. The setting input 71 is connected to the input 41 of the comparison device 4, the setting input 72 is connected to the input 42 of the comparison device 4 . The flip-flop 7 has an output 73 which is connected to the output 43 of the comparison device 4. The further output 44 of the comparison device 4 is connected to an output 74 of the flip-flop 7. A reset input 75 of the flip-flop 7 is connected to the connection 45 of the comparison device 4. The output signal at the output 73 of the flip-flop 7 indicates which of the signals at the setting inputs 71 and 72 has a signal transition first. The respective output signal is stored at output 73 until the flip-flop 7 is reset.