ATD generation in a synchronous memory

FIELD OF THE INVENTION

0001The present invention relates in general to memory devices and in particular to interleaved memories, readable in synchronous mode by successive locations with a sequential type of access, commonly referred to as burst mode, and to standard memories read in a random access asynchronous mode with fast access times. The invention can be effectively used in interleaved memory devices, even if not exclusively.

BACKGROUND OF THE INVENTION

0002In a standard nonvolatile memory, a read cycle spans from a request of data by way of the switching of the input address lines to the final extraction of the bits stored in the addressed memory location.

0003In particular, in modern devices, the read circuitry (references, sense amplifiers, etc.) is disabled at the end of each read cycle in order to minimize energy consumption. Therefore the start of a new reading must be triggered by the generation of a suitable signal (Address Transition Detection pulse or briefly ATD) that is generally produced by a circuit sensing a change of the input address.

0004A typical ATD pulse generator is depicted in <figref idref="f0001"><b>Fig. 1</b></figref><b>.</b>

0005The ATD pulse must satisfy fundamental requirements for a correct reading and for satisfying the access time requirements.

0006In fact, independently from the particular architecture of the read circuitry, the ATD must be generated as quick as possible in order to quickly restart the whole analog sensing networks.

0007That is why it is important to generate the ATD immediately after the input buffer of the address bits. In this way, the time required for the address bits to propagate through the decoding circuitry down to select the addressed cells is simultaneously exploited to re-establish the bias conditions for an optimal reading.

0008It should be noticed that the assumption from outside of a new address and the consequent generation of a new ATD before a previous access is finished, causes interruption and suppression of the previously started read cycle and the immediate start of a new read cycle, which thus superimposes to the first one, substituting it.

0009In "burst" memory devices, that is operating a sequential reading, only the first reading, whose address is not predictable, must follow a standard data path. On the contrary, for successive cycles it is necessary to follow a different path.

0010Differently from a standard memory, in a synchronous memory the addresses successive to the first one of random access (asynchronous) are internally generated by a counter incremented by a pulse coherently with the system's clock.

0011In particular, in a synchronous memory device it is necessary to start the sequential reading, successive to the first reading, and synchronize it by internally generating the addresses, updated in a sequential manner. A common ATD pulse generator is unsuitable because the external address lines do not switch (or are not accessible to the memory device) during synchronous read cycles.

0012It is also true that if a generic signal, untied from the internal addresses generation, were used for starting sequential readings, the sensing circuit would become independent from the decoding circuitry, with the risk of anticipating or delaying the start of the reading in respect to the correct selection of the memory cells to be sensed.

0013In order to avoid the problem, at the start of the sequential accesses, the eventual propagation of the internally generated addresses (by introducing an appropriate delay) could be waited for. But in doing so, besides the cost in terms of silicon area requisite of such a delay chain, the control logic of the sense-amp would be greatly complicated because it will be necessary to implement two alternative data streams for the two different kinds random-asynchronous and sequential-synchronous modes of access, respectively.

0014A different solution could be that of placing the ATD generation circuit in cascade of the counter that generates the internal addresses (during the asynchronous reading the counter works as a register, because the internal and external addresses coincide), instead of in cascade of the input address buffer, in order to generate the pulses always at the same point of the control chain, independently of the kind of access in progress.

0015Unfortunately this solution burdens the read path in an opposite manner, because instead of starting the logic chain when a new reading has been acquired (because a change of address having been detected downstream of the input buffers), it is necessary to wait for the propagation of the signals through the latches of the counter, thus increasing the total access time.

0016<patcit id="pcit0001" dnum="US5963504A"><text>US 5,963,504</text></patcit> discloses an integrated circuit memory device designed to perform high speed burst access read and write cycle. A high speed burst mode of operation is provided where multiple sequential accesses occur following a single column address, and read data is output relative to the /CAS control signal. In the burst mode of operation the address is incremented internal to the device eliminating the need for external address lines to switch at high frequencies.

0017<patcit id="pcit0002" dnum="US5696917A"><text>US 5,696,917</text></patcit> discloses an asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component.

OBJECT AND SUMMARY OF THE INVENTION

0018The invention provides a method according to claim 1 and an ATD pulse generator according to claim 4. Preferable further method steps / embodiments are presented in the subclaims.

0019Accordingly, the present invention provides an outstanding solution to the above drawbacks by using an ATD signal even for starting sequential readings, by causing its generation when the start of a new cycle of synchronous readings with sequential access is detected.

0020The most appropriate signal to provide such an information is the increment pulse for the internal address counter. In fact by detecting this increment pulse it is possible to generate a (pseudo) ATD signal, i.e. stimulated by an internal cause and not by the switching of the external address lines, thus starting a new reading.

0021The final architecture maintains the classical structure of ATD generation, with circuits sensing the external address lines (useful for all conventional accesses) and has a block that senses the pulses of sequential increment of an internal address counter and generates the ATD pulses for starting sequential readings.

0022Finally, the two kinds of ATD pulses, a first kind due to external cause and the other kind due to internal cause can be summed by way of a logic output OR gate of the ATD generator.

0023Therefore, the method of the invention for synchronizing the start of sequential readings for a read cycle of a memory in burst synchronous mode, comprises the step of using the increment pulses of the address counter, or of the address counters in the case of interleaved memory devices, as synchronization signals, by generating, after each increment pulse, a dummy ATD pulse, practically undistinguishable from an ATD pulse generated by an effective switching of the input address latches.

0024According to an aspect of the memory architecture of the invention, a ATD pulse generator conventionally sensing the external address lines is used, but modified such to include at least a pulse generator circuit stimulated by an increment pulse synchronized by a respective address counter.

0025According to a preferred embodiment, in the case of an interleaved memory, the method of the invention can advantageously contemplate the fact that the increment pulses are distinct for the counter of one or of another bank of subdivision of the array of cells of the interleaved memory, the so distinct increment pulses producing corresponding distinct dummy ATD pulses for starting sequential readings in the respective subdivision banks of the array of cells of the interleaved memory.

0026An external protocol signal (ALE) or more generally an equivalent command ENABLE for enabling the input latch or latches of acquisition of externally input addresses determines, in function of its logic state, the generation of ATD pulses common to both the subdivision banks of the matrix (array) of cells of the interleaved memory, in case of read cycles in random access asynchronous mode or, according to the invention, the generation of dummy ATD pulses specifically for one or the other subdivision bank of the matrix of cells of the interleaved memory, in case of a synchronous read cycle in burst access.

0027The ALE signal establishes that it is necessary to start a read cycle from an external address. Being such a cycle either the first random cycle of a sequence of burst readings or a generic asynchronous access, the ATD pulse stimulated by the switching of the external address lines is sent to all the banks in the case of an interleaved memory, which will then enable their respective read structures.

0028If the access were purely asynchronous, both banks will terminate the readings, but only the bank effectively addressed by the external address shall output its datum (bank priority being defined by the least significant bit A<0> of the address, as already explained).

0029By contrast, because of the switching back to a low level of the signal ALE, should the read cycle be interpreted as being the first random cycle of a burst sequence, the control logic of the memory will generate a first increment pulse for the address counter of the bank (or banks) that is not in priority, for example the bank ODD, in order to generate the address on which the following (second) reading will be carried out.

0030Using as a stimulation the increment pulse, destined to one or another of the internal address counters, a new dummy ATD pulse is generated to start a new read cycle on the ODD bank, i.e. on the bank whose internal address is being incremented.

0031In this way, the reading on the bank EVEN is left to evolve and by way of a new dummy ATD pulse, following the generation of an internal address counter increment pulse, the reading on the other bank ODD is restarted with the updated internal address.

0032At the end of a first random access cycle (that is only after having output the datum read during the first random access cycle on the EVEN bank) a new increment pulse INC_E, this time destined to the address counter of the EVEN bank on which the reading has just terminated, will be generated.

0033Again, by using the address counters increment pulse, a new ATD pulse dedicated to the bank EVEN will be generated to restart a new reading, while the ODD bank, having acquired priority from the control logic, will be completing the reading cycle as far as to output of the read datum. Basically, by continuing to produce increment pulses alternately for the respective address counters, dedicated ATD pulses are coordinately generated to start the readings on the two banks in an alternate fashion.

BRIEF DESCRIPTION OF THE DRAWINGS

0034The different aspect and advantages of the invention will become clearer through the following description of several embodiments with reference to the attached drawings, in which: <ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001"><b>Figure 1</b></figref> shows a classical structure for generating ATD pulses from the switching of external addresses;</li><li><figref idref="f0002"><b>Figure 2</b></figref> is a basic diagram of the architecture of the invention for generating ATD pulses for synchronous memories;</li><li><figref idref="f0003"><b>Figure 3</b></figref> illustrates graphically the ATD pulse generation processes in the case of a random access and in the case of sequential access (burst);</li><li><figref idref="f0004"><b>Figure 4</b></figref> shows a simplified block diagram of an interleaved memory;</li><li><figref idref="f0005"><b>Figure 5</b></figref> illustrates graphically the dependence between the increment pulses and the generation of internal addresses for the two banks of an interleaved memory;</li><li><figref idref="f0006"><b>Figure 6</b></figref> shows the time evolution of the main signal involved in the ATD pulse generation;</li><li><figref idref="f0007"><b>Figure 7</b></figref> is a diagram of the architecture of the invention according to an alternative embodiment that is particularly effective for interleaved memory devices.</li></ul>

DESCRIPTION OF SEVERAL EMBODIMENTS OF THE INVENTION

0035The basic diagram of the architecture of the invention for a synchronous memory is depicted in <figref idref="f0002"><b>Fig. 2</b></figref><b>.</b>

0036As it can be easily noticed by comparing it to the conventional architecture of <figref idref="f0001"><b>Fig. 1</b></figref><b>,</b> in the case of the architecture of the invention, the increment pulse of the address counter (generically indicated by the signal INC in the conventional diagram of <figref idref="f0001"><b>Fig. 1</b></figref>) is identified as INC_COUNTER, and in addition to the function of incrementing the counter or of the counters of the internal addresses, stimulates, by way of a suitable pulse generating circuit (PULSER), the generation of a "dummy" ATD signal, that at the output constituted by an OR logic gate, results substantially undistinguishable from the ATD pulses produced by the array of pulse generators, PULSE GENERATOR, because of a switching of the registers of external addresses.

0037The block CONTROL LOGIC represents the logic circuit that generates the increment pulse INC_COUNTER, immediately after the detection of a rising edge of a synchronism signal of the synchronous readings, indicated as EXT_CLOCK in the diagram.

0038The functioning of the circuit of the invention of <figref idref="f0002"><b>Fig. 2</b></figref> is diagrammatically depicted in <figref idref="f0003"><b>Fig. 3</b></figref> in the case of a random access (RAND ACCESS) and in the case of a sequential read cycle (SYNC ACCESS).

0039A fundamental advantage of the architecture of the invention consists in making the path of ATD be the same both in case of sequential reading and in case of random access asynchronous readings. In fact, the generation of the ATD pulses takes place during the same logic phase of a reading, that is when the latches that constitute the internal address counter are stabilizing themselves, whether the address is input from outside or it is internally generated through an incrementing of the counter itself. In this way, the same propagation delay of the ATD pulses that would be experienced during a standard random access read cycle is ensured also in case of sequential synchronous reading cycles.

0040Fulfillment of this important condition may be easily verified by looking at the diagrams of <figref idref="f0003"><b>Fig. 3</b></figref><b>.</b>

0041Although such increment pulses could be used ATD pulses for readings successive to the first one, in this case it would be necessary to tie the duration of the ATD pulse, from which depends the timing of the reading and thus the access time, to the duration of the increment pulse, that on the contrary may be dictated by the particular structure and by the characteristics of the internal address counters. As a consequence, the access time would made unduly dependent from the characteristics of the address counters.

0042In interleaved memory devices only the first reading, whose address is not predictable, must follow the standard data path. On the contrary, for cycles successive to the first one, it is necessary to follow an alternative (interlaced) data path to exploit the contiguity condition, i.e. the fact that the successive cell to be read is adjacent to the one currently being read and thus its address is predictable.

0043A simplified block diagram of a typical two-bank interleaved memory is depicted in <figref idref="f0004"><b>Fig. 4</b></figref><b>.</b>

0044In this type of memory devices the matrix is divided into two independent banks, EVEN MATRIX and ODD MATRIX, each one of them having its own read path structure. The read cycles of the two banks may then superimpose to one another though out of phase. While on one of the two banks, evaluation and transfer of the datum to the output is being carried out (OUTPUT BUFFER), on the other bank (by virtue of the fact that the location to be addressed is known) it is possible to start a new reading without waiting for the conclusion of the reading in progress on the first one.

0045By means of a control signal, CONTROL, tied to the external synchronization clock, it is possible to manage the multiplexing in the respective output MUX, alternating the priority from a bank to the other.

0046Therefore, for readings successive to the first one, in order to exploit the contiguity of addresses it is necessary to generate addresses internally by means of the respective counters, EVEN COUNTER and ODD COUNTER, incremented coherently with the system's clock by the respective increment pulses INC_EVEN and INC_ODD.

0047The dependence among the specific increment pulses and the generation (sequential updating) of the internal addresses of the two banks is graphically depicted in <figref idref="f0005"><b>Fig. 5</b></figref><b>.</b>

0048An example of the timing of the main involved signals is depicted in <figref idref="f0006"><b>Fig. 6</b></figref>.

0049According to an alternative and particularly preferred embodiment for interleaved memory devices, the basic diagram of <figref idref="f0002"><b>Fig. 2</b></figref> can be modified as depicted in <figref idref="f0007"><b>Fig. 7</b></figref><b>.</b>

0050It still comprises the classic ATD pulse generation structure based on circuits sensing switchings of the external address lines. The ATD pulses generated by these circuits sensing the external address lines are common for the two banks and are used for all conventional random accesses.

0051Substantially the structure of the ATD pulse generator of <figref idref="f0007"><b>Fig. 7</b></figref> comprises, instead of a single auxiliary pulse generator, two auxiliary pulse generating circuits, EVEN PULSER and ODD PULSER, stimulated by specific increment signals INC_EVEN COUNTER and INC_ODD COUNTER, respectively, for the internal address counter of the EVEN bank and for the internal address counter of the ODD band which generate specific dummy ATD pulses: EVEN_ATD and ODD_ATD for the two banks for interleaved sequential readings.

0052During synchronous functioning, in burst mode, the generation of ATD pulses "from external addresses" is disabled by the presence of the external protocol signal ALE.

0053Also in the case of an interleaved memory, the path of the control signals (starting from the ATD pulse) in case of sequential access reading is the same of that in case of a random access reading. The generation of ATD pulses takes place in the same logic phase of a reading, i.e. when the latches that constitute the internal address counter are stabilizing themselves, whether the address is input from outside or it is internally generated through an incrementing of one or of the other counter. In this way, the same propagation delay of the ATD pulses as in the case of a standard random access read cycle is ensured and this identity of propagation delays solves in a simple and effective manner the problem of ensuring a synchronized start on the two banks of burst access readings without requiring the implementation of any further control logic. Moreover, by virtue of the fact that burst access readings take place through the same mechanisms (starting from the counters increment pulses) and using the same circuits as for random access readings, there is a further guarantee of correctness of the operation and of robustness of the architecture.

0054An additional advantage is represented by the exploitation of the distinct increment pulses for the internal address counters of the two banks. In this way, no further processing is necessary for correctly conveying the dummy ATD pulse to one bank without affecting the other bank. The alternative of generating a common ATD pulse and successively permit propagation only toward the correct bank would require in practice a further control signal for implementing the required multiplexing (for example a priority flag signal).

0055It is thus evident that the concept of using the increment pulses to synchronize the start of sequential readings through the generation of dummy ATD pulses, undistinguishable from the ones generated by a switching of the external address lines, represents altogether an extremely efficient, easy and robust solution for synchronous memory devices and in particular for interleaved memory devices, because it allows the use of the same read control architecture and the same signal hierarchy, independently from the system used to generate the internal addresses and above all from the kind of access that is being used, whether asynchronous or sequential.