Dynamic range extension of a digitiser

Field of the Invention

The invention relates to analog-to-digital converters with expanded dynamic range, and to wideband receivers incorporating such analog-to-digital converters.

Background of the Invention

It is a problem with existing wideband radios in basestations that they include ADCs (analog-to-digital converters) which do not have sufficient dynamic range to simultaneously handle properly the large signal strengths from mobiles which are close to the basestation and the small signal strengths from mobiles which are far from the basestation close to the basestation's cell boundary. Typically, when the signal strength becomes too large, the ADC saturates, and outputs a digital signal which contains no useful information.

Some existing systems attempt to overcome this problem through the use of AGC (automatic gain control) in which a variable attenuator is used to insert a variable loss in the analog signal before it is digitized. Due to the dynamic range required and the lower frequency limit of PIN diode switches, AGC cannot be implemented at baseband, and implementing the AGC at RF (radio frequency) would degrade the noise figure of the receiver unduly. A compromise solution involves using the AGC at the IF (intermediate frequency). Such a solution has at least three problems. Firstly, a significant noise figure degradation results due to the limited amount of gain in front of the variable attenuator. Adding more gain in front of the attenuator is not feasible due to the linearity constraint of subsequent components. Secondly, the overload is easiest detected at the digital side of the ADC. By the time the overload is detected, a finite amount of signal is lost due to ADC overload, and clicks are detected at audio. In addition, data is lost in CDPD (cellular digital packet data) and modem applications. Thirdly, the circuit implementation is complex and costly.

In U.S. Patent No.5,422,643 which issued June 6, 1995 to Chu et al., an ADC with expanded dynamic range is proposed wherein the analog signal is duplicated in a plurality of channels each with a different attenuation or gain inserted. Then, depending upon the amplitude of the signal, a particular channel is chosen such that the resulting compensated signal will not saturate the ADC but will be close to full scale of the ADC. At the output of the ADC, the digitized signal must be adjusted to reflect the attenuation or gain inserted. The circuitry for selecting the particular analog channel is complex and requires complicated calibration procedures. Furthermore, there is no suggestion in Chu et al. that this type of ADC would be appropriate for use in a wideband receiver context.

Summary of the Invention

It is an object of the invention to obviate or mitigate one or more of the above identified disadvantages.

According to a first broad aspect, the invention provides a digitizer with increased dynamic range having an analog input and a digitized output consisting of P-bit samples, the digitizer comprising: a gain(attenuation) stage having N channels, each for applying a respective gain or attenuation to said analog input to produce a respective scaled analog signal, where N is an integer greater than or equal to two; N M-bit analog-to-digital converters, each connected to receive a respective one of said scaled analog signals, each for producing a respective M-bit digital sample of the respective scaled analog signal, where M is the sample bit length of the analog-to-digital converters; a switching circuitry connected to receive as inputs all of said M-bit digital samples, for outputting a P-bit sample as a function of a selected one of the M-bit digital samples, where P > M. Preferably, a selection circuit is provided for selecting the selected one of said M-bit digital samples, preferably in such a manner that at least one of, and preferably all of the various analog-to-digital converters are not operated at or very near their respective full scales. This might for example consist of circuitry which will cause a switch between consecutive analog-to-digital converters when the output of the first of the two consecutive analog-to-digital converters is within a predetermined amount of full scale, such as one dB.

In another embodiment, a wideband receiver is provided which has increased dynamic range due to the inclusion of the above summarized digitizer.

Brief Description of the Drawings

Preferred embodiments of the invention will now be described with reference to the attached drawings in which: <ul id="ul0001" list-style="none" compact="compact"><li>Figure 1 is a block diagram of a conventional wideband receiver;</li><li>Figure 2 is a block diagram of a known digitizer with expanded dynamic range;</li><li>Figure 3 is a block diagram of a wideband receiver according to an embodiment of the invention;</li><li>Figure 4A is a block diagram of a digitizer with expanded dynamic range according to another embodiment of the invention;</li><li>Figure 4B is a block diagram showing details of connections shown in Figure 4A between the analog-to-digital converters and the multiplexer and between the multiplexer and the overload detect circuit;</li><li>Figure 4C is a block diagram of the overload detect circuit appearing in Figures 4A and 4B;</li><li>Figure 4D is a block diagram showing details of connections shown in Figure 4A between the analog-to-digital converters and the multiplexer and between the multiplexer and the overload detect circuit in which 16-bit logic is employed;</li><li>Figure 5 is a block diagram of a digitizer according to another embodiment of the invention;</li><li>Figure 6 is a block diagram of the digitizer of Figure 4A with a specific implementation of the overload detect circuit;</li><li>Figure 7 is a block diagram of another overload detect circuit which might be used in the embodiments of Figures 4A and 4B;</li><li>Figure 8 is a block diagram of another overload detect circuit which might be used in the embodiments of Figures 4A and 4B;</li><li>Figure 9 is a block diagram of a digitizer in which overload is detected on the basis of an unattenuated path; and</li><li>Figure 10 is a block diagram of another overload detect circuit which detects overload on the basis of the unattenuated path.</li></ul>

Detailed Description of the Preferred Embodiments

Referring firstly to Figure 1, a conventional wideband receiver in which AGC is implemented at IF is shown to comprise, connected together in sequence, an RF mixer 10 which has an RF input signal 11, a buffer 12, a filter 14, AGC stage 16, an IF mixer 18, a second buffer 20, a second filter 22, and an ADC 24. The ADC 24 has an output 25 connected to a digital processing block 26 which in turn has an output which controls a gain or attenuation introduced by the AGC stage 16. The problems with such an arrangement have been detailed above.

Referring now to Figure 2, a digitizer disclosed in the above-mentioned U.S. Patent No. 5,422,643 is shown, this figure being a simplified version of Figure 1 of that patent, and includes a scaling bank 30 which applies four different gains/attenuations to a signal received from a signal source 32. The scaling bank 30 produces four scaled signals which are passed to a multiplexer 34 which passes a single one of them to an ADC 36. The four scaled signals are also each passed through four respective analog comparators 38 which have outputs which are fed through a PIP (parallel interface port) 40 and ultimately to a microprocessor 42. The microprocessor 42 makes a selection of which scaled signal to use on the basis of the outputs of the comparators 38 and on the basis of calibration information stored in a RAM (random access memory) 44. In addition, the microprocessor 44 performs some adjustment on the digitized signal produced by the ADC 36 to account for the gain or attenuation in the selected signal. This adjustment is referred to as "compression" or "expansion" in the description, but no details of how this is achieved are provided. As identified previously, this system requires a complex calibration procedure. The need for a plurality of analog comparators, a microprocessor and RAM also makes this implementation expensive and complicated.

Referring now to Figure 3, a wideband receiver according to an embodiment of the invention is shown to include the RF mixer 10, buffer 12, filter 14, IF mixer 18, buffer 20, and filter 22 all as previously introduced with respect to the conventional wideband receiver of Figure 1. In place of the ADC 24 of Figure 1, there is a 15-bit increased dynamic range digitizer 46 provided by an embodiment of the invention. The signal output by the filter 22 and input to the digitizer 46 is referred to as SI. Unlike the receiver of Figure 1, there is no variable gain stage between the filter 14 and the mixer 18. There is no need for a digital processing block for providing a feedback signal to the variable gain stage since the variable gain stage does not exist.

Referring now to Figure 4A, a 15-bit digitizer with increased dynamic range according to an embodiment of the invention is generally indicated by 46 and may, for example, be employed in the wideband receiver of Figure 3 in which case the signal SI output by the filter 22 is input to the digitizer. Alternatively, the digitizer 46 may be used in other digitizing applications where increased dynamic range is required. The digitizer 46 includes a gain(attenuation) stage 50, an ADC stage 52, and a multiplexer stage 54. At the input to the gain(attenuation) stage 50, the input signal SI is split into two paths SI1, SI2 with some type of signal splitter (not shown, well known in the art). The first path SI1 is fed to an amplifier 60 in the gain(attenuation) stage 50, and the second path SI2 is fed to an attenuator 62 in the gain(attenuation) stage 50. The ADC stage 52 comprises a first ADC 64 and a second ADC 66, and the multiplexer stage 54 comprises a multiplexer 58 and an overload detect circuit 59. The amplifier 60 has an output SO1 which is digitized by the first ADC 64 in the ADC stage 52 and passed to a first input A of the multiplexer 58, and the attenuator 62 has an output SO2 which is digitized by the second ADC 66 in the ADC stage and passed to a second input B of the multiplexer.

It is assumed that for the purpose of this example that the ADCs 64,66 produce two's complement 12-bit digital representations of the analog signals they receive. The first bit of such a two's complement representation is a sign bit which is "0" for positive numbers and "1" for negative numbers. The remaining 11 bits will be referred to as the "value" bits. For positive numbers, the remaining 11 bits are a binary representation of the number. Positive numbers run from 000000000001 which represents +1 through to 011111111111 which represents +2047. For negative numbers, the remaining 11 bits are a two's complement representation of the corresponding positive number determined by starting with the binary representation of the positive number, replacing ones with zeros, replacing zeros with ones and adding one. Negative numbers run from 111111111111 which represents -1 through to 100000000000 which represents -2048. The fact that two's complement ADCs are used has an effect on how the overload of the ADCs is detected as discussed in detail below. Other types of ADCs may be used in implementing the invention assuming the appropriate modifications to the overload detection circuitry are made.

It is a property of the ADCs 64,66 that each bit corresponds to 20log₁₀(2) = K = 6.0206 dB. The difference between the gain in the amplifier 60 and the attenuation in the attenuator 62 is selected to be 3xK dB in this embodiment. The two ADCs 64,66 perform analog-to-digital conversion on their respective input signals SO1, SO2 to produce first and second 12-bit digitized signals D1, D2 at inputs A and B of the multiplexer 58. The first digitized signal D1 is a digitized version of the amplified signal SO1, and the second digitized signal D2 is a digitized version of the attenuated signal S02. Subtracting 3xK dB from a signal with respect to another signal has the effect of shifting the value bits of the 12-bit representation three bits towards the least significant bit (LSB). For example, the following 12-bits form a two's complement representation of the number 55: 000000110111. Subtracting 3xK dB from 55 gives 6.875, the integer part of which is the number 6. The following is the two's complement representation of the number 6: 000000000110 which by inspection is the two's complement representation of the number 55 shifted to the right (towards the LSB) by exactly three bits. The same example would apply for negative numbers by simply replacing all zeros with ones and replacing all ones with zeros, and adding one.

Thus the second 12-bit digitized signal D2 is a version of the first 12-bit digitized signal D1 shifted three bits towards the LSB. The overload detect circuit 59 is connected so as to monitor the output D2 of the second ADC 64, and to control through select line 61 an output C of the multiplexer 58 as discussed in detail below.

The connections between the ADCs 64,66 and the multiplexer 58 will be described in further detail with respect to Figure 4B. The two inputs A,B of the multiplexer 58 are 15-bit inputs, labelled A₀ to A₁₄ and B₀ to B₁₄ respectively. The output D1 of the first ADC 64 is labelled D1₀ to D1₁₁, and the output D2 of the second ADC 66 is labelled D2₀ to D2₁₁. At input A, bits D1₀ to D1₁₁ are connected to input bits A₀ to A₁₁. In addition, the most significant bit D1₁₁ of D1 is connected to bits A₁₂,A₁₃,A₁₄ of input A. At input B, bits D2₀ to D2₁₁ are connected to bits B₃ to B₁₄ of input B. The output C of the multiplexer 58 is a 15-bit output labelled C₀ to C₁₄. In addition, bits D2₈,D2₉,D2₁₀,D2₁₁ are connected to the overload detect circuit 59.

When the overload detect circuit 59 detects through an analysis of bits D2₈,D2₉,D2₁₀,D2₁₁ that the first ADC 64 is not saturated, then the A input is selected to be passed through as the multiplexer output C. In this case, bits C₀-C₁₁ of the 15-bit output C will contain data, and bits C₁₂-C₁₄ will always contain bits equal to the sign bit of input A, namely bit All. When input A is selected, there is no noise or error introduced in extending the twelve bit representation of D1 to a 15-bit representation because the three additional bits are known to equal the sign bit of A.

When the overload detect circuit 59 detects that the first ADC 64 is saturated, then input B is selected to be passed through as the multiplexer output C. In this case, bits C₃-C₁₄ will contain data equal to input bits B₃-B₁₄. When input B is selected, there will be noise introduced because the resolution provided by the contents of the three least significant bits B₀,B₁,B₂ will be lost since these bits are unknown. These three bits may be permanently connected to zero (ground 68). This will result on average in a slight underestimate of positive numbers and in a slight overestimate of negative numbers.

The second ADC 66 has an input signal SO2 which is 3xK dB less than that of the first ADC 64, and as such it will not saturate until the default input signal SO1 is at least 3xK dB larger than the nominal ADC saturation level. There are two cases in which the first ADC 64 will saturate and both of these are identifiable by examining the output of the second ADC 66. The input A will be D1₁₁ D1₁₁ D1₁₁ D1₁₁ D1₁₀ D1₉ D1₈ D1₇ D1₆ D1₅ D1₄ D1₃ D1₂ D1₁ D1₀. The B input will be D2₁₁ D2₁₀ D2₉ D2₈ D2₇ D2₆ D2₅ D2₄ D2₃ D2₂ D2₁ D2₀ 0 0 0 and the output C will be C₁₄ C₁₃ C₁₂...C₀.

If the input is positive (B₁₄ = D2₁₁ = 0), then if any of B₁₃ B₁₂ or B₁₁ (D2₁₀,D2₉ or D2₈) are high then A is overloaded, since these would necessarily represent numbers larger that the range of A. Similarly, if the input is negative (B₁₄ = D2₁₁ = 1), then if any of B₁₃ B₁₂ or B₁₁ (D2₁₀,D2₉,D2₈) are low then A is overloaded, since these would represent numbers below the most negative number A can handle. This can be summarized using Boolean logic as follows where OVLD represents the overload state, and is high if A is overloaded and low otherwise: <maths id="math0001"><math display="block"><mrow><msub><mrow><mtext>OVLD = ((D2</mtext></mrow><mrow><mtext>10</mtext></mrow></msub><msub><mrow><mtext> OR D2</mtext></mrow><mrow><mtext>9</mtext></mrow></msub><msub><mrow><mtext> OR D2</mtext></mrow><mrow><mtext>8</mtext></mrow></msub><msub><mrow><mtext>) AND NOT D2</mtext></mrow><mrow><mtext>11</mtext></mrow></msub><mtext>) OR</mtext><mspace linebreak="newline" /><msub><mrow><mtext>( (NOT D2</mtext></mrow><mrow><mtext>10</mtext></mrow></msub><msub><mrow><mtext> OR NOT D2</mtext></mrow><mrow><mtext>9</mtext></mrow></msub><msub><mrow><mtext> OR NOT D2</mtext></mrow><mrow><mtext>8</mtext></mrow></msub><msub><mrow><mtext>) AND D2</mtext></mrow><mrow><mtext>11</mtext></mrow></msub><mtext>)</mtext></mrow></math><img file="EP1111795A2_D0001.tif" /></maths>

An example realization of an overload detect circuit 59 which realizes the above logic is shown in Figure 4C and includes a 3-input OR gate 70 and a 3-input OR gate 72 with inverted inputs, both connected to received D2₁₀,D2₉, and D₂₈ as inputs. Each OR gate 70,72 has an output connected to a first input of a respective 2-input AND gate 74,76, with the second input of AND gate 74 being an inverted input. Bit D2₁₁ is connected to the inverted input of AND gate 74 and to the remaining input of AND gate 76. Both AND gates 74,76 have outputs connected to the input of an OR gate 78. The OR gate 78 produces an output OVLD satisfying the above expressed Boolean logic equation.

The overload detect circuit 59 preferably also includes a hysteresis functional block 72. In the absence of the hysteresis block 72, a high OVLD output would select input B and a low OVLD output would select input A, in both cases through a signal to the multiplexer 58 on select line 61. The hysteresis functional block 72 is provided to avoid a high rate of toggle between input A and input B. A high rate of toggle is undesirable because in a practical realization, the gain (attenuation) difference between inputs A and B may not be exactly 3xK dB, and the variation from this figure will cause spectral splatter. The energy of the splatter can be reduced by holding input B for a fixed amount of time independent of overload duration, for example 1 ms.

In non-saturation conditions, bits C₃-C₁₁ of the bit stream at output C are unchanged when A or B is selected. When the path B is selected, the three least significant bits, bits C₀-C₂, will always contain zeros, and this will translate into a small amount of noise. Thus, in non-saturation conditions, it is preferable to use input A.

In the above embodiment, 15-bit digital representations are produced and as such all subsequent circuitry must be selected to handle 15-bit samples. Preferably, 16-bit samples are produced since 16-bit circuitry is more readily available. Referring to Figure 4D, a version of Figure 4B, is shown which results in 16-bit signals. Input A has an additional input bit A₁₅ which is connected to receive D1₁₁. Input B has an additional input B₁₅ which is connected to receive bit D2₁₁. Output C has an additional bit C₁₅. The overload detect circuit 59 connections do not change.

In the above example, the improved digitizer has divided the input signal into two paths with a gain/attenuation difference of 3xK dB, and it is assumed that 12-bit ADCs are employed. More generally, the improved system may be designed with an arbitrary number, N, of paths each preferably differing in attenuation/gain from each other by multiples of K dB. The overload detect circuit must select the highest gain (least attenuated) path which does not result in an overload of the respective ADC. The ADCs may not necessarily be 12-bit ADCs, but may have some other nominal bit count, M. The number of bits, P, required at the multiplexer will be the nominal ADC bit count, M, plus a number of bits equal to (maximum gain - maximum attenuation)/K dB, where "maximum gain" and "maximum attenuation" are respectively the largest and smallest of the gains (attenuations) inserted in any of the paths. An example of this is shown in Figure 5 where a digitizer which splits an input signal SI into N=five different paths 80,82,84,86,88 is shown. The gain (attenuation) stage adds 2xK dB, K dB, 0 dB, -K dB, -2xK dB of gain (attenuation) in each of the five paths 80,82,84,86,88 respectively. The maximum gain is 2xK dB, and the maximum attenuation is -2xK dB, therefore (2xK - (-2xK))/K = 4 additional bits are required. The gain (attenuation) stage 50 produces five compensated outputs which are passed to five ADCs in the ADC stage 52, each ADC having a nominal 12-bit count. The ADC stage 52 has five digitized outputs connected to input A,B,D,E and F of the multiplexer 58. Since each ADC has a M=12 bit nominal bit count, the multiplexer 58 must handle P = 12 + 4 = 16 bit signals. The digitized outputs are connected to bits 0-11, 1-12, 2-13, 3-14, and 4-15 of inputs A,B,D,E and F respectively. Again, assuming two's complement ADCs, the MSB of the actual signal input at each of A,B,D,E,F will be copied to the remaining more significant bits. For example, the MSB of A will be bit 11 and this is copied to bits 2,13,14 at input A. More generally, the multiplexer has N P-bit inputs each numbered bit 0 through bit P-1, and each ADC is connected to its respective multiplexer input at only M of the possible P bits, namely bit X through bit X + M-1, where X is the lowest numbered bit to which a connection is made, and where X is determined according to:<maths id="math0002"><math display="block"><mrow><mtext>X = maximum gain (lowest attenuation) of any channel -</mtext><mspace linebreak="newline" /><mtext> gain(attenuation) of the particular channel)/K dB.</mtext></mrow></math><img file="EP1111795A2_D0002.tif" /></maths>

Furthermore, for cases where the output samples are to be padded such that a convenient sample size is achieved (for example as shown in Figure 4D) the P-bit output sample forms a subrange of an R-bit output sample, where R&gt;P, with the switching circuitry connecting the R-P most significant bits of the R-bit sample to be equal to the most significant bit the P-bit sample.

The overload detect circuit 59 selects one of inputs A,B,D,E, and F to be passed through the multiplexer 58. If path A is saturated, then path B is checked, and if unsaturated, path B is selected. If path B is also saturated, then path D is checked, and if unsaturated, path D is selected. If path D is also saturated, then path E is checked, and if unsaturated, path E is selected. If path E is also saturated, then path F is selected.

The overload detect circuit identifies whether a particular analog-to-digital converter is saturated by determining whether another analog-to-digital converter whose input is attenuated relative to that of the particular analog-to-digital converter is producing an output which is outside the range of that representable by the particular analog-to-digital converter.

The ADCs used in the digitizer with increased dynamic range may for example be Analog Devices part AD6640 12-bit ADC which has the ability to digitize up to 32 MHZ of spectrum. It has a nominal dynamic range of 72 dB. When used with the embodiment of Figure 4A for example, the dynamic range of the resulting digitizer is increased to 72 dB + ~18 dB ≃ 90 dB.

The AD6640 produces a full scale output with a 1Vpp (volts peak-to-peak) input signal. Referring again to the example of Figure 4A in which two paths are employed with a gain (attenuation) difference of ~18 dB are used, assume that the gains in the two paths are 40 dB and 22 dB respectively. Using two Analog Devices AD6640 ADCs in an increased dynamic range digitizer, an RF input signal having -36 dBm received through an antenna input having a 50Ω input impedance and 40dB voltage gain would result in a 1Vpp full scale signal at the first ADC input. In other words, any signal larger than -36 dBm received by the receiver will result in the first ADC saturating, and in the selection of the second ADC. The second ADC will be able to handle received signals having strengths up to -18 dBm without saturating.

It is noted that since the output of the digitizer with increased dynamic range has more bits per sample than the conventional ADC, subsequent components in the receiver must be selected to handle these larger samples. For example, channelizer functionality may follow the digitization stage, and the channelizer must be designed to accomodate 15-bit samples. This does not entail a re-design, but rather entails simply selecting available off-the-shelf components having the capacity to handle the increased sample size.

In the above described example, it has been assumed that each amplifier or attenuator has a gain equal to an exact multiple of K = 20log₁₀(2). Depending upon the amount of gain or attenuation, there is some tolerance in this value. For the example of Figure 4A in which there is a single path with an attenuation nominally equal to 3xK = 18.0618 dB, the three bit shifting will perform perfectly for any attenuations in the range 18.0533 dB to 18.1901 dB. For attenuations outside these ranges an error will occur when the shift is performed. For example, a perfectly attenuated version of a number normally digitized as 1023 will be digitized as 127, this being 1023 shifted to the right three bits. However, it will be digitized as 126 for attenuations which are too large (above 18.1901 dB), and it will be digitized as 128 for attenuations which are too small (below 18.0533 dB). Thus some care must be taken to ensure that these gains and attenuations are sufficiently accurate.

In another embodiment, assuming that each analog-to-digital converter has an overload pin which indicates when the converter is saturated, overload detect logic can be provided which is connected to receive the overload pin outputs, and to select the output from the first non-overloaded analog-to-digital converter.

Preferably, a overload detect circuit functions in a manner such that the various analog-to-digital converters are not operated at or very near their respective full scales. For example, the overload detect circuitry might be configured to cause a switch between consecutive analog-to-digital converters when the output of the first of the two consecutive analog-to-digital converters is within a predetermined amount of full scale, such as one dB. The benefit of switching at -1 dB full scale is a reduced noise and spurious level in the range of inputs to the ADCs between -1 dB full scale and 0 dB full scale.

There are many ways to configure the overload detect circuit to achieve this function. Several examples will be given for the case where there are two analog-to-digital converters which produce digitized signals D1 and D2 respectively, each of which are easily extended to handle any number of analog-to-digital converters.

In one approach, the overload is measured on signal D2 as in the previous examples, but rather than simply examining the most significant bits, the signal is compared to a digitized value which would indicate D1 is within the predetermined amount of its full scale.

For 12-bit two's complement ADCs: <ul id="ul0002" list-style="none" compact="compact"><li>positive full scale is [0 1 1 1 1 1 1 1 1 1 1 1] = 2047 decimal</li><li>negative full scale is [1 0 0 0 0 0 0 0 0 0 0 0] = -2048 decimal</li><li>-1 dB full scale is A= [0 1 1 1 0 0 1 0 0 0 0 0] positive    B= [1 0 0 0 1 1 0 1 1 1 1 1] negative</li></ul>

Thus if D2 is greater than A, or D2 is less than B, then D1 must be within -1 dB of its full scale, and a switch to D2 should be made. A more general example of this approach is shown in Figure 6 in which an overload detect circuit 100 functions to determine when D2 is greater than C1 or D2 is less than C2, and if either condition is true, to select the attenuated ADC output D2 in the multiplexer 58. The selection of C1 and C2 (equal to A and B in the specific example above) determines how close to full scale D1 is before a switch is made.

In another approach, a constant is added or subtracted from D2 such that activity detected on the three most significant bits is indicative of an overload condition on the first ADC, as in the previously described embodiment of Figure 4B, using the circuit of Figure 4C for example. For 12-bit two's complement ADCs: <ul id="ul0003" list-style="none" compact="compact"><li>positive full scale is [0 1 1 1 1 1 1 1 1 1 1 1] = 2047 decimal</li><li>negative full scale is [1 0 0 0 0 0 0 0 0 0 0 0] = -2048 decimal</li><li>-1 dB full scale is A= [0 1 1 1 0 0 1 0 0 0 0 0] positive    B= [1 0 0 0 1 1 0 1 1 1 1 1] negative</li><li>delta = [0 0 0 0 1 1 0 1 1 1 1 1] is the binary number added to [0 1 1 1 0 0 1 0 0 0 0 0] or subtracted from [1 0 0 0 1 1 0 1 1 1 1 1] to get [0 1 1 1 1 1 1 1 1 1 1 1] and [1 0 0 0 0 0 0 0 0 0 0 0] respectively. Thus the three MSBs on the quantity D2 + delta for positive numbers or D2 - delta for negative numbers are examined, and if there is any activity in the form of ones for positive numbers or zeros for negative numbers, then D2 should be selected. A more general example of this approach is shown in Figure 7 in which an overload detect circuit includes logic 102 functions to add a value C1 to D2 when positive and subtract a value C2 when D2 is negative to produce a value D3, and then includes circuitry identical to that of Figure 4C for controlling when to select D2 on the basis of the most significant bits of D3. The selection of C1 and C2 (both equal to delta in the specific example above) determines how close to full scale D1 is before a switch is made.</li></ul>

In another embodiment, the D2 is multiplied by a constant before examining the most significant bits. For example, multiplying D2 by 1.1225 will result in -1 dB full scale selection of D2. This is shown more generally in Figure 8 where logic 104 is shown which multiplies D2 by a constant K, and then includes circuitry identical to that of Figure 4C for controlling when to select D2 on the basis of the most significant bits of D3. It is noted that multiplication requires more processing power.

In other embodiments in which switching before full scale is to be performed, D1 itself can be examined. In this case, attention must be paid to overflow of D1 which results in the production of nonsense which may or may not indicate overflow. Thus, if D1 is greater than C1 for positive numbers or D1 is less than C2 for negative numbers, or if overflow has occurred, for example as indicated by an overflow pin, then D2 should be selected. An example of this is illustrated in Figure 9 where overload detect circuitry 106 is shown connected to receive D1 from ADC 64, and to receive the output 106 of the overflow pin (not shown) of ADC 64. Similar to embodiment of Figure 7 above where D2 plus or minus a constant was examined, a constant can be added to or subtracted from D1 using logic 110, and the most significant bits of the result examined, as the overload detect circuit depicted in Figure 10. In this case OR gate 78 has a third input 112 consisting of the overflow output from the first ADC 64 such that regardless of the output from logic 110, if ADC 64 has an overflow, D2 from ADC 66 is selected.

Specific examples of overload detect circuitry have been given for determining when to switch between analog-to-digital converters. It is to be understood that these are examples only and that any suitable circuit for selecting which output to us may be employed. These may result in switching between analog-to-digital converters exactly at full scale, or between analog-to-digital converters before full scale occurs.

Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practised otherwise than as specifically described herein.

In the above described examples, it is assumed that two's complement ADCs are used. Of course other types of ADCs such as one's complement ADCs, for example may alternatively be used. This would necessitate changing the overload detect circuit and changing the connections between the ADCs and the multiplexer.

In the above described example, a multiplexer is used to channel one of two inputs through to an output. Of course this would be done using any suitable switching circuitry.

While in the illustrated embodiment, the multiplexer is shown as having P-bit inputs, it is to be understood that it could instead simply have M-bit inputs provided that the appropriate inputs bits are routed to the appropriate output bits depending upon the input selected.