Device with thin-film circuit
Abstract
The invention describes a device equipped with thin-film circuit. to realize the component with thin-film circuit on a substrate (1) made of a insulating material in addition to the strip lines capacitors or capacitors and resistors, capacitors, resistors and inductors using thin film techniques applied already directly onto the substrate. The partial or complete Integration of passive components is provided a component with minimal space requirements.

Term
Term ended
Projected expiry passed 18 December 2020, 5.8 years ago.
- Priority
- Filed
- Published
- Projected expiry
- Today
17 claims: 3 independent, 14 dependent
- 1Bauteil ausgerüstet mit einem Dünnschichtschaltkreis auf einem Substrat (1) aus einem isolierenden Material mit mindestens einem passiven Bauelement, welches wenigstens eine erste strukturierte elektrisch leitende Schicht (2), ein Dielektrikum (3), eine zweite elektrisch leitende Schicht (4) umfasst, einer Schutzschicht (5), sowie mindestens einem Kontaktloch (6), welches das Bauteil durchdringt und einer Metallisierung, welche das Bauteil und das Kontaktloch (6) bedeckt.
- 2Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass zwischen Substrat (1) und erster strukturierter elektrisch leitender Schicht (2) eine Widerstandsschicht (7) aufgebracht ist.
- 3Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass das Substrat (1) aus isolierendem Material ein keramisches Material, ein glaskeramisches Material, ein Glasmaterial oder ein keramisches Material mit einer Planarisierungsschicht aus Glas oder einem organischen Material enthält.
- 4Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 3, dadurch gekennzeichnet , dass das Substrat (1) aus isolierendem Material Al 2 O 3 , Glas oder Al 2 O 3 mit einer Planarisierungsschicht aus Glas oder einem organischen Material enthält.
- 5Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass zwischen Substrat (1) und erster strukturierter elektrisch leitender Schicht (2) oder zwischen Substrat (1) und Widerstandsschicht (7) eine Barriereschicht (8) aufgebracht ist.
- 6Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass die erste und zweite strukturierte elektrisch leitende Schicht (2,4) Cu, Al dotiert mit Cu, Al dotiert mit Mg, Al dotiert mit Si oder Al dotiert mit Cu und Si enthält.
- 7Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 2, dadurch gekennzeichnet , dass die Widerstandsschicht (7) Ni x Cr y Al z (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si x Cr y O z (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si x Cr y N z (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Cu x Ni y (0 ≤ x ≤1, 0 ≤ y ≤ 1) oder Ti x W y (0 ≤ x ≤1, 0 ≤ y ≤ 1) enthält.
- 8Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass das Dielektrikum (3) Si 3 N 4 , SiO 2 , Si x O y N z (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) oder Ta 2 O 5 enthält.
- 9Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass die Schutzschicht (5) ein anorganisches Material enthält.
- 10Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass die strukturierte Metallisierung eine Basisschicht (9) und eine Deckschicht (11) enthält.
- 11Bauteil ausgerüstet mit einem Dünnschichtschaltkreis nach Anspruch 1, dadurch gekennzeichnet , dass auf der dem Dünnschichtschaltkreis entgegengesetzten Seite des Substrats diskrete Bauelemente aufgebracht sind.
- 12Verfahren zur Herstellung eines Bauteiles ausgerüstet mit einem Dünnschichtschaltkreis auf einem Substrat (1) aus einem isolierenden Material mit mindestens einem passiven Bauelement, dadurch gekennzeichnet , dass auf einem Substrat (1) eine erste elektrisch leitende Schicht (2) abgeschieden und strukturiert wird, auf die erste strukturierte elektrisch leitende Schicht (2) ein Dielektrikum (3) abgeschieden wird, auf das Dielektrikum (3) eine zweite elektrisch leitende Schicht (4) abgeschieden und strukturiert wird, auf die zweite strukturierte elektrisch leitende Schicht (2) eine Schutzschicht (5) aufgebracht wird, Dielektrikum (3) und Schutzschicht (5) strukturiert werden, wenigstens ein Kontaktloch (6), welches das Bauteil durchdringt, geschaffen wird und über dem Bauteil und dem Kontaktloch (6) eine strukturierte Metallisierung aufgebracht wird.
- 13Verfahren nach Anspruch 12, dadurch gekennzeichnet , dass als erster Schritt auf dem Substrat (1) eine Barriereschicht (8) abgeschieden wird.
- 14Verfahren nach Anspruch 12, dadurch gekennzeichnet , dass auf das Substrat (1) oder die Barriereschicht (8) zunächst eine Widerstandsschicht (7) aufgebracht und strukturiert wird.
- 15Verfahren nach Anspruch 12, dadurch gekennzeichnet , dass das Kontaktloch (6) im ersten Schritt oder nach Aufbringen der Schutzschicht (5) geschaffen wird.
- 16Verfahren nach Anspruch 12, dadurch gekennzeichnet , dass zur Herstellung der strukturierte Metallisierung zunächst eine Basisschicht (9) über dem Bauteil und in dem Kontaktloch (6) abgeschieden wird, auf die Basisschicht (9) eine Schicht aus Fotolack (10) abgeschieden und entsprechend der gewünschten Strukturierung der Metallisierung strukturiert wird, auf die Basisschicht (9) eine Deckschicht (11) abgeschieden wird und der Fotolack (10) und bestimmte Teile der Basisschicht (9) entfernt werden.
- 17Dünnschichtschaltkreis auf einem Substrat (1) aus einem isolierenden Material ausgerüstet mit mindestens einem passiven Bauelement, welches wenigstens eine erste strukturierte elektrisch leitende Schicht (2), ein Dielektrikum (3), eine zweite elektrisch leitende Schicht (4) umfasst, einer Schutzschicht (5), sowie mindestens einem Kontaktloch (6), welches das Substrat (1) durchdringt und einer strukturierten Metallisierung, welche die Schutzschicht (5) und das Kontaktloch (6) bedeckt.
Independent claims17
51 paragraphs, as filed
0001The invention relates to a component equipped with a thin-film circuit on a Substrate of an insulating material, a method for producing a component with Thin-film circuit and a thin film circuit.
0002The development of many electronic devices is characterized by the following trends: Miniaturization, lower or at least constant prices with increasing functionality, higher reliability and lower energy consumption. The number of passive Components making experience has shown that in many consumer electronic devices, for example, in television sets or video recorders, 70% of the existing components out. But the rapid developments in mobile communications and the constant miniaturization the cordless telephone sets lead to increased demands on the individual Components.
0003A step on the road to continuous miniaturization, the so-called SMD technology form. The basis for this technique miniaturized components (SMDs = surface Mounted Devices) which, directly onto the surface of printed circuit boards or ceramic substrates which are provided with strip lines, are mounted. SMDs are significantly smaller than similar conventionally wired components. With consistent use of can the area or space requirements and weight of circuits halved be up gedrittelt. Also, by optimum use of SMD technology a Cost savings are obtained because smaller printed circuit boards can be used.
0004Using this technique is today also a power amplifier module for the radio frequency unit a mobile phone made. be on a substrate having a Printing striplines applied. The substrate serves as a carrier for active components such as amplifiers and passive components such as resistors, Capacitors and inductors. The active components are thereby as ICs mounted on the substrate by a bonding method and the passive components as SMD components soldered.
0005Through further miniaturization but also the production, handling and installation of passive SMD components more difficult. This can be avoided, integrated passive components (IPCs) are used. In this technique, are passive components such as resistors (R), capacitors (C) or Inductors (L) combined into inseparable basic circuits and systems. By Application of thin-film techniques is obtained with the aid of masks on support plates of an insulating material called thin-film circuits, the very one greatly reduced printed circuit match. The production of thin film circuits is known and is generally carried out by various successive Coating and patterning processes. To a thin film circuit consists of a combination of resistors, capacitors or inductors, to realize, are different layers having different shapes, compositions and thicknesses apply.
0006A simple implementation of circuits with different passive and active Components is achieved with by combining discrete (SMD) components active devices, a specific function (for example a filter function) have. One drawback though is that SMD components are all soldered individually have to. By soldering large areas are required, whereby the circuits be very large.
0007The invention is based on the object, a component with a thin-film circuit with passive components or with active and passive components on a substrate creating of an insulating material having a small space requirement.
0008This object is achieved by a component equipped with a thin-film circuit on a substrate of an insulating material with at least one passive component, which at least<sl><li>a first patterned electrically conductive layer,</li><li>a dielectric,</li><li>comprises a second electrically conductive layer,</li><li>a protective layer,</li></sl>and at least one contact hole which passes through the module and a metallization which covers the module and the contact hole. In this thin-film circuit on a substrate are not only the strip lines, but also at least a passive component such as a capacitor applied. This direct integration of passive components, the entire Thin-film circuit can be realized with significantly reduced space requirements.
0009In a particularly preferred embodiment, between the substrate and the first patterned electrically conductive layer deposited a resistive layer, so that the Thin-film circuit includes at least one resistor.
0010It is preferred that the substrate of insulating material is a ceramic material, a glass-ceramic material, a glass material or a ceramic material with a planarizing layer contains from glass or an organic material.
0011A substrate made of these materials is inexpensive to produce and process costs for this component can be kept low. In this case, the substrate the support for discrete devices and ICs represent.
0012It is particularly preferred that the substrate of insulating material Al<sub>2</sub>O<sub>3</sub>, Glass or Al<sub>2</sub>O<sub>3</sub> includes a planarization layer of glass or organic material.
0013These materials are thin-film technology compatible and have an acceptable surface roughness on. Especially Al<sub>2</sub>O<sub>3</sub> characterized by its mechanical stability and thermal conductivity as a substrate.
0014It is further preferred that between the substrate and the first structured electrically conductive layer or between the substrate and the resistive layer, a barrier layer is applied.
0015A barrier layer reactions with the dielectric and rough surfaces can the electrically conductive layers, or to short-circuits of the capacitors bad high-frequency characteristics result, are avoided.
0016It is advantageous that the first and second patterned electrically conductive layer Cu, Al doped with Cu, Al doped with Mg, Al doped with Si or Al doped with Cu and Si.
0017It is also preferable that the resistance layer of Ni<sub>x</sub>Cr<sub>y</sub>Al<sub>z</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si<sub>x</sub>Cr<sub>y</sub>O<sub>z</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si<sub>x</sub>Cr<sub>y</sub>N<sub>z</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) Cu,<sub>x</sub>Ni<sub>y</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1) or Ti<sub>x</sub>W<sub>y</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1).
0018These materials are, after deposition, for example by means of lithographic Processes associated with wet and dry etching steps in accordance with the feature that the should fulfill layers in thin-film circuit, structured.
0019It also advantageous that the dielectric Si<sub>3</sub>N<sub>4</sub>, SiO<sub>2</sub>, Si<sub>x</sub>O<sub>y</sub>N<sub>z</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) or Ta<sub>2</sub>O<sub>5</sub> contains.
0020All these materials have a relative dielectric constant ε<sub>r</sub> > 4 and to allow so high capacitance values in small dimensions.
0021It is preferred that the protective layer contains an inorganic material.
0022The protective layer protects the underlying layers from mechanical changes and corrosion by moisture.
0023Furthermore, it is preferred that the structured metallization a base layer and a Topcoat contains.
0024In this embodiment, the base layer acts as a seed layer for electrodepositing the top layer of the structured metallization.
0025It very particularly preferred that on the thin-film circuit opposite Side of the substrate discrete components are applied.
0026Through these components on both sides of a wafer, the packing density can be further increased will.
0027Furthermore, the invention relates to a method for producing a component equipped with a thin-film circuit on an insulating substrate having at least a passive component, in which<sl><li>on a substrate a first electrically conductive layer is deposited and patterned becomes,</li><li>on the first structured electrically conductive layer, a dielectric is deposited,</li><li>deposited on the dielectric layer and a second electrically conductive structure becomes,</li><li>on the second patterned electrically conductive layer, a protective layer is applied, dielectric and protective layer to be structured,</li></sl>at least one contact hole which passes through the module, is created and the component and the contact hole a patterned metallization is applied.
0028In a particularly preferred embodiment, the first step on the substrate a barrier layer deposited.
0029In a very particularly preferred embodiment, on the substrate or on the Barrier layer is first applied a resistive layer and structured.
0030It is further preferred that the contact hole of the first step or after application Protective layer is created.
0031Depending on the manufacturing process, the contact hole can create by applying the protective layer be or already before by thin film techniques, the strip lines and passive integrated components are applied.
0032It is preferred that for producing the structured metallization firstly a base layer to the component and is deposited in the contact hole,<sl><li>on the base layer, a layer of photoresist is deposited and according to the desired structuring of the metallization is structured,</li><li>on the base layer a cover layer is deposited and</li></sl>the photoresist and certain parts of the base layer are removed.
0033Moreover, the invention relates to a thin-film circuit on a substrate of an insulating material equipped with at least one passive component, which at least<sl><li>a first patterned electrically conductive layer,</li><li>a dielectric,</li><li>comprises a second electrically conductive layer,</li><li>a protective layer,</li></sl>and at least one contact hole which penetrates the substrate, and a structured metallization which the protective layer and the contact hole covered.
0034In the following, the invention is based on five figures and three embodiments are explained.
It shows
0035<dl tsize="17" compact="compact"><dt>Fig. 1</dt><dd>in cross-section the schematic structure of an inventive Component equipped with a thin-film circuit, which a capacitor, a resistor and a Streifenleitungsinduktor has and</dd><dt>FIG. 2 to FIG. 5</dt><dd>a flow chart for manufacturing a component with thin-film circuit.</dd></dl>
0036Referring to FIG. 1, a component with a thin-film circuit substrate 1 which For example, a ceramic material, a glass-ceramic material, a glass material or a ceramic material with a planarizing layer of glass or contains organic material. Preferably, the substrate 1 Al<sub>2</sub>O<sub>3</sub>, Glass, Al<sub>2</sub>O<sub>3</sub> With a planarization layer of glass, polyimide or polybenzocyclobutene. In this Substrate 1 may be applied a barrier layer 8, which for example, Si<sub>3</sub>N<sub>4</sub> contains. On the substrate 1 or the barrier layer 8, a resistive layer 7 is deposited and structured. This structured resistance layer 7, for example, Ni<sub>x</sub>Cr<sub>y</sub>Al<sub>z</sub> (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si<sub>x</sub>Cr<sub>y</sub>O<sub>z</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si<sub>x</sub>Cr<sub>y</sub>N<sub>z</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) Cu,<sub>x</sub>Ni<sub>y</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1) or Ti<sub>x</sub>W<sub>y</sub>(0 ≤ x ≤1, 0 ≤ y ≤ 1). In this resistive layer 7 is a first electrically conductive layer 2 is deposited and patterned. On this structured first electrically conductive layer 2 is a dielectric 3, which is generally the whole covered surface of the substrate 1 and is interrupted only at certain points to Vias produce to the underlying first electrically conductive layer patterned second The dielectric 3, for example, Si<sub>3</sub>N<sub>4</sub>, SiO<sub>2</sub>, Si<sub>x</sub>O<sub>y</sub>N<sub>z</sub> (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) or Ta<sub>2</sub>O<sub>5</sub> contain. On the dielectric 3 is a second electrically conductive Layer 4 is deposited and patterned. The first electrically conductive layer 2 and the second electrically conductive layer 4 can, for example, Cu, Al, Al doped with a few Cu percent, Al doped with a few percent of Si, Al doped with a few percent of Mg or Al doped with a few percent of Cu and Si. Over the entire region of the Substrate 1 is a structured protective layer 5 of an inorganic material such as SiO<sub>2</sub>, Si<sub>3</sub>N<sub>4</sub> or Si<sub>x</sub>O<sub>y</sub>N<sub>z</sub> (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1). alternative may also be an organic material such as polyimide, polybenzocyclobutene or be used. In addition, the member has provided with a thin-film circuit at least one contact hole 6. The component and the contact hole 6 are of surrounded a structured metallization which in turn includes a base layer. 9 It may be preferred that the base layer 9 one or more additional metallic Layers are applied. In this case, the base layer 9, which for example serves Cr / Cu, as a seed layer for the galvanic deposition of a covering layer 11. The cover layer 11 contains, for example, Cu / Ni / Au.
0037Furthermore, power supply lines can be mounted on opposite sides of the component be. As power supply, an electroplated SMD end contact of Cr / Cu, Ni / Sn, or Cr / Cu, Cu / Ni / Sn, or Cr / Ni, Pb / Sn, a bump end contact, a castellation of Cr / Cu, Cu / Ni / Au, a ball grid array of a Cr / Cu / Ni-layer having a mounted ball of Sn or a PbSn alloy or a land grid array of Cr / Cu be used.
0038Such a device equipped with a thin-film circuit, for example, in the manufacture of a power amplifier for the high frequency unit of a mobile Phone use.
0039For producing a component with thin-film circuit, in accordance with process step I in Fig. 2, first, on a substrate 1, for example a ceramic material a glass-ceramic material, a glass material or a ceramic material with a Planarizing layer of glass or an organic material, such as Polyimide or polybenzocyclobutene contains a barrier layer 8, which for example, Si<sub>3</sub>N<sub>4</sub> contains are deposited. On the barrier layer 8 or alternatively the Substrate 1, a resistive layer 7 is deposited and structured (process step II in Fig. 2). The resistive layer 7, for example, Ni<sub>x</sub>Cr<sub>y</sub>Al<sub>z</sub>(0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si<sub>x</sub>Cr<sub>y</sub>O<sub>z</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), Si<sub>x</sub>Cr<sub>y</sub>N<sub>z</sub>(0 ≤ x ≤1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) Cu,<sub>x</sub>Ni<sub>y</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1) or Ti<sub>x</sub>W<sub>y</sub> (0 ≤ x ≤1, 0 ≤ y ≤ 1). On the barrier layer 8 or, alternatively, to the substrate 1 and on Parts of the resistive layer 7, a first electrically conductive layer 2 is deposited and patterned (process step III in Fig. 2). Over the entire surface of the substrate 1 is a dielectric 3 is deposited (step IV in Fig. 2). The dielectric 3 preferably contains Si<sub>3</sub>N<sub>4</sub>, SiO<sub>2</sub>, Si<sub>x</sub>O<sub>y</sub>N<sub>z</sub> (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) or Ta<sub>2</sub>O<sub>5</sub>, According to process step I in Fig. 3 subsequently to the dielectric 3, a second electrically conductive layer 4 is deposited and patterned. The first electrically conductive Layer 2 and the second electrically conductive layer 4 can, for example, Cu, Al, Al doped with a few percent of Cu, Al doped with a few percent of Si, Al doped with a few Percent Mg or Al doped with a few percent of Cu and Si. According to method step II in Fig. 3 over the entire thin-film circuit a protective layer 5 applied from an inorganic material. As the inorganic material can be used to example Si<sub>3</sub>N<sub>4</sub>, SiO<sub>2</sub> or Si<sub>x</sub>O<sub>y</sub>N<sub>z</sub> (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1) can be used. Alternatively, an organic material such as polybenzocyclobutene or Polyimide can be used as the material for the protective layer. Following are the Protective layer 5 and the dielectric 3 patterned (process step III in Fig. 3). This can be effected by means of photolithographic processes or photosensitive materials Otherwise, by means of wet-chemical or dry etching. In addition, at least Created a contact hole 6 penetrating through the substrate 1 by means of a laser (Process step IV in Fig. 3).
0040According to method step II in Fig. 4 is for realizing the structured metallization first a base layer 9 is applied, which the component and the contact hole 6 covered. This base layer 9 includes, for example, Cr / Cu. The next step is to the base layer 9 is a layer of photoresist 10 is deposited and by photolithographic Processes structured so that the layer of photoresist 10, the pattern of the desired Structuring the metallization comprises (process step III in Fig. 4). Then galvanically a topcoat 11 which, for example Cu / Ni / Au comprises, deposited on the base layer. 9 (Step II in Fig. 5). By distance the photoresist 10 are the areas not covered with the covering layer 11 parts of Base layer 9 is removed by an etching bath.
0041Furthermore, power supply lines can be mounted on opposite sides of the component be. As power supply, an electroplated SMD end contact of Cr / Cu, Ni / Sn, or Cr / Cu, Cu / Ni / Sn, or Cr / Ni, Pb / Sn, a bump end contact, a castellation of Cr / Cu, Cu / Ni / Au, a ball grid array of a Cr / Cu / Ni-layer having a patch Ball of Sn or PbSn alloy or a land grid array of Cr / Cu used will.
0042Alternatively, to create a contact hole 6 before using thin film techniques applied the strip lines and passive integrated components will.
0043Embodiments of the invention are explained, the exemplary implementation options represent.
Embodiment 1
0044On a substrate 1 made of Al<sub>2</sub>O<sub>3</sub> with a planarizing layer of glass is a structured Barrier layer 8 of Si<sub>3</sub>N<sub>4</sub> applied. On the barrier layer 8 has a resistive layer 7 of Ni<sub>03</sub>Cr<sub>06</sub>Al<sub>01</sub> deposited and patterned. On a part of the resistance layer 7 and on parts of the barrier layer 8, a first electrically conducting Layer 2 of Al doped with 4% Cu deposited and patterned. In the next step was over the entire surface of the substrate 1 a dielectric 3 of Si<sub>3</sub>N<sub>4</sub> deposited. On the dielectric 3 a second electrically conducting layer 4 of Al doped with 4% Cu deposited and patterned. The entire thin-film circuit was with a protective layer 5 made of Si<sub>3</sub>N<sub>4</sub> provided. The dielectric 3 and the protective layer 5 were patterned to a later electrical contacting of the first electrically conductive Layer 2 and / or to enable the resistive layer 7th Further, several contact holes 6 that penetrate the substrate 1, by means of a set s laser. To the component and in the contact holes 6, a metallization of a Base layer 9 is applied of Cr / Cu and a top layer 11 made of Cu / Ni / Au. also were on both sides of the component, ball grid arrays with a layer of Cr / Cu / Ni and Balls attached from Sn as power supply lines.
0045was by further equipping with appropriate active and passive components the component fitted with a thin-film circuit for producing a power amplifier further used for the high frequency unit of a mobile phone.
Embodiment 2
0046On a substrate 1 made of Al<sub>2</sub>O<sub>3</sub> was a barrier layer 8 of Si<sub>3</sub>N<sub>4</sub> deposited and patterned. On the barrier layer 8 A first electrically conducting layer 2 of Al doped with 4% Cu deposited and patterned. The next step was the entire Surface of the substrate 1, a dielectric 3 of Ta<sub>2</sub>O<sub>5</sub> deposited and patterned. On the dielectric 3 a second electrically conducting layer 4 of Al doped with 4% Cu deposited and patterned. The entire thin-film circuit was a protective layer 5 made of Si<sub>3</sub>N<sub>4</sub> provided. Furthermore, a plurality of contact holes 6 were, which created the substrate 1 completely penetrate by means of a laser. to the entire component and in the contact holes 6 was a metallization of a base layer 9 is applied of Cr / Cu and a top layer 11 made of Cu / Ni / Au. also were on both sides of the component castellations of Cr / Cu, Cu / Ni / Au as the current supply leads attached. The resulting component with thin-film circuit is for producing a band-pass filter further used in mobile phones.
Embodiment 3
0047For producing a component with thin-film circuit on a substrate 1 was prepared from Al<sub>2</sub>O<sub>3</sub> with a planarizing layer of glass, a barrier layer 8 of Si<sub>3</sub>N<sub>4</sub> secluded and structured. On this barrier layer 8, a resistive layer 7, from Ti<sub>0.1</sub>W<sub>09</sub> deposited and patterned. Subsequently, a first electrically conductive Layer 2 is deposited and patterned. In this first structured electrically conductive Layer 2, a dielectric 3 of Si<sub>3</sub>N<sub>4</sub> deposited. Then, on this dielectric 3 a second electrically conductive layer 4 is deposited and patterned. The first electrically conductive layer 2 and the second electrically conductive layer 4 contained Al doped with Si four percent. To the component a protective layer 5 was prepared from Si<sub>3</sub>N<sub>4</sub> applied. To make electrical contact were by the protective layer 5 and the dielectric 3 Vias etched. Subsequently, several vias were 6 means created a laser that penetrate the substrate 1 completely. In the next step was around the component and in the contact holes 6, a base layer 9, which Cr / Cu contained, deposited. Thereafter, on the base layer 9 is a layer of photoresist 10 applied. This layer of photoresist 10 was determined by photolithographic processes so structured such that the layer of photoresist 10, the pattern of the desired structuring the metallization had. In the next step a cover layer 11 made of Cu / Ni / Au was electrodeposited onto the base layer 9 made of Cr / Cu is deposited, followed by the removed photoresist 10th Moreover were on both sides of the component, ball grid arrays with a layer of Cr / Cu / Ni and balls mounted from Sn as power supply lines.
6 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US7875956B2 | Cited by | United States of America | Applicant |
| US10490322B2 | Cited by | United States of America | Applicant |
| EP1697991A1 | Cited by | European Patent Office (EPO) | Search report |
| US6898604B1 | Cited by | United States of America | Applicant |
| US7266605B2 | Cited by | United States of America | Applicant |
| US6961750B1 | Cited by | United States of America | Applicant |
| WO2017121727A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| US8569142B2 | Cited by | United States of America | Applicant |
| US7640495B2 | Cited by | United States of America | Applicant |
| EP1697991A4 | Cited by | European Patent Office (EPO) | Search report |
| EP0670668B1 | Cites | European Patent Office (EPO) | Search report |
| GB2186436A | Cites | United Kingdom | Search report |
| US4735676A | Cites | United States of America | Search report |
| US4854040A | Cites | United States of America | Search report |
| US5270493A | Cites | United States of America | Search report |
| JPH0258893A | Cites | Japan | Search report |
8 members in 5 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 19961683 | Germany | – | |
| 19961683 | Germany | A |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| EP1111679A2This record | European Patent Office (EPO) | A2 | |
| DE19961683A1 | Germany | A1 | |
| CN1306307A | China | A | |
| JP2001223329A | Japan | A | |
| US2001017770A1 | United States of America | A1 | |
| US6545225B2 | United States of America | B2 | |
| CN1203554C | China | C | |
| EP1111679A3 | European Patent Office (EPO) | A3 |
18 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Application deemed to be withdrawnWithdrawn18D | 18D | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWNSTAA | STAA | |
| First examination report despatched17Q | 17Q | |
| Designation fees paidAKX | AKX | |
| Request for examination filed17P | 17P | |
| Designated contracting statesAK | AK | |
| Request for extension of the european patentAX | AX | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | |
| Search report despatchedORIGINAL CODE: 0009013PUAL | PUAL | |
| Party data changed (applicant data changed or rights of an application transferred)RAP1 | RAP1 | |
| Party data changed (applicant data changed or rights of an application transferred)RAP1 | RAP1 | |
| Party data changed (applicant data changed or rights of an application transferred)RAP1 | RAP1 | |
| Party data changed (applicant data changed or rights of an application transferred)RAP1 | RAP1 | |
| Designated contracting statesAK | AK | |
| Request for extension of the european patentAL;LT;LV;MK;RO;SIAX | AX | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI |
Numbers
- Publication
- 1111679
- Application
- 2046159
Titles3
- German
- Bauteil mit Dünnschichtschaltkreis
- English
- Device with thin-film circuit
- French
- Dispositif ayant un circuit à couche mince
Classification
- CPC, 9
- H05K1/162
- H05K1/0306
- H05K1/16
- H05K1/167
- H05K3/388
- H05K3/428
- H05K3/467
- H05K2201/0179
- H10D86/85
- IPC, 10
- H01L27 01
- H05K1 09
- H01L21 70
- H05K1 03
- H05K1 11
- H05K1 16
- H05K3 38
- H05K3 40
- H05K3 42
- H05K3 46
Designated states26
- Contracting states, 20
- Austria
- Belgium
- Switzerland
- Cyprus
- Germany
- Denmark
- Spain
- Finland
- France
- United Kingdom
- Greece
- Ireland
- Italy
- Liechtenstein
- Luxembourg
- Monaco
- Netherlands (Kingdom of the)
- Portugal
- Sweden
- Türkiye
- Extension states, 6
- Albania
- Lithuania
- Latvia
- North Macedonia
- Romania
- Slovenia