Scratch resistance improvement by filling metal gaps

0001The present invention relates generally to scratch protection for integrated sensor circuits, and more specifically to improvement of scratch protection in capacitive sensor circuits through planarization of passivation overlying capacitive sensor electrodes.

0002Fingerprint acquisition circuits employ arrays of sensors coated with a dielectric onto which the finger is placed with the epidermis in contact with the dielectric. The ridges and grooves on the epidermal layer of the finger are then detected by the sensors, which transmit signals representative of the detected pattern. Although various sensors are possible (e.g., resistive, etc.), capacitive sensors have been found to provide the best performance and security. Since capacitance between two capacitive plates is inversely proportional to the distance between the plates, using the contacting dermal tissue itself as one capacitor plate and the sensor electrode as the other and then determining capacitance for each sensor electrode in the array, it is possible to locate the ridges and grooves of the fingerprint.

0003Such capacitive sensors cannot be mechanically protected because physical contact on the surface of the integrated circuit with the finger is necessary. However, some scratch resistance protection for the capacitive sensor electrodes is required to prevent "scratch" damage to the sensor electrodes. Such damage typically results from undue (and unnecessary) pressure on the surface of the integrated circuit, alone or in combination with some sharp edge or protrusion such as a callous or scar, fingernail, rings, dust or dirt particle, etc. While extremely hard passivation stacks employing silicon carbide (SiC) have been developed for these circuits, the capacitive electrodes may still become very badly damaged through use.

0004It would be desirable, therefore, to improve the scratch resistance of passivation employed in capacitive sensor circuits.

0005Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.

0006The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: <ul id="ul0001" list-style="none"><li><b>Figures 1A-1B</b> depict various views of a sensor circuit employing scratch resistance in accordance with a preferred embodiment of the present invention;</li><li><b>Figures 2A-2C</b> are cross-sectional details of a sensor circuit in accordance with the known art and in accordance with a preferred embodiment of the present invention;</li><li><b>Figures 3A-3F</b> depict results of micro scratch testing for sensor circuits in accordance with the known art and in accordance with a preferred embodiment of the present invention; and</li><li><b>Figures 4A-4F</b> are a series of cross-sections for a process of fabricating a sensor circuit in accordance with a preferred embodiment of the present invention.</li></ul>

0007The following description details the structure, application and features of the present invention, but it will be understood by those of skill in the art that the scope of the invention is defined only by the issued claims, and not by any description herein. The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.

0008With reference now to the figures, and in particular with reference to <b>Figures 1A</b> and <b>1B</b>, various views of a sensor circuit employing scratch resistance in accordance with a preferred embodiment of the present invention are depicted. <b>Figure 1A</b> depicts a block diagram of the sensor circuit <b>102</b>, which is formed as an integrated circuit on a single die. The sensor circuit <b>102</b> and its operation are described more fully in commonly assigned, copending application serial no. 09/040,261, entitled "CAPACITIVE DISTANCE SENSOR" and filed May 9, 1998, which is incorporated herein by reference.

0009The portions of sensor circuit <b>102</b> relevant to the present invention include an array <b>104</b> of capacitive sensors for fingerprint acquisition by sensing distances between capacitive electrodes within the sensor array <b>104</b> and ridges and grooves on a finger placed in contact with sensor array <b>104</b>. Sensor circuit <b>102</b> also includes signal lines <b>106</b> and <b>108</b> and output bus <b>110</b>. Signal line <b>106</b> connects I²C interface and control device <b>104</b>, which provides a bidirectional communication protocol enabling sensor circuit <b>102</b> to communicate with a controller such as a microcontroller, with controller circuitry (not shown) external to sensor circuit <b>102</b>. Signal line <b>108</b> is a synchronization line coupling sensor array <b>104</b> to the external controller circuit, providing synchronization signals allowing detected voltages representative of the capacitive value of individual capacitive electrodes within sensor array <b>104</b>, and therefore representative of the distance between the capacitive electrode and the portion of the epidermal layer contacting sensor array <b>104</b> in the region of the capacitive electrode, to be properly interpreted by the external controller. Output bus <b>110</b> coupling an analog-to-digital (A/D) converter <b>114</b> to the external controller. A/D converter <b>114</b> processes analog voltage measurements received from sensor array <b>104</b> and generates digital representations recognized by the external controller as distance measurements of the analog measured voltages from individual capacitive electrodes within sensor array <b>104</b>. A/D converter <b>114</b> transmits these digital signals to the external controller on output bus <b>110</b>.

0010<b>Figure 1B</b> is a pictorial representation of the "front" side of sensor circuit <b>102</b>; that is, <b>Figure 1B</b> depicts the major surface of the die <b>116</b> on which the active devices constituting sensor circuit <b>102</b> are formed. Sensor array <b>104</b> is located on the front side of die <b>116</b> and includes a plurality of cells <b>118</b>, each containing one or more capacitive electrodes. Sensor array <b>104</b> in the exemplary embodiment contains square cells approximately 45-50 µm on a side, forming a 250 X 350 array of contiguous cells <b>118</b> within sensor array <b>104</b>. Sensor array <b>104</b> is covered by a passivation material overlying the capacitive electrodes within each cell <b>118</b>. Other active devices required to form sensor circuit <b>102</b> are formed below the capacitive electrodes.

0011Referring to <b>Figures 2A</b> throug<b>h 2C</b>, cross-sectional details of a sensor circuit in accordance with the known art and in accordance with a preferred embodiment of the present invention are illustrated. The details illustrated are from cross-sections taken at section line <b>A-A</b> in <b>Figure 1B</b>. <b>Figure 2A</b> illustrates sensor circuit passivation in accordance with the known art. Sensor circuit <b>102</b> includes metal electrodes <b>202</b> for the capacitive sensors overlying an interlevel dielectric <b>204</b>, such as an oxide. Passivation formed over capacitive metal electrodes <b>202</b> includes phosphosilicate glass (PSG) layer <b>206</b>, silicon nitride (SiN) layer <b>208</b>, and silicon carbide (SiC) layer <b>210</b>, which together form the passivation for sensor circuit <b>102</b>. As illustrated, the passivation layers <b>206</b>, <b>208</b> and <b>210</b> are conventionally formed conformally over electrodes <b>202</b> and dielectric <b>204</b>. This structure has been found to provide less than completely satisfactory scratch resistance, even when tungsten electrostatic discharge (ESD) protection patterns and/or capacitive electrodes are employed.

0012<b>Figure 2B</b> illustrates sensor circuit passivation in accordance with the present invention. Scratch resistance is improved by filling the spaces between the metal electrodes <b>202</b> to prevent these electrodes from crashing under pressure. However, the sensitivity of the capacitive cells within sensor circuit <b>102</b> should not be degraded, which means that the capacitance should not be significantly reduced by additional dielectric thickness between the capacitive electrodes <b>202</b> and the finger or by introduction of materials with a high dielectric constant. In the present invention, therefore, a hydrogen silsesquioxane (HSQ) layer <b>212</b> is formed over the interlevel dielectric <b>204</b> and capacitive metal electrodes <b>202</b> before forming the passivation.

0013HSQ (also referred to as "flowable oxide") layer <b>212</b> may be formed according to known processes and exhibits a very high planarization, greater than 90% planar at spacings of 5 µm or less. HSQ also has excellent gap filling capabilities, down to 0.1 µm spaces, and a low dielectric constant (less than 3). Thus HSQ layer <b>212</b> should not significantly degrade the sensitivity of sensor circuit <b>102</b>. HSQ layer <b>212</b> is formed very thin over capacitive electrodes <b>202</b>, with less than the thickness of capacitive electrodes <b>202</b> (approximately 1 µm thick) overlying the capacitive electrodes <b>202</b>. The thickness of HSQ layer <b>212</b> in regions adjacent to capacitive electrodes <b>202</b> is thus preferably only slightly thicker than the capacitive electrodes <b>202</b> themselves.

0014HSQ layer <b>212</b> provides a substantially planar upper surface, on which is formed the passivation: PSG layer <b>206</b> to a thickness of approximately 5,000 Å; SiN layer <b>208</b> to a thickness of approximately 5,000 Å; and SiC layer <b>210</b> to a thickness of approximately 2,500 Å. PSG layer <b>206</b> may be formed before HSQ layer <b>212</b>, but is preferably formed over HSQ layer <b>212</b> since the interface between HSQ and nitride is weaker. Alternatively, oxide may be deposited in lieu of (or in addition to) HSQ layer <b>212</b>, and planarized utilizing a planarizing etch-back, such as chemical mechanical polishing (CMP). <b>Figure 2C</b> illustrates sensor circuit passivation in accordance with an alternative embodiment of the present invention, in which SiC layer <b>210</b> is omitted.

0015With reference now to <b>Figures 3A</b> through <b>3F</b>, results of micro scratch testing for sensor circuits passivated in accordance with the known art and in accordance with a preferred embodiment of the present invention are depicted. In <b>Figure 3A</b>, test structures passivated with conformal PSG, SiN and SiC layers in accordance with the known art were subject to a 2 N force by a 1 mm steel stylus are seen to be damaged. Sensor circuits passivated in this manner are known to scratch easily, and may be rendered inoperative by a 1 N force applied by a 0.5 mm diamond pin.

0016<b>Figures 3B</b> and <b>3C</b> illustrate the effect of the same 2 N force applied by a 1 mm steel stylus on test structures passivated with a planarizing layer of flowable oxide in accordance with the present invention. <b>Figure 3B</b> illustrates the result when a SiC layer is employed, while <b>Figure 3C</b> illustrates the result without an SiC layer. As shown, no damage is detectable.

0017<b>Figures 3D</b> through <b>3F</b> illustrate similar testing as that for <b>Figures 3A</b> through <b>3C</b>, but with a 5 N force applied by the 1 mm steel stylus. Again, the test structures passivated in the conventional manner were destroyed, as shown in <b>Figure 3D</b>. Test structures passivated with a planarizing FOX layer exhibited no appreciable damage when a silicon carbide layer was employed, as shown in <b>Figure 3E</b>, and only very minimal damage without the silicon carbide layer, as shown in <b>Figure 3F</b>.

0018Referring to <b>Figures 4A</b> through <b>4F</b>, a series of cross-sections for a process of fabricating a sensor circuit in accordance with a preferred embodiment of the present invention are illustrated. The process begins with the sensor circuit fabricated to the point of having formed capacitive electrodes <b>402</b> connected to underlying conductive polysilicon structures <b>404</b>, which may be gate electrodes, source/drain contacts, or interconnects, through an interlevel dielectric <b>406</b> and a lower dielectric layer <b>408</b>. Cross-sections from the sensor array area <b>410</b>, the peripheral area <b>412</b>, and the pad area <b>414</b> of the sensor circuit are depicted. Contacts <b>416</b> for ESD protection lines and die contact pads <b>418</b> are formed within the peripheral area <b>412</b> and the pad area <b>414</b>, respectively.

0019A flowable oxide layer <b>420</b> and a PSG layer <b>422</b> are then formed over all areas <b>410</b>, <b>412</b>, and <b>414</b>, as shown in <b>Figure 4B</b>. In the example shown, PSG layer <b>422</b> is formed beneath flowable oxide <b>420</b>, although the opposite order is preferred for the reasons described above. Vias <b>424</b> for the connections to ESD protection lines are then etched as illustrated in <b>Figure 4C</b>, and silicon nitride layer <b>426</b> and silicon carbide layer <b>428</b> are deposited and patterned for the ESD protection grid as shown in <b>Figure 4D</b>. A tungsten layer is then formed and etched back to form ESD protection lines and connections <b>430</b> as illustrated in <b>Figure 4E</b>, and an opening to pad <b>418</b> is etched as shown in <b>Figure 4F</b>.

0020The present invention improves scratch resistance for a capacitive sensor circuit simply by planarizing the passivation, without significantly diminishing the sensitivity of the sensor circuit. The spaces between capacitive electrodes at the surface of the sensor circuit, immediately below the passivation, are filled with flowable oxide, with only a very thin layer of flowable oxide formed over the capacitive electrodes themselves, resulting in a planar surface for formation of the passivation layers. The planarized passivation provides uniform boundaries for force applied to the surface of the sensor circuit, substantially improving scratch resistance for the circuit.

0021While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.