Pseudo-random data generator and scrambler using the same

A random data generator and a scrambler using the same are provided. The random data generator includes a m×n decoder (100) for receiving m bits and outputting n bits, registers (r0-rn-1) arranged in series for shifting and storing the n bits, and selection output circuits (m0-mn-1) for receiving n bits of output from the m×n decoder (100) as selection signals, and providing "0" with respect to valid bits among the n bits of output from the m×n decoder (100) and providing the outputs of the registers (r0-rn-1) with respect to invalid bits. The random data generator also includes logic circuits (G0-Gn-1) for performing XOR operations with respect to the n bits of output from the selection output circuits (m0-mn-1) and the n bits of output from the registers (r0-rn-1), and feeding the results of the XOR operations back to a least significant register (r0) only in the case of valid bits among the n bits of output from the m×n decoder (100). Accordingly, random data having a cycle of 64K or greater can be generated, and a random data generator for 2m×64K can be realized with the m×n decoder.