Circuit and method for automatic detection and correction of short circuits between wordlines and bitlines

The present invention relates to a circuit arrangement and a method for the automatic detection and elimination of word line bit line short circuits in a memory cell arrangement comprising sensor amplifiers and having bit lines and redundant bit lines, the sensor amplifiers dividing the memory cell arrangement into memory blocks.

Word line bit line short circuits are known to prevent reading into and reading out from a memory cell arrangement of a memory. The detection and elimination of such word line bit line short circuits is therefore of great importance in order to be able to guarantee the operation of the memory.

Such word line-bit line short-circuits occur when word lines and bit lines touch each other as a result of errors or irregularities in the production process of the memory or are connected in a low-resistance manner, for example, by conductive dirt particles.

In the case of memories which use split sensor amplifiers in the bit lines, so that two branches of a bit line or two different bit lines are assigned to each sensor amplifier and the memory cells of the memory cell arrangement are subdivided overall into two adjacent memory blocks, that even after the replacement of a bit line short-circuited with a word line in one memory block, the correct operation of this bit line in the other memory block is disturbed: the correct precharging of the bit line of the other memory block is namely prevented by the short circuit between the corresponding bit line and a word line in the one memory block, so that a correct reading of the corresponding memory cells of the short-circuited bit line in the one memory block is no longer possible in the other memory block.

In order to overcome this difficulty, not only has the defective branch of the bit line in one memory block been replaced, but also the branch of the bit line, which is not defective per se, or a different bit line in the other memory block, has been replaced by a redundant bit line in both memory blocks. This has the disadvantage that practically twice as many bit lines have to be kept available for redundancy as if only the actually defective bit lines or their branches have to be replaced in the respective memory blocks. In other words, the redundancy of the existing memory cell arrangements - as far as the occurrence of word line-bit line short-circuits - is reduced by a factor of 2 when using shared sensor amplifiers if the bit lines actually disturbed by short circuits are considered in the two memory blocks.

It is therefore an object of the present invention to provide a circuit arrangement and a method for the automatic detection and elimination of word line bit line short circuits, with which an increase in redundancy when such errors occur is possible in order to achieve an improved yield.

This object is achieved according to the invention in a circuit arrangement or a method according to the preamble of patent claim 1 or 4 by the features specified in the respective characterizing parts of these patent claims.

In the invention, a fuse is therefore provided in the bit lines before the sensor amplifiers in each memory block, which fuse is activated in a test mode, so that the short-circuited bit line in question is separated from the sensor amplifier in the corresponding memory block. The branch of the corresponding bit line in the other memory block can thus operate correctly, so that a replacement by a redundant bit line is not necessary here. This means that the flexibility of the redundancy of the bit lines is fully retained, since the short-circuited bit lines are separated from the sensor amplifiers by the test mode by activating their fuses. Only these separated bit lines therefore need to be replaced by redundant bit lines in the respective memory blocks.

The present invention thus enables a considerable simplification of the redundancy, which is of the order of a factor 2: only half as many redundant bit lines have to be kept available in order to replace bit lines which are disturbed by word line-bit line short-circuits. Alternatively, it is also possible to use the "saved" redundant bit lines for eliminating other errors, which improves the yield.

The respective fuses in the bit lines can be activated in the test mode in various ways: it is possible to provide a transistor for activating the fuses between the respective fuses and sensor amplifiers. In the test mode, the word lines are then activated one after the other and the bit lines are separated from one another by switching off the precharge and muxing transistors provided in the sensor amplifiers. That is, the bit lines are separated by the sensor amplifiers so that one branch of the same bit line in one memory block is separated from the other branch of the same bit line in the other memory block. If there is a short circuit between the activated word line and a bit line branch, this bit line branch receives almost the same, high potential of the word line. If this bit line branch is then pulled to a correspondingly low potential via a transistor located between the fuse of this bit line branch and the sensor amplifier, the fuse of this bit line branch is activated and this bit line branch is separated from the sensor amplifier.

Thus the short-circuited bit line branch no longer interferes with the operation of the other branch of the same bit line or even a different bit line, so that this other branch does not have to be replaced by a redundant bit line. It is therefore sufficient if only one defective branch of the bit line in the one memory block is replaced by a redundant bit line.

It is not absolutely necessary to provide the transistor located between the fuse and the sensor amplifier. If necessary, it is also possible to use the normal write-in path: a low (zero) voltage is applied to the sensor amplifier in the write cycle and / or a high voltage is applied to the word line at the same time. As a result of the voltage difference that occurs in the short-circuited word line, the corresponding fuse is severed in test mode.

2 shows an existing memory cell arrangement with word lines WL1, WL2, WL3, ..., bit lines BL1, BL2 and <maths id="math0001" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0001.tif" /></maths>1, <maths id="math0002" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0002.tif" /></maths>2nd and redundant bit lines RBL, <maths id="math0003" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext mathvariant="italic">RBL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0003.tif" /></maths>. For bit lines BL1, BL2 or<maths id="math0004" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0004.tif" /></maths>1, <maths id="math0005" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0005.tif" /></maths>2nd can be two branches of the same bit line or two different bit lines. At intersections of bit lines BL1, BL2 and<maths id="math0006" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0006.tif" /></maths>1, <maths id="math0007" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0007.tif" /></maths>2nd with the word lines WL1, WL2, WL3, ... there are memory cells composed of transistors T and capacitors C. For architecture and space reasons, only every second overlap of word lines and bit lines is occupied by such memory cells. The electrodes of the capacitors C facing away from the transistors T are each subjected to a constant voltage of, for example, 0.9 V.

The bit lines BL1, BL2 or <maths id="math0008" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0008.tif" /></maths>1, <maths id="math0009" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0009.tif" /></maths>2nd are, as shown in Fig. 2, divided into two branches ("1" and "2") by a sensor or sense amplifier SA. These sensor amplifiers SA contain precharge and muxing transistors (not shown). The muxing transistors each switch the "left" or "right" branch of a bit line BL1, BL2 or<maths id="math0010" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0010.tif" /></maths>1, <maths id="math0011" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0011.tif" /></maths>2nd a.

The bit line <maths id="math0012" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0012.tif" /></maths>1, <maths id="math0013" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0013.tif" /></maths>2nd serves as a reference line with a reference voltage of 0.9 V for the sensor amplifier SA when the bit line BL1, BL2 is read. Conversely, the bit line BL1, BL2 serves as a reference line for the sensor amplifier SA with a reference voltage of 0.9 V if the bit line<maths id="math0014" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0014.tif" /></maths>1, <maths id="math0015" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0015.tif" /></maths>2nd is read.

The redundant bit lines RBL, <maths id="math0016" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext mathvariant="italic">RBL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0016.tif" /></maths> are constructed in the same way as explained above for the bit lines.

If a short circuit occurs between, for example, the bit line BL1, BL2 and the word line WL1 in this circuit arrangement, not only the bit line branch (BL1) of the bit line BL1, BL2 is "left" from the sensor amplifier SA, but also the branch (BL2) to the right this sensor amplifier SA, as explained above, so that the disturbed bit line through the redundant bit line RBL (or <maths id="math0017" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext mathvariant="italic">RBL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0017.tif" /></maths>) must be replaced.

The invention remedies this in a simple manner in that fuses are provided in the respective bit lines, as explained above.

The invention is explained in more detail below with reference to the drawings. Show it:<dl id="dl0001"><dt>Fig. 1</dt><dd>a circuit diagram with a bit line and a word line for explaining the invention, and</dd><dt>Fig. 2</dt><dd>an existing circuit arrangement.</dd></dl>

2 has already been explained at the beginning.

In FIG. 1, corresponding parts are provided with the same reference numerals as in FIG. 2.

1 shows a word line WL in which there is a short circuit with a bit line BL1, BL2 at an intersection point 1. The word line WL thus corresponds, for example, to the word line WL1 from FIG. 2, while the bit line BL1, BL2 is to be assigned to the bit line BL1, BL2 from FIG. 2. If such a short circuit occurs, then not only the branch (BL1) of the bit line BL1, BL2 on the "left" side of a sensor amplifier SA is disturbed, but also the branch (BL2) of the bit line BL1, BL2 on the "right" side thereof . This means that the bit lines of both memory blocks are disturbed. It should be noted again that the lines BL1, BL2 can be two branches of the same bit line or two different bit lines.

In order to avoid that the branch of the bit line BL2 on the "right" side of the sensor amplifier SA has to be replaced by a redundant bit line, a fuse FE is provided between the overlap 1 and the sensor amplifier SA which, when a certain limit voltage is exceeded " burns out "and the electrical connection is interrupted. Such fuses are in all bit lines BL1, BL2 (and<maths id="math0018" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0018.tif" /></maths>1, <maths id="math0019" num=""><math display="inline"><mrow><mover accent="true"><mrow><mtext>BL</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0965995A2_D0019.tif" /></maths>2) provided, which lead to the sensor amplifier SA.

In a test mode, the word lines WL are activated in succession and the bit lines BL1, BL2 are separated from one another by switching off the precharge and muxing transistors in the sensor amplifiers SA. 1 and 2, the "left" and "right" branches of the bit lines BL1, BL2 are each separated from one another after the precharge and muxing transistors have been switched off. If there is a short circuit between an activated word line WL and a bit line BL1, this bit line BL1 receives almost the high potential of the word line WL as a result of the short circuit. If in this state the bit line BL1 is pulled to a correspondingly low potential via a transistor T1 branched off between the fuse FE and the sensor amplifier SA, the fuse FE is activated so that the corresponding branch of the bit line BL1 is separated from the sensor amplifier SA. To enable this disconnection, the transistor T1 is switched on at its gate via a corresponding signal TMWLBL, so that the low potential reaches the node between the fuse FE and the sensor amplifier SA via the source-drain path of the transistor T1.

If necessary, the transistor T1 can also be dispensed with. In this case, a low "special voltage" is applied to the sensor amplifier SA in the write cycle, while a correspondingly high voltage is supplied to the word line WL. If the voltage difference between this special voltage and the high voltage is sufficiently large, the fuse FE is disconnected in the event of a short circuit between the word line WL and the bit line BL1.

The invention thus enables a circuit arrangement or a method with which the word lines are successively activated in a test mode and the bit lines are separated from one another by switching off the precharge and muxing transistors. If there is a short circuit between an activated word line and a bit line, this receives almost the high potential of the word line in the test mode. In this case, a fuse provided in the bit line is activated, so separate the short-circuited bit line or its branch from the sensor amplifier.

The number of redundant bit lines to be provided can thereby be considerably reduced. Alternatively, it is also possible to use the "saved" redundant bit lines for eliminating other errors, which increases the overall yield.