A frame format and method and apparatus for processing a frame

0001The present invention relates to a frame format and to a method and apparatus for processing a frame. A particular arrangement to be described by way of example in illustration of the invention is concerned with a frame format used in a Forward Error Correction section for an error correction code that is used in a main transmission apparatus.

0002In recent years, an increase in the amount of communication is remarkable against the background of the development of information transfer. Accordingly, the development of a high speed and large capacity transmission apparatus is urgently needed in a main transmission system. Also, at the same time as this, the small-sizing of apparatus and the reduction of cost are essential. The codec section for an error correction code used in main transmission apparatus is also no exception to this.

0003Accordingly, since, in an FEC (Forward Error Correction)IC that has been used conventionally, the processing speed is slow, parallel processing is conducted by means of a number of IC's for achieving high speed processing. This means that the scale of the apparatus becomes large. Accordingly, a high speed and small-sized IC is required. Actually, high speed IC, parallel processing is often conducted so as to meet the speed of an encoding section inside the IC.

0004EP-A-0 777 354 discloses a digital transmission apparatus employing differential coding and forward error correction and in which a forward error correction frame is divided for parallel processing.

0005A frame format has been proposed previously for use in a high speed FEC-IC, and the operation of the high speed FEC-IC will be explained, with reference to Figs. 13 to 18 of the accompanying drawings in which:- <ul id="ul0001" list-style="none" compact="compact"><li>Fig. 13 is a diagram for use in explaining a previously proposed frame format,</li><li>Fig. 14 is a block schematic diagram for use in explaining one example of a previously proposed high speed FEC-IC,</li><li>Fig. 15 is a diagram showing a bit series of one frame which is input in a previous proposal to a high speed FEC-IC,</li><li>Fig. 16 is a diagram showing the positions of bits which are processed by each COD of the high speed FEC-IC in a previous proposal,</li><li>Fig. 17 is a block schematic diagram showing a circuit arrangement of an FEC frame transformation section for use in conducting an FEC frame processing method in a previous proposal, and</li><li>Fig. 18 is an explanatory view of a data array after frame transformation in the FEC frame processing method in relation to a prior proposal.</li></ul>

0006As shown in Fig. 13, one frame is constructed of a total of 255 bits in which the first bit is an overhead (OH), 238 bits are data, and the remaining 16 bits are Reed Solomon codes (referred to as RS, hereinafter).

0007Now, the high speed FEC-IC for processing the data in the above-mentioned frame format will be explained.

0008Fig. 14 is a view for explaining one example of the high speed FEC-IC.

0009This FEC-IC is assumed to operate with 300 MHZ so as to conduct 8 bit parallel processing (input/output #1 to #8). Also, each input of the 8 bit parallels is further divided to 4 bit parallels by means of a serial-parallel (S/P) convertor, and the speed thereof is reduced to a speed at which code processing for a correction code can be conducted. Thereafter, the Reed Solomon codes (RS) are calculated and added by each COD module, and the speed is restored to the original transmission speed by a parallel-serial (P/S) transformation.

0010Next, operation of the high speed FEC-IC in which a frame of the previously proposed frame format is input will be explained.

0011A bit series of one frame that is input to #1 of Fig. 14 is shown in Fig. 15. Each numeral in Fig. 15 shows a bit position within the frame, and it will be considered that this frame is repeatedly input.

0012First, a serial data of 255 bits, which has been input from #1, is transformed to a 4 bit parallel data by the S/P transformation. Encoding of RS on the data is conducted by COD1 to COD4, respectively, and thereafter, the speed is restored to the original speed by the P/S transformation.

0013A bit series that is processed by the COD1 to COD4 at this time is shown in Fig. 16. Since the serial data of 255 bits is processed by the 4 bit parallels, the bit positions at which each COD conducts the processing are different for each frame (shifted by one bit).

0014By the way, in order to resolve the above-mentioned shift of the bit positions at which each COD conducts the processing by means of a hardware, it is necessary to incorporate a buffer in the IC or to add a function capable of accommodating itself to the shift in the COD modules.

0015However, if such a means is arranged, the arrangement results in a lowering of a processing speed or large-sizing of the IC.

0016Next, operation of the receiving the FEC frame be explained. In a previously proposed FEC frame processing, an optical signal of 32,640 bits that has been input is divided into 128. Since this optical signal is processed by the even-number of circuits, the circuit size of an FEC frame transformation section becomes large, and the processing is inefficient.

0017Fig. 17 simply shows an arrangement of the FEC frame transformation section in relation to the prior proposals, and shows here that four parallel processing is applied to the even-number of the 255 bits optical signal transformed in a serial-parallel convertor 170.

0018The first bit is removed out of the respective optical signals to which the four parallel processing was applied in this manner, since it is an OH signal, and then, 239 - 255 bits of Reed Solomon signals (syndromes) are removed. This situation is shown in Fig. 18. An upper column to a lower column in the table show contents to be processed in each of frame transformation sections 171-174. It is shown that numbers with half-tone in this table are to be removed, respectively.

0019Features of a frame format, frame processing and apparatus to be described below, by way of example in illustration of the invention are that the hardware arrangement within the FEC-IC becomes comparatively simple, and high speed processing and small-sizing can be achieved and that a frame format for accomplishing the above-described features can be obtained with high compatibility with the conventional system.

0020According to an aspect of the present invention, there is provided a frame format used for a codec in which where the number of total bits used for an overhead, a data and an error correction code is B bits, and the frame includes at least one dummy bit with the bit number of the dummy bit(s) being D bits, the number A of total bits of one frame is A = B + D, and where the number of parallel processing inside the codec is P, the bit number D of the dummy bits satisfies <maths id="math0001" num=""><math display="block"><mrow><mi mathvariant="normal">D</mi><mo>=</mo><mi mathvariant="normal">P</mi><mo>×</mo><mi mathvariant="normal">n</mi><mo>−</mo><mi mathvariant="normal">B</mi><mo>;</mo></mrow></math><img file="EP0949780B1_D0001.tif" /></maths> wherein n is a natural number.

0021In addition, for the above-described error correction code, a Reed Solomon code is used as a typical example.

0022Also, it is possible to use the above-described dummy bits as an arbitrary information bit.

0023According to another example of the present invention, there is provided a frame processing method of a codec in which the number of parallel processing is P and, the frame includes at least one dummy bit wherein the bit number of the dummy bit(s) is D bits, and a data and an error correction code is B bits such that D = P x n - B, where n is a natural number, the method including the steps of: <ul id="ul0002" list-style="none" compact="compact"><li>receiving a bit series in which the number of data and error correction code bits in the frame is B;</li><li>processing a bit series in which the number of total bits of one frame is A bits;</li><li>adding a number of dummy bits D to the frame format before the data is input to the FEC coding/decoding section;</li><li>adding an error correction code;</li><li>processing the resulting frame so that bit positions of the bit series which are processed by each parallel processing section are not different for every frame.</li></ul>

0024In addition, in the case in which the number of total bits used for an overhead, a data and an error correction code is B bits, and the number of parallel processing of the codec is P the bit number ofD of the above-described dummy bits is D = P x n - B (n is a natural number).

0025Also, if the above-described dummy bits are processed as an arbitrary information bit, it is possible to incorporate information into the dummy bits.

0026In the frame format for the codec to be described below as example in illustration of the present invention, the dummy bits are added to a frame arrangement that has been used conventionally, in accordance with the number of parallel processing operations inside the codec.

0027The above-described features are obtained by one exemplary FEC frame processing method in which an FEC frame included in an optical signal to be input is divided into one hundred twenty eight, and the optical signal divided into one hundred twenty eight is processed by means of a three parallel method in applying serial-parallel converting to the optical signal, and by an FEC frame processing method in which an optical signal to which serial/parallel converting is applied in accordance with a three parallel method is output as an optical signal forming an FEC frame by means of multiplexing of one hundred twenty eight.

0028There will also be described an exemplary FEC frame processing apparatus which has a serial/parallel convertor for converting an FEC frame of a serial system, which is divided into one hundred twenty eight, into three parallels, and bit removal means for removing a bit at a previously fixed bit position of each signal that was converted.

0029In a FEC frame processing method to be described as an example in illustration of the present invention, after an FEC frame included in an optical signal to be input and output is divided into 128, the optical signal divided into one hundred twenty eight is processed by means of the three parallel method. According to such three parallel processing, the removal of the OH signal and the Reed Solomon signals can be easily conducted, and the scale of the hardware circuit to be mounted for processing the FEC frame is reduced. In other words, as a result of adopting the three parallel method, since a frame pattern that is processed in each frame transformation becomes to be one pattern, the processing is simplified, and it is possible to reduce the scale of the hardware circuit to be mounted.

0030The following description and drawings disclose, by means of examples, the invention which is characterised in the appended claims, whose terms determine the extent of the protection conferred hereby.

0031In the drawings:- <ul id="ul0003" list-style="none" compact="compact"><li>Fig. 1 is a view showing one example of a frame format for a high speed FEC-IC,</li><li>Fig. 2 is a block diagram showing one example of the high speed FEC-IC,</li><li>Fig. 3 is a view showing an example of a serial data which is input to the high speed FEC-IC shown in Fig. 2,</li><li>Fig. 4 is a view showing positions of bits which are processed by each COD of the high speed FEC-IC shown in Fig. 2,</li><li>Fig. 5 is a block diagram showing a generalized high speed FEC-IC,</li><li>Fig. 6 is a view for explaining a generalized frame format,</li><li>Fig. 7 is a block diagram showing an embodiment of a circuit arrangement appropriate for conducting an FEC frame processing method (reception),</li><li>Fig. 8 is a block diagram showing an embodiment of an FEC frame transformation section appropriate for conducting the FEC frame processing method,</li><li>Fig. 9 is an explanation view of an FEC frame of an optical signal to be processed,</li><li>Fig. 10 is an explanation view of a frame format after serial/parallel converting,</li><li>Fig. 11 is an explanation view of a data array after a frame transformation, and</li><li>Fig. 12 is a block diagram showing an embodiment of a circuit arrangement appropriate for conducting an FEC frame processing method (transmission).</li></ul>

0032First, one example of a frame format for a high speed FEC-IC will be explained. Fig. 1 is a view showing one example of a frame format for a high speed FEC-IC.

0033In the conventional frame format, one frame is constructed of a total of 255 bits in which the first one bit is an overhead (OH), 238 bits are data, and the remaining 16 bits are Reed Solomon codes.

0034However, in the frame format for the high speed FEC-IC to be described in illustration of the present invention, in addition to the conventional frame format, by taking into account that 4 bit parallel processing is applied to inputs in the IC, 256 bits are realized by adding a dummy bit of 1 bit.

0035Now, a high speed FEC-IC to which the frame format for the high speed FEC -IC is input will be described. Fig. 2 is a block diagram showing one example of the high-speed FEC-IC.

0036This high speed FEC-IC operates at 300 MHZ so as to conduct 8 bit parallel processing (input/output #1 to #8).

0037Also, each input (#1 to #8) of the 8 bit parallels is further divided to 4 bit parallels by means of serial-parallel (S/P) convertors 21a - 21h, and the speed is reduced to a speed at which code processing for a correction code can be conducted.

0038In each of COD modules 22a - 22d, Reed Solomon codes are calculated and added to the frame format. A dummy bit of 1 bit is added to the frame format before the data is input to the FEC coding/decoding parallel processing section.

0039Data output from each of the COD modules 22a - 22d are input to parallel-serial (P/S) transformations 23a - 23h, and the speed is restored to the original transmission speed.

0040Next, the operation of this embodiment will be explained. In order to make the explanation easy to understand, the operation will be explained by focusing on an input #1 in Fig. 2. Actually, the operation explained below is processed from #1 to #8 in parallel.

0041First, a serial data of 256 bits as shown in Fig. 3 is input to the input #1. Then, this serial data of 256 bits is transformed to a 4 bit parallel data by means of the S/P transformation 21a. Bit series which are processed by each of the COD 22a to the COD 22d at this time are shown in Fig. 4.

0042Since the dummy bit is being added to by 1 bit, 256 can be divided by 4 and positions of the bits which are processed by each of the COD 22a to 22d do not change for every frame, and a task such as a bit shift which occurs in the above-mentioned conventional frame arrangement can be avoided. In addition, 0 or 1 which does not have a specific meaning can be allocated to the dummy bit, and some information can be allocated, however. In the above-mentioned example, even though 1 + 4 x N bits (N is a natural number) are allocated to the dummy bit, much information can be put on without causing a shift of the bit positions. Management information of a transmission system and so forth can be the information to be put on.

0043Although, in the above-mentioned example, an example of one bit as the dummy bit was explained, a case in which the frame format is generalized will be explained.

0044An FEC-IC to which a bit series is input is shown in Fig. 5. In Fig. 5, the FEC-IC is shown, in which the number of processing in the FEC-IC is K, and the number of parallel processing of each processing is P.

0045Here, assuming that the number of parallel processing steps inside the FEC-IC is P, the number of bits of the conventional frame format is B, and the number of bits of the dummy bit is D, a proposed frame format can be represented as shown in Fig. 6. However, the bit number D of the dummy bit must satisfy the following equation: <maths id="math0002" num="(1)"><math display="block"><mrow><mi mathvariant="normal">B</mi><mo>+</mo><mi mathvariant="normal">D</mi><mo>=</mo><mi mathvariant="normal">P</mi><mo>×</mo><mi mathvariant="normal">N</mi><mrow><mo>(</mo><mrow><mi mathvariant="normal">N</mi><mi mathvariant="normal"> </mi><mi mathvariant="normal">is</mi><mi mathvariant="normal"> </mi><mi mathvariant="normal">a</mi><mi mathvariant="normal"> </mi><mi mathvariant="normal">natural</mi><mi mathvariant="normal"> </mi><mi mathvariant="normal">number</mi></mrow><mo>)</mo></mrow></mrow></math><img file="EP0949780B1_D0002.tif" /></maths>

0046For example, if in the above-mentioned example P = 4 and B = 255, and if these values are assigned into the equation (1), <maths id="math0003" num="(2)"><math display="block"><mrow><mn>255</mn><mo>+</mo><mi mathvariant="normal">D</mi><mo>=</mo><mn>4</mn><mo>×</mo><mi mathvariant="normal">N</mi></mrow></math><img file="EP0949780B1_D0003.tif" /></maths>

0047Since D is a positive integer N ≧ 64 and if a case of N = 64 is considered, <maths id="math0004" num="(3)"><math display="block"><mrow><mn>255</mn><mo>+</mo><mi mathvariant="normal">D</mi><mo>=</mo><mn>256</mn></mrow></math><img file="EP0949780B1_D0004.tif" /></maths> and accordingly, D can be set: D =1 1 bit.

0048Also, in the case in which it is desired that much information is put on the dummy bit, N is set: N = 65, for example, <maths id="math0005" num="(4)"><math display="block"><mrow><mn>255</mn><mo>+</mo><mi mathvariant="normal">D</mi><mo>=</mo><mn>260</mn></mrow></math><img file="EP0949780B1_D0005.tif" /></maths> and accordingly, D can be set: D = 5 bits.

0049By using the frame format described in a type of the high speed FEC-IC in which the speed is reduced by means of the S/P transformation inside the IC, compared with the case in which the conventional frame arrangement is employed, the number of buffers in the FEC-IC becomes less, the hardware arrangement becomes more simple, and a high speed and small-sizing of the IC can be realized.

0050Also, since a format equivalent to the previously proposed format can be obtained by removing only a dummy bit by means of a dummy bit removing circuit, a high degree of compatibility with the previously proposed conventional system is possible.

0051Next, frame processing illustrative of the present invention will be described. Referring to Fig. 7 showing an arrangement of a first embodiment, in an optical signal receiving section 71, an optical signal formed of an FEC frame is received, and the optical signal formed of the FEC frame is divided into eight.

0052In a first FEC frame decode section 72, each signal that was divided into eight is divided by two and into sixteen signals. In a second FEC frame decode section 73, the optical signals that were previously divided by two are further divided by eight and into one hundred twenty eight signals.

0053A serial-parallel convertor 74 at the next stage is an assembly of individual serial-parallel convertors 74a-74c arranged correspondingly to the respective signals. The individual serial-parallel convertors 74a-74c apply serial-parallel converting to the signals that were divided into one hundred twenty eight through the above-mentioned process, and provide the signals to three respective FEC frame transformation sections 81 - 83 that are arranged as shown in Fig. 8. An FEC frame transformation section 75 of Fig. 7 is formed by three such FEC frame transformation sections 84-83.

0054Out of the respective optical signals that were divided into three in the FEC frame transformation section 75. as mentioned below with reference to Fig. 9, an OH signal and Reed Solomon signals of the FEC frame are removed.

0055Fig. 9 shows the FEC frame of an optical signal that is input to the optical signal receiving section 71, in which the FEC frame is constructed of a format of a total of 32,640 bits, which is formed of an OH signal of 128 bits, information signals of 30,464 (= 238 x 128) bits, and RS signals of 2,048 (= 16 × 128) bits.

0056If the optical signal of Fig. 9 is divided into one hundred twenty eight in a manner as mentioned in connection with Fig. 7, when the optical signals are input to the serial-parallel convertor 74, the FEC frame of Fig. 9 comes to have a frame format of a total of 255 bits consisting of an OH signal of 1 bit, information signals of 238 bits and RS signals of 16 bits, as shown in Fig. 10. The signals that were divided into one hundred twenty eight are separated into three signals and processed through the serial-parallel convertor 74.

0057In the FEC frame transformation sections 81 - 83 of Fig. 8, by removing bits, which are always fixed, such as 1 (= an OH signal) and 239-255 (=RS signals) that correspond to half-tone parts shown in Fig. 11. it is possible to remove the OH signal and the Reed Solomon signals (syndromes) that are included the optical signal.

0058With regard to the effect of the presently proposed arrangement, conventionally, the signals are divided into four and are processed by means of the serial-parallel convertor 170 shown in Fig. 17. However, in the case in which the signals are divided into four, since as shown in Fig. 18 there are four patterns of the OH signal and the Reed Solomon signals to be removed, the scale of the circuit on which the frame transformation sections 171-174 of Fig. 17 are mounted becomes large. To the contrary, in the present arrangement, by dividing the signals into three as shown in Fig. 8, it becomes possible to reduce the scale of the circuit hardware.

0059Although Fig. 7 and Fig. 8 are embodiments showing the processing for the signals that are input (received), similarly the same concept can be used for signals that are output (transmitted). Fig. 12 shows this arrangement, and although it is almost the same arrangement as Fig. 7, signals go forward in the opposite direction. In an FEC frame transformation section 121, the three parallel method is applied for processing a data that is formatted as shown in Fig. 11. After that, the data is transformed into serial signals in the serial-parallel convertors 122.

0060The signals obtained that were divided into one hundred twenty eight are encoded into sixteen signals in a first FEC frame encode section 123. and then, the signals are encoded into eight signals in a second FEC frame encode section 124, and then, an optical signal is output (transmitted) through an optical signal transmitting section 125.

0061In the processing during such an output also, the arrangement operates in a similar way to the case of the input, and by dividing the signals into three and processing them, the removal of unnecessary signals can be conducted by means of a simple circuit arrangement, and it is possible to reduce the scale of the circuit hardware to be provided.

0062It will be understood that although particular arrangements have been described, by way of example in illustration of the present invention, variations and modifications thereof, as well as other arrangements, may be conceived within the scope of the appended claims.