Offset autonomous input/output controller

0001The present invention relates to an input-output controller to cooperate with the central unit of a computer that communicates with various peripheral electronic equipment. The IO controller can be used particularly in avionics.

0002Currently in aerodynes several computers coexist, they each fly a single application. For application, the autopilot means, for example, the proximity detection system of the soil, the protection system against step etc .....

0003In each computer CPU is connected by a parallel bus to the peripheral electronic equipment belonging to the application. This connection parallel bus can transmit broadband data but it requires a large number of connection pins.

0004Such a connection brings some uncertainty because, if a failure occurs, all data passing over this connection is lost. Because each application is treated independently insecurity is tolerable.

0005With the significant development of the speed and capacity of processors and to reduce costs, it is conceivable that a single CPU controls several applications but it entails a new risk of error propagation between applications designed to increase insecurity at each application.

0006The European patent application EP 0694842 describes a method for securing the flow of linear sequences of orders executed by a processor to guard against error propagation between different applications processed by the same CPU by enabling to check the read addressing a memory storing instructions to be executed in sequence.

0007The present invention aims to fight against the propagation of errors between different applications processed by the same CPU in intervening in the computer input-output interfacing between the CPU of the computer and various peripheral electronic equipment , external to the computer used by the applications processed by the CPU.

0008It relates to a controller IO defines as claimed in claim 1.

0009The IO controller is autonomous and can work with all types of CPU and peripheral electronic equipment.

0010One or more types of instructions from the memory can be described as pseudo-instructions formed by lists of analogue values, stored in the memory, different types corresponding to lists of different kinds of values.

0011Some instructions other than the pseudo-instructions from memory, can form blocks executed after a synchronization instruction.

0012The sequencer device may allocate equal time slots for the successive processing of each type of instructions, then granted a period of time without treatment, possibly zero, before starting treatment. Each type of instruction is treated with the same frequency.

0013A more sophisticated sequencing may be envisaged so as to allow a treatment with frequencies adapted to the different types of instructions. Such sequencing responds much better to the needs encountered in an avionics application.

0014The sequencer device may allocate equal time slots in the processing of instructions by type, each type of instructions being assigned an occurrence period, the first type of instructions treated with the smallest period, this period being said reference period and a so-called reference phase, the other types of instructions having a phase constraint in relation to the reference phase, these other types of instructions being processed with a rank based on the ascending order of their constraint phase, their period being a multiple of the reference period.

0015It is easier to choose by convention a zero reference phase.

0016The reference period may be a multiple of a length, said base period, which corresponds to the access to instruction time in memory.

0017It is advantageous to express the phase constraint of the second type of instructions which is processed by a phase increment in relation to the reference phase. Those of the types of instructions of rank higher by a phase increment in relation to the phase constraint of the type of instructions which is processed in the preceding rank.

0018A sequencer device for treating different types of instructions with different frequencies can include:<ul><li>a device providing a current phase called from a base clock whose period corresponds to the access to instruction time in memory,</li><li>a first basic clock divider receiving in addition to the base clock, the value of the reference period and which generates pulses having the reference period and the reference phase;</li><li>a set pre divider divider respectively associated with each of the other types of instructions to be processed, receiving the base clock and the reference period,</li></ul><sl><li>each predivider receiving the value of the reference period and a start signal from the comparison between the phase constraint of the associated type instructions and the current phase, and generating, to the divider of the same set that it, a signal period equal to the reference period and phased according to the phase constraint of the associated type of instructions,</li><li>each divider generating pulses having the period and the phase constraint of the associated type of instructions.</li></sl>

0019The device delivering the current phase may be achieved by a saturation counter receiving the base clock.

0020The counter saturation can be reset during a reclosing of the IO controller or by a signal from a reset device.

0021Each predivider may be associated with a comparator which issues the start signal, each comparator receiving the current phase and the phase constraint, in relation to the reference phase, of the associated type of instructions.

0022The first comparator directly receives the value of the phase increment of the second type of instructions in relation to the reference phase while the other comparators are each associated with an adder, each adder delivering the phase constraint, in relation to the reference phase, the associated type of instructions, and type the receiving phase constraint of instructions treated with the previous row and the value of the phase increment in relation to the aforementioned constraints.

0023Another instruction that a pseudo-instruction may be of ARINC 429 and include thirty-two bits including a code on at most eight bits and a parameter on at most twenty-one bits.

0024The values ​​of the time of occurrence and the phase constraints of the various types of instructions can be coded in the parameter of one or more loading instructions.

0025The input-output controller according to the invention may include a code analysis device which decodes the instruction codes.

0026A pseudo-instruction is executed under the control of an activation instruction. It includes thirty-two bits a list of analogue values ​​which are coded either in the form of increments, either as absolute values.

0027The input-output controller may have to manage pseudo-instructions, steering means of pseudo-instructions that receive activation instructions, which keep the codes of activation instructions and are responsible for access to memory via an access pointer. The code analysis device receives the pseudo-instructions and the codes of the activation instructions of pseudo-instructions control means.

0028If multiple memory accesses are required to extract an instruction, it is desirable that the input-output controller includes memory management means with a buffer block managed by the sequencer device. The buffer unit can also be controlled by means of pseudo-pilot instructions.

0029The memory management means may also include a memory download sequencer device from instructions received from the CPU.

0030It is advantageous that the input-output controller can communicate acquisition or generation with bidirectional interface devices electronic equipment by several channels may be configured such parallel bus, link carrying Boolean, in serial, in association with optical encoder, and for that the input-output controller may include at least one interface device connected to the peripheral electronic equipment at least one of these interface channels. This interface device is quite standard.

0031Similarly, there may be provided an interface device with the central unit, connected to the central unit via the input and output lines.

0032The invention will be better understood and other features and advantages will appear on reading the description of embodiments illustrated by the attached figures which show:<ul><li>Figure 1 at least one input-output controller according to the invention in perspective;</li><li>Figure 2 the structure of a controller IO according to the invention;</li><li>Figure 3 a sequencer device capable of processing the different types of instructions with suitable frequencies.</li></ul>

0033Figure 1 shows very schematically a first CO IO controller according to the invention in its environment. In this example, it is intended for use in an avionics application.

0034This CO IO controller is for cooperating with a central processing unit CPU of a computer (not shown) which communicates with peripheral electronic equipment EQ. In the avionics application, these devices EQ electronics are sensors or actuators. The input-output controller CO receives instructions of a first type of the central unit UC by a line Isse serial input and transmits information to the central unit UC by at least one output line Iss series. In the example described, preferably, two lines ISS1 series, output Iss2 are used. It is possible to provide one of the lines series ISS1 output will emit information via the input-output controller CO, only from the peripheral electronic equipment EQ and the other Iss2 can transmit information , via the CO-IO controller, from electronic equipment EQ devices but also from other devices as will be seen later. Optionally multiple controllers IO according to the invention can be connected to one central unit UC by the same line series of lse entry. In Figure 1 a second input-output controller CO has been shown in dotted lines. This second input-output controller CO is connected to the central unit UC by at least one output line Iss'.

0035Each input-output controller CO, CO is intended to cooperate with a respective referenced PROM PROM external to the central unit UC. They receive instructions from one or more types of PROM, PROM 'associated.

0036The following description is for the CO IO controller, the other would be similar. CO IO controller is intended to communicate acquisition or generation of information with peripheral electronic equipment EQ. Several routes or routes of VP1 interface, VP2, VP3, VP4 bidirectional fate provided between the CO IO controller and peripheral electronic equipment EQ. These channels interface VP1, VP2, VP3, VP4 may be configured by the instructions received by the input-output controller CO, including parallel bus, by carrying Boolean links, serial links and even bonds with optical encoder and can function as input or output. In the example shown in Figure 1, it is assumed that a given instant the first VP1 channel is configured in parallel input bus, the second channel is configured in VP2 link carrying Boolean output, the third channel is configured VP3 connected in series and output as the fourth VP4 channel is configured in association with the optical encoder input.

0037Figure 2 shows in detail the different functions of an input-output controller of the invention.

0038CO IO controller has at least one DI interface device with peripheral electronic equipment EQ. Dl this interface device is connected to electronic equipment EQ devices by at least one channel interface VP1, VP2, VP3, VP4. In the avionics application of the described example, four identical devices Dl standardized series-parallel interfaces are sufficient to communicate with all the electronic equipment EQ devices present. More details on the interface devices DI will be given later.

0039CO IO controller has a DIP interface device connected to the central unit UC by Ise input and output lines ISS1, Iss2.

0040CO IO controller for receiving instructions from a share of the CPU CPU and secondly PROM and deal with that is to say in a decode device code analysis DAC, refer them to the appropriate bodies, that is to say the electronic equipment EQ devices or the central unit UC. CO IO controller processes the instructions alternately according to their type and comprises for this a sequencer device SEQ. Its operation will be described later.

0041One or more types of instructions from the PROM can be described as pseudo-instructions. A pseudo-instruction consists of a list of analog values ​​stored in the PROM. These pseudo-instructions are operated under the control of an activation instruction and until a deactivation instruction.

0042In the avionics application, these lists of analogue values ​​may correspond to a waveform to be issued to excite a sensor or an audio signal, for example, an alarm to sound to alert the crew. The various types corresponding to lists of various kinds of values. In the example described, it is assumed that two different types of instructions in the form of analog values ​​lists may come from the PROM. In the following description when the term is used without special instruction indication this also includes pseudo-instructions.

0043Some instructions other than the pseudo-instructions from the PROM can be executed in sequence after one synchronization instruction.

0044Another instruction that a pseudo-instruction is modeled on that of a word ARINC 429 with 32 bits. It includes a code of 8 bits (bits 0-7) by indicating the action to perform, bits 8 and 9 are used for safety. A share acquisition peripheral electronic equipment EQ data to the central unit UC is coded on five bits (bits 0-4). These bits indicate the nature of the acquisition. Bit 5 shows information about the ISS1 output serial line or Iss2 to borrow to the CPU and bit CPU 6 and 7 provide information on the interface device Dl and route concerned interface.

0045Similarly, a data generation action to an electronic equipment EQ device is encoded on 6 bits (bits 0 to 5). These bits indicate the nature of the data generation. Bits 6 and 7 provide information on the DI interface device and route concerned interface.

0046Bits 8 and 9 of an instruction that comes from the central unit UC identify the IO controller CO, CO recipient since there may be several.

0047When the instruction is to issue a given CPU to CPU, the code includes a label which must precede the given issue. When the instruction is to issue a given a peripheral electronic equipment EQ to the bit CPU CPU 8 and 9 identify the issuer.

0048Instruction also includes 21 bits (10-30) by a parameter, this parameter can be a base address in the PROM, for example to download instructions from the PROM, synchronization instructions or activation, eg programming data to program the sequencing, a value to be transmitted to the peripheral electronic equipment EQ or to the central unit UC, a default time when no other parameters are required. When the parameter has less than 21 bits, the encoded data are on the most significant bits (10 and following bits). Bit 31 is a parity bit and parity of an instruction is odd.

0049Some instructions can use 16-bit parameter for encoding data and the following five bits as control. These instructions are preferably used to control the DI interface devices that are connected peripheral electronic equipment EQ.

0050The instructions from the PROM may use certain codes, such as those corresponding to the deletion, downloading and replaying the PROM. These codes are for the exclusive use of the central unit UC.

0051An activation instruction code behave like the action to perform, which can match the recipient of analog values ​​and parameters as the original points to address the sequence of analog values ​​to be extracted from the PROM.

0052CO IO controller also includes control means SP pseudo-instructions. These SPs control means receives the DAC code analysis device, the activation instructions and deactivation. They retain the code activation instructions and are responsible for access to the PROM via POIN access pointer and the issuance of the pseudo-instruction and code to the DAC code analyzer.

0053The POIN access pointer is second to access the PROM after a synchronization instruction which has as a parameter the initial tally address of the first instruction of the sequence to execute or to generate standardized values ​​that are used in the erase sequences and programming PROM.

0054Put bits butt 8 instructions in sequence from the PROM may encode the current address of the access pointer to the PROM according to the French Patent Publication No. 2723222 in the name of the applicant. Bit 9 identifies the entry point of a sequence stored in the PROM.

0055The pseudo-instructions read PROM may take different formats of 32 bits depending on the dynamics and magnitude analog values ​​to be transmitted. Analog values ​​can be encoded as increment or as an absolute value.

0056For example, a pseudo-instruction can hold 3 9-bit values ​​or four values ​​of 7 bits or even 2 14-bit values.

0057The last bit is a parity bit and the parity of a pseudo-instruction is odd. The penultimate bit is a security bit. Placed end to end security successive bits of a pseudo-code instructions list can reverse the current address of the access pointer to the PROM according to the French Patent Publication No. 2723222 in the name of the applicant.

0058Choosing a reverse coding for the instruction sequences and the sequences of analog values ​​ensures the impossibility for the program to perform inadvertently an analog sequence of values ​​instead of a sequence of instructions and vice versa .

0059then we can detect and prevent the execution of a sequence not matching the execution context by the use of different coding invariants depending on context.

0060The other free bits of pseudo-instructions indicate if the values ​​are encoded as incremental or absolute and whether it is with or without an ending sequence.

0061This encoding form of increment or absolute value optimizes the space occupied in the PROM including sounds. The low dynamic periods may advantageously be encoded as increment is 7 bits or 9 bits, while the periods of low amplitudes can be coded as absolute value of 9-bit or 7-bit increment. 14-bit values ​​as to represent absolute values.

0062We have seen that the DAC code analysis device receives instructions of a first type of the central unit UC and instructions of one or more types of PROM. This alternative way to treat as a timing allocated by the sequencer device SEQ. The timing can be fixed or programmable.

0063More generally, if the CO input-output controller has to process instructions of the n types, the sequencer SEQ device can cut the processing time into n + 1 slices (n is an integer greater than or equal to two), n these being equal installments devoted to successive processing of each of the n types of instructions, the last tranche of possibly zero programmable duration adjusts the recurrence of the sequencing. At the end of the last installment the treatment again.

0064It is assumed in the example described that the input-output controller CO receives three types of instructions from the PROM which two types correspond to pseudo-instructions and an instruction type CPU CPU. These four types of instructions are referenced CO1 respectively for pseudo-instructions corresponding to excitations CO2 for instructions from the PROM, CO3 for pseudo-instructions corresponding to the audio signals, CO4 for instructions from the CPU CPU.

0065During the first stage of processing time will be processed the CO1 instructions, while the second tranche will be treated the CO2 instructions while the third tranche will be treated the CO3 instructions during the fourth tranche will be treated the CD4 instructions and during the fifth tranche no treatment is performed.

0066The minimum time for access to the PROM or atomic time is between 2 and 8 times of the general clock of the computer. For a 20 MHz clock to the atomic time can be set from 50ns to 50ns of 100 ns to 400 ns.

0067Successive access to the PROM are required to read an instruction, in the case of a memory 8-bit and 32-bit instruction is that of the example described, four ports are required. The time required to access an instruction is equal to four times the atomic time. This duration is called base period and its inverse base frequency.

0068This shows that in the event of an atomic time of 200 ns and duration of the fifth tranche of 400 ns, the maximum frequency of treatment instructions or pseudo-instructions of contexts is 277.8 kHz . The recurrence of the sequencing is 3.6 microseconds. It is then possible to generate an excitation at 5 kHz with 55.5 samples per period or excitation at 2.78 kHz with 100 samples per period.

0069Assuming a 200 ns atomic time and duration of the fifth tranche zero, the maximum processing rate of one type of instruction is 312.5 kHz. The recurrence of the sequencing is 3.2 microseconds. It is possible to generate an excitation at 5 kHz with 62.5 samples per period or excitation at 3.125 kHz with 100 samples per period.

0070This sequencing allocates equal time slots for different types of instructions and different types of instructions are treated with the same frequency.

0071More sophisticated sequencing can increase the frequency of treatment of a type of instructions compared to that of other types and adjust the frequency of treatment depending on the type of instructions. In the avionics application, pseudo-instructions that transmit stimuli have the highest frequency.

0072The sequencer device SEQ can cut processing time by a succession of equal time slices, these slices are devoted to processing instructions according to their type. It is assumed that the different types of instructions are the same as those described in the previous example.

0073For each type of instructions, an occurrence period is defined. The first type of instructions CO1 treaty is one that has the smallest period of occurrence. This period is called the reference period and is defined by a multiple of the base period. The first type of instructions CO1 treaty is assigned a so-called reference phase which by convention is chosen preferably zero. To ensure that at any given time only one type of instructions is processed, the other types of instructions CO2, CO3, CO4 have a phase constraint in relation to the reference phase and these other types of instructions CO2 , CO3, CO4 are assigned a rank of treatment (2 to n) according to the ascending order of their phase constraint.

0074The period of the second type of instructions CO2 treaty is a multiple of the reference period. Its phase constraint is expressed by the phase increment in relation to the reference phase, this increment is counted in base period.

0075The period of the third type of instructions CO3 treaty is a multiple of the reference period. Its phase constraint is expressed by the phase increment from the constraint of the second type of instructions CO2 treated stage, this increment is counted base period.

0076More generally the type of instructions treated with the rank i (integer greater than two) for a period of a multiple of the reference period and the phase constraint is expressed by the phase increment from the phase constraint type instruction treated with the rank i -1, this increment is counted base period. Described in Example i is an integer between 3 and 4.

0077The values ​​of the periods, reference phase (if not null) and of the phase constraints can be encoded on several bits, for example three. This timing can be programmed in the form of one or more loading instructions. The value of the reference phase may also be coded if it is not void.

0078In the example four types of instructions CO1, CO2, CO3, CO4 a single load instruction whose parameter has 21 bits is enough if one considers that the reference phase is zero.

0079The first three bits of the parameter aaa encode the reference period.

0080Here are the meanings of the codes used:<sl><li>001: processing with the base period. In this case is only the first type of instructions is processed, or if another type of instructions is processed, this first type of instruction is inactive and the relevant reference period only to define the period of the other type 'processed instructions.</li><li>010: processing with the base period multiplied by 2</li><li>011: processing with the base period multiplied by 3</li><li>100: processing with the base period multiplied by 4</li><li>101: processing with the base period multiplied by 5</li><li>110: processing with the base period multiplied by 6</li><li>111: processing with the base period multiplied by 7</li><li>000: processing with the base period multiplied by 8</li></sl>

0081The reference phase is zero, it is not coded.

0082The next three bits of the parameter bbb encode the phase constraint of the second type of instructions CO2.

0083Here are the meanings of the codes used:<sl><li>000: unused type of instructions,</li><li>001: phase increment of a base period relative to the reference phase,</li><li>010: phase increment of two basic periods in relation to the reference phase,</li><li>011: phase increment of three basic periods in relation to the reference phase,</li><li>100: phase increment by four base periods in relation to the reference phase, </li><li>101: phase increment of five basic periods in relation to the reference phase,</li><li>110: phase increment of six basic periods in relation to the reference phase,</li><li>111: phase increment of seven basic periods in relation to the reference phase,</li></sl>

0084The following three bits ccc code the period of the second type of instructions CO2.

0085Here are the meanings of the codes used:<sl><li>001: processing with the base period,</li><li>010: processing with a double period of the reference period,</li><li>011: processing with a triple period of the reference period,</li><li>100: processing with a quadruple period of the reference period,</li><li>101: processing with a period of five times the reference period,</li><li>110: processing with a six-period of the reference period,</li><li>111: processing with a period of seven times the reference period,</li><li>000: processing with a period eight times the reference period.</li></sl>

0086The following three bits ddd code the phase constraint of the third type of instructions CO3.

0087Here are the meanings of the codes used:<sl><li>000: unused type of instructions</li><li>001: phase increment of a base period relative to the phase constraint of the second type of instructions,</li><li>010: phase increment by two base periods in relation to the phase constraint of the second type of instructions,</li><li>011: phase increment by three base periods in relation to the phase constraint of the second type of instructions,</li><li>100: phase increment by four base periods in relation to the phase constraint of the second type of instructions,</li><li>101: phase increment of five basic periods in relation to the phase constraint of the second type of instructions, </li><li>110: phase increment by six base periods in relation to the phase constraint of the second type of instructions.</li><li>111: phase increment of seven basic periods in relation to the phase constraint of the second type of instructions;</li></sl>

0088The following three bits eee encode the period of the third type of instructions CO3.

0089Here are the meanings of the codes used:<sl><li>001: processing with the base period,</li><li>010: processing with a double period of the reference period,</li><li>011: processing with a triple period of the reference period,</li><li>100: processing with a quadruple period of the reference period.</li><li>101: processing with a period of five times the reference period,</li><li>110: processing with a six-period of the reference period,</li><li>111: processing with a period of seven times the reference period,</li><li>000: processing with a period eight times the reference period.</li></sl>

0090The three following bits fff encode the phase constraint of the fourth type of instructions CO4.

0091Here are the meanings of the codes used:<sl><li>000: unused type of instructions,</li><li>001: phase increment of a base period relative to the phase constraint of the third type of instructions,</li><li>010: phase increment of two basic periods in relation to the phase constraint of the third type of instructions,</li><li>011: phase increment of three basic periods in relation to the phase constraint of the third type of instructions,</li><li>100: phase increment by four base periods in relation to the phase constraint of the third type of instructions,</li><li>101: phase increment of five basic periods in relation to the phase constraint of the third type of instructions,</li><li>110: phase increment of six basic periods in relation to the phase constraint of the third type of instructions, </li><li>111: phase increment of seven basic periods in relation to the phase constraint of the third type of instructions.</li></sl>

0092The following three bits ggg encode the period of the fourth type of instructions CO4.

0093Here are the meanings of the codes used:<sl><li>001: processing with the base period,</li><li>010: processing with a double period of the reference period,</li><li>011: processing with a triple period of the reference period,</li><li>100: processing with a quadruple period of the reference period,</li><li>101: processing with a period of five times the reference period,</li><li>110: processing with a six-period of the reference period,</li><li>111: processing with a period heptuple of the reference period,</li><li>000: processing with a period eight times the reference period.</li></sl>

00943 shows a diagram of an example of a sequencer SEQ device capable of performing the sequence which has just been described.

0095The sequencer SEQ device CPH comprises a device delivering a current phase that a first divider D0 associated with the first type of processed instructions and a prescaler-divider assembly (PD1, D1), (PD2, D2), (PD3, D3) associated to each of the other types of instructions to be processed.

0096CPH device delivering the current phase receives pulses from a base clock hb completes the basic frequency. In the example described the device is a CPH counter saturation, that is, after a reset, it generates a counting sequence up to that each of the prescaler divider-sets has started with the strain correct phase.

0097After the counting sequence, it remains blocked in its final state and can not be re initialized by an appropriate command which can be a general re engagement CO IO controller or can be derived from a recalibration REC optional device that detects abnormal events, such as the treatment of more than one type of instructions at a time or multiple times corresponding to the common to all periods of different types of instructions which allows more frequent resetting.

0098The first divider D0 is a divisor of the base clock hb, he received the aaa value of the reference period and provides pulses having the reference period and the reference phase. These pulses correspond to the instants of beginning of treatment of first type instructions and have a duration equal to the duration of the period of the basic clock.

0099Each set predivider divider (PD1, D1), (PD2, D2), (PD3, D3) also receives hb base clock. Each pre divider PD1, PD2, PD3 receives the value of the reference period aaa and a start signal from the comparison between the phase constraint of the associated instruction type and the current phase.

0100Each predivider PD1, PD2, PD3 generates to the associated divider, a signal period equal to the reference period and is phased according to the phase constraint of the associated type of instructions.

0101Each divider D1, D2, D3 also receives the value of the period of the associated type of instructions. Each divider D1, D2, D3 therefore generates periodic pulses of duration equal to a base period with the period and the phase constraint of the associated type of instructions. These pulses correspond to moments of early treatment of associated type of instructions.

0102Each pre divider PD1 to PD3 is associated with a comparator C1 to C3 which issues the start signal. Each comparator C1, C2, C3, receives the current stage that compares the phase constraint, in relation to the reference phase, of the associated type of instructions. The first comparator C1 directly receives the value of the phase increment bbb relative to the reference phase, this value corresponds to the phase constraint of the second type of instructions CO2 treaty.

0103For other types of instructions CO3, CO4 rank greater than two, each comparator C2, C3 interacts with an adder A1, A2. Each adder A1, A2 delivers to the comparator C2, C3 the phase constraint, in relation to the reference phase, of the associated type of instructions. Each adder A1, A2 receives the stress of instructions model treaty of phase with the previous row and the value of the phase increment ddd, fff from the so-called phase constraint.

0104CO IO controller also includes MG management means of the PROM with a buffer block BT managed by the sequencer device SEQ and SP pilot means of pseudo-instructions. This buffer block BT accumulates in the example described, four consecutive bytes stored in the PROM so as to constitute a usable entity type instruction including the DAC code analyzer.

0105The central unit UC can control the downloading of the PROM. MG management means of the PROM have a SEQP memory sequencer device that receives input via lse series line erasure of all or part of the PROM instructions and / or loading instructions from a base address in the command parameter. This base address is transmitted to POIN access pointer. In the case of a delete instruction, the sequencer device SEQP product specific sequence to complete erasure or block by block from the base address.

0106After a load instruction, the sequencer SEQP device receives via the serial line one or more 32-bit words he just write from the base address respecting the programming sequence. If problems detected while writing, it is planned to update a storage device of ST encountered.

0107The DAC code analysis device has a DEC instruction decoding device that operates in priority order bits 0-9 instructions. rank bits 0 to 7 are analyzed to generate appropriate commands to perform the action contained in the instruction. Bits 8 and 9 of the statement are checked differently according to their origin as they do not express the same as previously described. These commands are sent to Dl identified horn interface device which also receives the parameter values.

0108SEC security blocks are also provided in the DAC code analysis device. These blocks check the consistency criteria are met such as the odd parity instructions or pseudo-instructions and safety course instructions and pseudo-instructions from the PROM.

0109The pseudo-instructions from the PROM pass before being decoded in a block buffer BTA having as many buffers that type of pseudo-instructions.

0110The contents of the storage device ST anomalies encountered by the DAC code analysis device and the SEQP sequencer device during operation can be transmitted to the central unit UC on request or by executing a statement in from the PROM. This transmission is done only by one of the transmission lines in the example described it is assumed that this is the series of Iss2 line out, ST storage device can be set to zero during a reset controller IO or a dedicated instruction.