Node interface in a data network

The invention relates to an interface for a data node of a data network, one equipped with such interface data nodes and a data node such comprehensive data.

The data node of such a data network communicate with each other via a bus line connecting them, wherein each data node may be the sender or receiver.

Such data networks are also in motor vehicles for some time used where it the term CAN (Car Area Network) known are. Such CAN systems include two open or ring-like line Community lines, namely a bus line for data and Message transmission and a power supply line to Supply of each node with a battery voltage.

The individual data nodes typically comprise a data processing unit, particularly in the form of a microcontroller, and a Power supply unit, in particular in the form of a voltage regulator, wherein both the microcontroller and the voltage regulator via an interface to the bus line or the power line are coupled.

Both the voltage regulator and particularly the microcontroller reduce battery life in active state. This resulted in a Data network whose data nodes are all in the active state to a correspondingly high consumption of electrical energy. This would lead to a relatively rapid draining the car battery if the vehicle is not used for a long time. this problem encountered conventionally in that the individual data nodes if their activity is not needed, in an idle state are switched and because of this idle state only in a Active state are brought when their activity is needed. For example In the case of a stationary vehicle, in particular when is equipped with an alarm system, cyclically checks the door contacts. For this Enabling data node is usually the Waking expression used.

In conventional CAN systems when a Data node data on the bus line are sent, all data nodes fully awakened. In each data node is doing on the interface of the voltage regulator is activated to voltage supply line of the to decrease the operating voltage and the microcontroller by supplying power supply in active mode to set.

One of a data node via the bus line message sent includes an address part and a data part. contains the address part the addresses of the data nodes with each transmitted message to be addressed. In this case, an address exclusively for a single data node or for a predetermined range of Data nodes to be determined.

The individual data nodes are equipped with address filtering, means what they can see whether it is the on at the address Bus line message sent to a specific address for them is or not.

Such addressing selection or address filtering, for example, be carried out with circuit arrangements and methods as in the own German patent applications 196 45 055.1 and 196 45 057.8 are given, the contents of which is hereby incorporated by reference made the disclosure of the present patent application will. In such an address selection method either the entire Adressenbitfolge at once or individual segments of predetermined Length of Adressenbitfolge with address words or Address segments compared, in each data node stored. If a data node, several different Address codes can be accepted, either a number of the to acceptable addresses or address segments corresponding Number Address filter required or used in addition to the Filter masks, defined by means of which for each Filterbitstellen is whether they for an acceptance of a received Adressenbitstelle only to take place when the address bit of the corresponding Adressenbitstelle with the associated Filterbitstelle matches, or if an acceptance is to take place regardless of whether with regard to the respectively considered Adressenbitstelle accordance with the relevant Filterbitstelle exists or not.

In conventional systems, the CAN-address filtering takes place in the Microcontroller instead. If sent by one data node data are, all data nodes are fully awakened to the microcontroller of each data node by activating the ability to enable to carry out the address filtering and to determine it, whether the wakeup causing message on the bus for the observed data node is intended or not. Since the voltage regulator and in particular the microcontroller in the active state relative consume a lot of electric energy, even leading a mode wherein the data nodes in the vehicle is stationary in an idle state offset and only now and then, mostly cyclic, in the active state be awakened, even at a relatively high power consumption and according to high load of the vehicle battery. Becomes a Such a vehicle parked for a long time, for example on a Airport car park during a long flight, the vehicle battery by such a cyclic wakeup of all data nodes be discharged after periods ranging from 1 to 2 weeks.

The invention is based on the object to remedy this situation and provide a method in particular for CAN systems, which to lower energy consumption and thus prolonged power capacity the vehicle battery even during longer operational pauses the vehicle performs.

This object is achieved in that the interface Equipped of each data node with an activation address filter is, so that the address filtering for a via the bus line transmitted activation command for selectively activating or Aufweckung are carried out by data nodes to interface can. This eliminates the need for activating address filtering the entire data nodes, in particular the microcontroller, wake and in the energy consuming active state to turn.

The interfaces of the individual data nodes require significantly less electric power than the microcontroller. In addition, you can see the interfaces keep in a low power state when no data on the Bus transfer. If an activation command via the Bus sent, in this embodiment, the interfaces of all Nodes in an activation address filtering or activation address identification enabling active status added. In this Check status on all interfaces, whether in the address portion of the bus line on sent message a specific address for them activation is included.

Only when an interface for a particular node's data activation address recognizes, it operates the activation of the associated Data node, for example, by activation of this data node associated voltage regulator, and thus the wakeup of the associated Microcontroller in its active state.

The Waking of interfaces in their state in which they enable the identification address can perform or filtering, happening preferably by means of a characteristic Rahmenstartbits, the transmitted the message frame of each on the bus line initiates message.

The programming interface of a node with regard to the data to be recognized by him address or addresses can from the associated Microcontrollers are effected.

Since the microcontroller conventional CAN systems a private address filter exhibit, the correctness of the associated interface conducted address identification upon waking the microcontroller be reviewed by this again. One can, however, also in microcontrollers, according to the invention specifically for a data network Interfaces are determined, the address identification portion omit, since an address filtering already in the upstream Interface takes place.

In a preferred embodiment, the individual interfaces not only by the start of a message frame in their active state woken up but additionally by an external alarm. The latter can, for example, come into play when a data node is one of the zentralverriegelbaren Türschlüsser and operated door lock this node to open or close this door becomes. This causes the associated with this door lock data nodes is actively switched via the external alarm and that this Data node to the other door locks associated data node via the bus line, a corresponding activation message sends to opening even with respect to this additional door locks to induce or closing.

In a preferred embodiment, regardless of whether a Interface of a data node is equipped with a private address filter or not, self-invention has value, includes the interface a Bittaktrückgewinnungseinrichtung, by means of which via the bus line bit sequences received bit clock can be reconstructed. The Interfaces the CAN systems are usually a private oscillator equipped, which is on the one hand for reasons of cost and on the other hand from the point of low energy consumption oscillators relatively low frequency stability is, for example, RC oscillators. If one uses this nachstimmbare oscillators can If these by means of the recovered bit clock with this bit clock synchronize.

In a particularly preferred embodiment of such a Bittaktrückgewinnungseinrichtung is used a Bitlängenzähler, the as a count clock, the oscillator signal of the oscillator is fed to interface and the Bitwechselstellen the received bit sequence are reported. Of the duration of the start bit of the respective message frame reached count of Bitlängenzählers is in a Bitlängenspeicher detained and whose memory value corresponding to the length the start bit. After this Bitlängenspeicherung the Bitlängenzähler is every time its count either stored in Bitlängenspeicher count has reached or when reported him that in the received bit sequence occurred a top edge of a new bit is reset and then starts again counting again. at each reset operation is a at the output of Bitlängenzählers issued Bitwechselsignal and these represent the Bitwechselsignale recovered bit clock is.

Conventional microcontrollers have its own oscillator high frequency stability, in general, a quartz oscillator on. Such oscillators not only its own energy needs but are also relatively expensive. In one embodiment of the invention, which also regardless of whether the interface of the respective data node with a private address filtering and / or a Bittaktrückgewinnungseinrichtung is provided, self-invention has value, have the Microcontrollers of individual data nodes not own oscillators on but the microcontroller are controlled by a clock, which is obtained by means of a controllable oscillator which, under the Control characteristic quantities is that transmitted through the bus line will. This can be done in the recovered associated interface use bit timing of each transmitted bit sequence or the frame length or frame part lengths over the bus transferred Message frame or cyclically transmitted specific frequency synchronization frame recourse.

In a preferred embodiment of this invention is used a frame length counter, the count clock as the oscillator output a controllable oscillator directly or by means of sale division a divider is supplied, wherein a counting operation of the frame length counter from Rahmenstartbit the relevant message or is Oszillatorsynchonisationsrahmens triggered. The frame end reached by the frame length counter count represents the respective Rahmenlängenistwert . By means of a comparison device is this Rahmenlängenistwert compared with a frame length setpoint and by means of which may result if this comparison Deviation of Rahmenlängenistwertes the frame length setpoint is retuned the controllable oscillator.

For systems whose transmitted bit sequences different frame lengths may have, you can take a bit counter to help, the beginning with each Rahmenstartbit a predetermined Number of bits is one, for example, using the recovered Bit clocks, the result of comparison between the Rahmenlängenistwert and the frame length set value at the time to Nachstimmsteuerung of the controllable oscillator is enabled to wherein the bit counter a predetermined number of bits since the occurrence the Rahmenstartbits counted. This predetermined bit count is equal to or smaller than the bit number of the shortest possible frame of the on the system transmitted bit sequences.

An interface according to a first aspect of the invention, namely with their own Activating address filter is given in Claim first an interface according to a second aspect of the invention, namely with Bittaktrückgewinnung, is defined in claim sixth An interface according to a third Aspect of the invention, wherein from a characteristic size of via the bus line bit sequences received a clock extraction for Control of the associated data processing unit, in particular of associated microcontroller is effected, is given in claim 10th A data node with such interfaces and a data network with respective data nodes are specified in claims 14 and 20 respectively. Advantageous developments of the individual aspects of the invention are defined in dependent claims.

The individual aspects of the invention and associated additional tasks and advantageous aspects will now detail using embodiments explained. In the accompanying drawings:<dl tsize="6"><dt>Fig. 1</dt><dd>a schematic representation of an example of a data network with data nodes and interfaces that are formed according to the invention could be;</dd><dt>FIG. 2</dt><dd>an embodiment of a data node, the present invention may be formed;</dd><dt>Fig. 3</dt><dd>an embodiment of a Adressenidentifizierungs- and Bittaktrückgewinnungsteils an inventive interface;</dd><dt>Fig. 4</dt><dd>a Bittaktrückgewinnungsteil an interface according to the invention;</dd><dt>Fig. 5</dt><dd>example waveforms in inventive context; and </dd><dt>Fig. 6</dt><dd>tunable an embodiment of a bus line Oscillator of a data node.</dd></dl>

An illustrated in Fig. 1 data network 11, for example, CAN data network, comprises a plurality of data nodes DK, the terms of data over a Bus 13 and energy supply as standard with a power supply line 15 to one another like a ring. In this case, each Data nodes DK the function of a transmitter or the function of a accept receiver.

A single data node DK with a data processing unit in Form of a microcontroller MC, a voltage regulator and a UR Interface IF is shown in block diagram moderately in FIG. 2, wherein the interface IF the one hand to the data bus 13 and on the other hand to the voltage supply line 15 is connected. The interface IF is the Microcontroller MC via an internal data DBInt in data connection. The microcontroller MC is UR of the voltage regulator supplied with operating voltage, when the interface IF a compound between the voltage supply line 15 and the voltage regulator UR releases. Such release causes a wakeup of the microcontroller MC in its active state, while the microcontroller MC otherwise is in low-power sleep state. On happened Such activating or waking the microcontroller MC either when an activation address filter means of the interface IF has recognized that with the address of a sent via the data bus 13 Bit sequence of the associated microcontroller activated or woken to be, or if the interface IF via an activation input WE an external alarm Wext supplied.

An embodiment of a Adressenfilter- and Bittaktrückgewinnungsteils an interface according to the invention in block diagram illustration shown in Fig. 3. A received via the data bus 13 bit sequence Rx is a hand on a Bittaktrückgewinnungseinrichtung BTR and on the other hand to an input of an address shift register ASR given. The address shift register ASR has a number of shift register stages on which the number of address bits of an over the Databus 13 messages sent frame is the same. As based on Fig. 5 will be explained in more detail, each message frame begins with an address bits presented Rahmenstartbit RSB, the is pushed out of the address shift register ASR again, when in ASR all address bits of each message frame . are The contents of the address shift register ASR is respectively compared with the content of an address filter AF, and the respective Comparison result with the aid of the contents of a mask register MR masking the already explained type subjected. A review found respectively by an AND operation using an AND gate AND instead, the output signal depending on whether the masked comparison of the received address bits with the Address filter AF stored address bits match or not, a first logic value, for example "0", and a second logic value, For example, "1", assumes.

The presentation of the AND gate AND as an output of the mask register MR downstream function block is shown in FIG. 3, only functionally specific. In practical circuits found in reality a link, for example, a multi-level link, the memory contents of the address shift register ASR, the contents of Address filter AF and the contents of the mask register MR instead, possibly with different or additional logic elements as the in FIG. 3 symbolically illustrated AND gate AND.

For details, can the previously mentioned two patent applications be removed.

By means of Bittaktrückgewinnungseinrichtung BTR is the bit timing of the recovered bit sequence of the received message frame, respectively. In order bit change can also be selected for the case that a plurality of Bits same logic or potential value in succession, between such adjacent bits thus no detectable edge change occur.

What the address identification or address detection of the interface relates, is in terms of Bittaktrückgewinnungseinrichtung BTR only of interest that this supplies the bit timing of the received bit sequence. Using this bit clock on the one hand the reading of address clocked in the address shift register ASR and on the other hand by means of a bit counter BZ, the number of already received bits of each message frame counted. If the bit counter BZ whose Counting process is triggered by a start signal of using generates Rahmenstartbits the message frame each received is a number counted bits equal to the Adressenbitzahl plus a Rahmenstartbit is, "white", the bit counter that in the address shift register ASR are all address bits and only the address bits need, and are at this time via its output an enable signal to an enable input FE of the AND gate AND, thus released its evaluation result only at the timing is, at what address in the shift register ASR all Address bits and only these are.

Appears to this release timing at the output of the AND gate AND logic one value, which indicates that the received address a particular consideration for the data nodes DK address is, is This potential value used as an internal alarm Wint to the associated microcontroller from idle state to the active state wake.

The internal alarm Wint but not directly as a wake-up signal Special passed through an OR gate OR with three inputs, where the internal alarm Wint, a Prioritätswecksignal Wprio or the external alarm Wext is supplied. Reaches one of these three Wake-up signals to the OR gate OR is at the output of OR a Alarm W generated, for activating the voltage regulator UR and thus leads to the activation of the microcontroller MC.

With the Prioritätswecksignal Wprio can be achieved that over a specific content of each received bit sequence all Data nodes DK be awakened in an active state. When in Fig. 3 is the embodiment illustrated Prioritätswecksignal Wprio created using the Bittaktrückgewinnungseinrichtung BTR. Further details are given below in connection with the Figures 4 and 5 explained.

A preferred embodiment of a Bittaktrückgewinnungseinrichtung BTR is shown in Fig. 4 in block diagram illustration. These comprises a differentiator DF, as the differentiating signal to the received bit stream Rx is supplied, for example in the form of in FIG. 5 bit sequence. created With each pulse edge of the bit string at the output of DF a negative or a positive differentiation pulse, of a count start / counter reset input S / R a Bitlängenzählers BLZ is given. The Bitlängenzähler BLZ is over an intermediate bus example in data exchange with a Bitlängenspeicher BLS. The Bitlängenzähler BLZ will be counted clock pulses CLKINT of a (not shown) of the interface IF oscillator of this Node data supplied. The oscillation frequency of this oscillator considerably higher than the bit clock of the transmitted via the data bus 13 Bit sequences Rx.

At a first output A1 of Bitlängenzählers BLZ is recovered Bit clock BitClk available and at a second output A2 from BLZ can optionally Prioritätswecksignal Wprio removed will.

A frame start detection device RSE receives via a first Input E1 of the recovered bit clock and via a second BitClk Input E2 the received bit stream Rx. With RSE may be Evaluating the respective Rahmenstartbits and the bit clocks of BitClk each received bit sequence of the beginning of a message frame be found. In determining a frame start is the Frame start detection device RSE via the outputs A3 and A4 each a frame start signal Start, which means at the beginning of a message frame the Bitlängenzähler BLZ reset and the Bitlängenspeicher BLS will be deleted. The signal is also used to start Reset the bit counter BZ of the address recognition apparatus shown in Fig. 3 used, the bit counter BZ with the beginning of received message frame resets.

With the aid of Fig. 5 is now the operation of the in Fig. 4 shown Bitrückgewinnungseinrichtung BTR explained.

According to the protocol of the conventional CAN data networks is the Data bus 13 between the message frame at a constant Logic value "1" and begins each message frame with a Rahmenstartbit RSB with the logic value "0". This protocol also writes before, that no more than a predetermined within a message frame Number, for example six, bits same logic value must be consecutive. If the frame start detection device RSE from about E2 supplied bit stream Rx and / or from their on E1 supplied recovered bit clock signal is seen that more than according to the records prescribed number of bits same logic value in succession, it is assumed that the data network between is or outside of message frames. If a later Logic level change occurs, namely the logic value "0" during the Rahmenstartbits RSB a now received message frame recognizes this is the start of frame detection device RSE as a frame start and causes at this time, resetting of a bank code, and Deleting BLS.

The Edge transition of the logic value "1" to logic "0", which to Beginning of Rahmenstartbits RSB occurs, also triggers a Zählstartimpuls at the output of the differentiator DF from which the Bitlängenzähler BLZ for counting the clock pulses supplied to it internal CLKINT starts. If, in the in Fig. 5 shown at the end of the bit sequence the RSB Rahmenstartbits a positive going signal transition occurs, this triggers the output of the differentiator DF a counting stop for the Bitlängenzähler BLZ from. At the same time storing the to be this time from Bitlängenzähler BLZ reached count in the Bitlängenspeicher BLS controlled the of this count for the rest keeps stored current message frame.

With the handover of the end reached by RSB count on the Bitlängenspeicher BLS is the Bitlängenzähler BLZ reset and started a new count. With each subsequent change of edge RX of Bitlängenzähler BLZ is reset again and started a new count. Because in a bit sequence of a message frame successive several bits same logic value can, as is for example shown in Fig. 5, is not at each Bitwechselstelle also an edge change available so that the Bitlängenzähler BLZ in the case of such successive same Logic values ​​would not be reset at the Bitwechselstelle. to also Bitwechselstellen the same between successive bits to detect logic value, the count of BLZ is constantly compared with the count value stored in BLS and BLZ is also then reset when a count after each counting start has reached which is equal to the count value stored in the BLS. consequently it comes to resets of BLZ whenever either Help the differentiator DF an edge change of the bit sequence Rx it has been found or if BLZ a count equal to the BLS stored count value has reached.

Each reset process of BLZ appears at the output A1 a Bittaktimpuls and the consequence of this bit clock pulses represents the recovered Bit clock BitClk represents.

With the help of the current comparison of the count value of BLZ with the in BLS stored count may thus Bitwechselstellen even are marked by the appearance of Bittaktimpulsen BitClk, if no edge change take place. In this way, not only Bitwechselstellen within the bit sequence of a currently received Message frame are marked, but the recovered Bit clocks may also be generated between the message frame, when the Bittaktrückgewinnungseinrichtung BTR configured and is controlled so that the memory content of the BLS also Bitlängenspeichers maintained after the end of a message frame remains and for cancellation only with the beginning of a Rahmenstartbits RSB subsequent message frame is done.

In the embodiment shown in Fig. 4, it is assumed, that the BLS Bitlängenspeicher this is even able to to recognize the beginning of a Rahmenstartbits. Another possibility would be, the BLS Bitlängenspeicher the differentiated signal at the output the differentiator DF evaluate permit.

The frame start detection device RSE can with a counter be constructed, which can refer both detect the edges of Rx (possibly with the aid of the output signals of the differentiator DF) and the other hand is reset with each of these edges and a Counting operation is started, in which he clock pulses of a predetermined Clock counts, for example, the recovered bit clock BitClk. If the respective count of RSE a count Indicates that the last edge change is older than according to the protocol within the bit sequence of a permissible message frame is allowed, it is assumed that a frame Pause or a frame space is present and that it is on it, at a following edge change at the beginning of a Rahmenstartbits RSB must act.

The following on Rahmenstartbit RSB bit is the first address bit of each message frame. If this first address bit, Unlike the example shown in Fig. 5, the same logic value "0" as the Rahmenstartbit RSB, is connected to the beginning of RSB triggered counting of Bitlängenzählers BLZ not end stopped by RSB, because at this time from the differentiator DF no differentiation pulse is delivered. This results in that the Bitlängenzähler BLZ its counting on the end of RSB addition continues and a takeover of the count in the Bitlängenspeicher BLS only occurs when a first edge change since the beginning of RSB occurs. The Bitlängenzähler BLZ therefore reaches a count, the - also taking into account the frequency of the inaccuracy internal count clock CLK supplied interface oscillator - well above the Count is who will be reached at the end of Rahmenstartbits RSB would. This type of behavior is targeted for the priority Awakening utilized. If data node is not determined by detecting for them Addresses are awakened but independent of a such address recognition, used by the data nodes of the other data nodes will wake address unspecific, just a to be sent data frame, in which the bit sequence on the Rahmenstartbit RSB with the logic value "0" a first address bit to the same logic value "0" follows. This results in the Bitlängenzählern Interfaces of all data nodes to achieve a count, which overlies the count value at the end of Rahmenstartbits RSB can be achieved. Now set to the Bitlängenzähler BLZ of Interface data of each node on a Prioritätsweckvorgang would be involved, in such a way that when reaching a predetermined Count value even considering a frequenzungenauen Interface oscillator certainly higher than the end of a Rahmenstartbits achievable count, the outcome A2 Prioritätswecksignal Wprio is discharged, you can all the Prioritätsweckverfahren Data nodes involved together continuously waking, that the sending data node trigger the Prioritätsweckvorgang want a data frame with a sequence of bits sent on whose Rahmenstartbit RSB follows with the logic value "0" a first address bit the same logic value "0".

In the usual case, each microcontroller MC a separate crystal oscillator on high frequency stability, with the control of the clock is microcontroller made. Since such crystal oscillators are relatively expensive, it would be beneficial, the timing of the respective Microcontroller does not depend on such an own quartz oscillator make it from the perspective of an external microcontroller make timing.

A circuit arrangement with which such a thing is possible in Fig. 6 is shown in block diagram illustration. This circuitry allows an interface oscillator excessive frequency accuracy a high frequency accuracy having a bit clock on the tune data received bit sequence. The output signal of the thus frequency exactly made interface oscillator can then as a clock control signal for the associated, not have its own oscillator having microcontrollers are used.

The circuit arrangement shown in Fig. 6 comprises a voltage controlled Oscillator VCO, the output of the clock signal MCCLK for the microcontroller MC of the affected data node DK supplies. For example, VCO generates a clock frequency of 10 MHz. This clock signal MCCLK is on a frequency divider FT with a given predetermined frequency dividing factor and at whose output is the internal clock CLKINT available. is a CLKINT where counting input of a frame length counter residual maturity, the reset input a RESET has, the start of frame signal from the start Frame start recognition means RES is supplied in Fig. 4, to the frame length counter residual maturity at the beginning of each new message frame reset. In addition, a frame length setpoint adjuster RLS is provided in which a count value corresponding to a predetermined Rahmensollänge is set. By means of a subtraction STE is the respective count value of the frame length counter RLZ continuously compared with the frame length setpoint. An off this comparison resulting difference is an ERROR as on given release dependent staging ZS and arrives at release of this on a summing circuit S. By means of summing S becomes a setting value of the desired frequency VCO leads when the current supplied by STE error is zero, the added to respective actual error and thus the frequency of VCO corrected.

Since the frame length counter RLZ only from Rahmenstartbit RSB is reset, that after a time period, the frame length on the goes beyond a bit counter BZ is provided, for which also in Fig. 3 existing bit counter BZ can be used by means of which a predetermined frame length corresponding to a predetermined Number of bits can be counted from the top frame. If the corresponding Number of bits or the frame length is reached, the latch is ZS released to the then existing ERROR to the Summing circuit S pass. If all message frames the same number of bits and thus the same frame length as may be adapted to the bit counter BZ that he for the enable signal the release dependent staging ZS respectively on actual Setting end supplies. For the case that the via the data bus 13 delivered message frames have different frame length can, the bit counter BZ is arranged such that it from the reset by Rahmenstartbit RSB a bit number and thus frame length is one which is at most as large as the smallest possible frame length all possible message frame.

The vote of the controlled oscillator operates as follows:

In the event that the VCO accurately delivers its nominal frequency, fits in with Help the bit counter BZ defined frame length or in the means of BZ defined review period (if shorter than an actual Frame length) a certain number of clock pulses CLKINT. This particular number of clock pulses corresponding to a certain level Count of the frame length counter residual maturity at the end of Frame length or the assessment period. Under length setpoint adjuster RLS is exactly this count corresponding setpoint stored. Has VCO's nominal frequency, is determined by means of STE Error is zero and is solely by the VCO Manipulated value controlled. Soft the frequency of the VCO of the frequency setpoint from, is within the frame length or the assessment period by residual maturity reached another count when he is placed in RLS. This then leads to a corresponding ERROR and to a corresponding Deviation of the given to the control input of VCO control signal the manipulated value. This leads to a corresponding change in supplied by the VCO frequency and hence of the micro-controller MC delivered microcontroller clock MCCLK.

Even though not all the microcontrollers of the entire data network ever require a separate crystal oscillator, must surely at any point the overall system, a crystal oscillator with high frequency accuracy be present, the frequency and hence the clock rate for the entire Rest of the data system dictates. For this purpose, a data node provided as a clock master and its microcontroller with a crystal oscillator are provided. Preferably, the clock master will awakened by any alarm in the entire data network and then reacts with the (preferably several times) sending a predetermined Taktdefinitionsbitfolge on the data bus 13. The Rahmenstartbit this Taktdefinitionsbitfolge brings the interfaces of all Data nodes active in the Mitlesezustand in which their address filter are. The Taktdefinitionsbitfolge is now designed in such a way that their a higher priority has played as the messages from all other Data nodes can be supplied as the clock master. Thereby it is ensured that from the transmission of a Taktdefinitionsbitfolge the clock master interfaces of all other data nodes feel concerned and in all these interfaces frequency synchronization takes place, as has been explained with reference to Fig. 6. The microcontroller of the data nodes need for this frequency control not to be woken up.

To synchronize the interface oscillators VCO all these ensure data node with the clock of the clock master, the Data network preferably organized such that during the transmission the Taktdefinitionsbitfolgen will not transfer messages. Also can be obtained by appropriate design of Taktdefinitionsbitfolge and clock synchronization circuits in the individual data nodes reach that clock synchronization circuits, for example, in Fig. 6 Art, respond only to Taktdefinitionsbitfolgen not However on Nachrichtenbitfolgen.

The frequency divider FT in Fig. 6 ensures that the maximum Count value for the frame length counter RLZ must be designed does not need to be too high and therefore one with a smaller, less Counting stages containing counters can survive.