Multiplane memory architecture

The invention relates to a multilevel hierarchy memory architecture constructed from memory cells.

Future microelectronic circuits will become complicated systems with transistor numbers in the region of 10¹² until 10¹⁵ realize. These systems, such as parallel processor systems, artificial intelligence systems, or multimedia systems, will typically include multiple cooperating subsystems for processing data. A crucial problem for the efficient practical realization of these future systems will therefore be the storage of the data to be processed as well as of the data processing programs. The most powerful systems will certainly be realized if there is a memory that the subsystems can access in parallel and with high bandwidth. Such memories, which have a plurality of ports as external connections, which external modules can access in parallel in time, are generally referred to as multi-port memories.

A particularly important boundary condition for economic reasons is, of course, the lowest possible outlay on the chip. Further boundary conditions result from the demand for the lowest possible access time to the memory cells or the ports and the lowest possible power loss of the entire memory system.

From LA Glasser &amp; DW Dobberpohl, <img file="EP0908893A2_D0001.tif" />The Design and Analysis of VLSI Circuits, "Addison-Wesley, ISBN 0-201-12580-3, pages 388-390, such a multi-port memory is given. This document shows a multi-port memory that implements the desired number of external ports in each individual memory cell. Each individual memory cell therefore occupies a large amount of chip area. In addition, there is a significant decoding overhead for each port added, so that the entire multi-port memory is ultimately extremely space consuming. This simplest realization of a multi-port memory is thus also the most surface-poor and thus the most expensive solution.

From K. Guttag, RJ Gove, JR Van Aken, <img file="EP0908893A2_D0002.tif" />A Single Chip Multiprocessor for Multimedia: The MVP, IEEE Computer Graphics &amp; App., Vol. 12, 1992, pages 53-64, another multi-port memory is known. The above-described problem is solved here by a so-called crossbar distributor, on whose input side the desired external ports are located, and on whose output side several conventional memory blocks with 1-port memory cells are connected. Although this approach comes advantageously with 1-port memory cells, but the crossbar distributor, which is often referred to as a switching network, in practice also requires a lot of chip area and generated because of the long wiring lines high power dissipation. Since not very many memory blocks can be connected, the number of unsuccessful accesses, that is, when more than one port is accessing a particular memory block at the same time, is relatively high.

The use of hierarchical memory architecture is known for other purposes in the literature. The most important of these tasks so far has been to shorten the effective access time over a single, conventional external port. Shortening the effective access time is especially important in the basically slow dynamic memories (DRAMs), so as not to cause too much of a difference in the clock rates of today's standard microprocessors. The access time for a memory arrangement essentially results from the transit time of the data signals on the word line and from the transhipment of the memory capacities. The hierarchical arrangement attempts to shorten the effective length of the tracks in order to correspondingly reduce the access time.

A memory arrangement which operates according to the banking technique is to a certain extent such a hierarchically structured memory. The banking technique exploits the fact that data transport over a data bus is much faster than memory access. It is therefore possible, in principle, to read out data from several memory blocks in parallel, to buffer them in fast registers and to output them externally at high speed via a data bus. However, for the banking technique, it is very important that the sequentially requested data is likely to be in different blocks. If this is not the case, access requests must be rejected. The essential part of banking is therefore the detailed algorithm for the distribution of the stored data to the individual memory blocks. In practice, the memory block number in banking is limited to a relatively small number of memory blocks, usually 32 memory blocks. In addition, the access times to the individual memory blocks are slow here.

A memory architecture which also utilizes a memory hierarchy is known from EP 0 393 434 B1. Here, a memory constructed in multilevel hierarchy is indicated having a single conventional external port. The fact is exploited that the signal propagation time in the critical conduction path can be shortened in a subdivision of the memory into a plurality of hierarchy levels. However, the burden of parts of the critical path should be avoided here by the hierarchical memory division. Due to the extremely high parasitic capacitances and resistances in the word line and bit line sections, otherwise there would be long signal change times and thus large access times to the external port.

With regard to further details, features, their advantages and mode of operation of hierarchically structured 1-port memory architectures, reference is expressly made to European Patent EP 0 393 434 B1 and incorporated by reference (US Pat.<img file="EP0908893A2_D0003.tif" />incorporated by reference ").

Based on this prior art, the invention is therefore an object of the invention to provide a memory architecture with multi-level hierarchy, which has a plurality of external ports.

According to the invention, this object is achieved by a memory architecture<ul id="ul0001" list-style="dash" compact="compact"><li>with a plurality of hierarchy levels,</li><li>with at least one memory block in each of the hierarchical levels, wherein the memory blocks in the lowest hierarchical level each consist of individual memory cells, each next higher hierarchical level containing memory blocks, which are respectively composed of memory blocks from the next lower hierarchical level,</li><li>with decoder devices in each of the hierarchical levels, for driving, reading and writing the respective memory blocks,</li><li>with at least one I / O interface, which has a plurality of I / O ports, wherein the I / O ports can be controlled in parallel simultaneously and independently of one another, and</li><li>with at least one address selection circuit and at least one port selection buffer circuit in at least one of the hierarchical levels.</li></ul>

The multilevel hierarchy memory architecture according to the invention thus has a multiplicity of external connection ports which can be simultaneously driven in parallel.

Each of these hierarchical levels has a plurality of different memory blocks. The memory blocks in the lowest hierarchical level consist of a plurality of memory cells. It would also be conceivable that the lowest hierarchical level consists of only a single memory cell. Usually, the use of two levels of hierarchy is quite sufficient for most requirements. However, then the memory block in the lowest hierarchical level should consist of at least a plurality of memory cells.

The multi-port memory architecture according to the invention advantageously makes it possible to use 1-port memory cells in the lowest hierarchical level. Of course, it would also be conceivable to use 2-port or multi-port memory cells. However, the use of 1-port memory cells proves to be particularly advantageous for reasons of area optimization, in particular because of the electrical tracks (word lines and bit lines). On the basis of SRAM design data, the use of multi-port memory cells can be increased by approx. 30 % at two ports up to approx. 70 % at 16 ports. The use of such static 1-port memory cells (SRAM memory cells) thus proves to be particularly cost-effective.

The arrangement of the memory blocks in the various hierarchical levels can be designed differently. It is particularly advantageous if the memory blocks of a hierarchical level are arranged in a matrix. It is particularly advantageous if the number of columns and rows of the memory block matrix is ​​a multiple of two.

However, it is also conceivable that the memory blocks are arranged in the hierarchical levels in a switching network arrangement, in banking technology or the like. The arrangement of the various memory blocks within the various hierarchical levels is left to the freedom of system design. It would also be conceivable if a different arrangement of the memory blocks is used in each of the different hierarchy levels.

In addition to the application in system integration, the invention can of course be used for space-favorable multi-port memory chips. It is not limited to any particular type of memory but is applicable to all types of nonvolatile, static and dynamic memory and the underlying memory technology. The invention is particularly advantageous in the case of static memories (SRAMs) and dynamic memories (DRAMs). However, the invention is particularly advantageous in logic memories, for example in all types of programmable read only memories (PROMs, EPROMs, EEPROMs). In addition, the memory architecture according to the invention also makes sense in conventional ROM memories. ROM memories are preferred in processor devices, and an application of the hierarchical architecture is particularly attractive here for reasons of space.

It would also be conceivable if different technologies were used at different levels. For example, for the so-called<img file="EP0908893A2_D0004.tif" />The memory architecture used is thus largely independent of the technology used.The invention is particularly advantageous in dynamic memory arrangements (DRAM), since in this case the capacities of the memory cells are lower due to the lower memory effective cable lengths can be dimensioned relatively small.

Despite the arrangement of the memory in several hierarchical levels, the access time per port does not deteriorate. The effect of an opposite development occurs here. Due to additional gates, such as an additional multiplexer, the access time is degraded by the additional runtime. However, the dimensions of the individual memory blocks and thus also of their printed conductors are made smaller, which in turn means a reduction of the access time. Moreover, access time is further improved due to the reduced parasitic capacitances and resistances in the critical conduction path.

The fact that only one memory block on the upper hierarchy levels is activated per port and per access, and the remaining unused memory blocks are effectively shut down, results in a lower power loss of the entire memory architecture. The remaining, unused memory blocks are thus virtually switched off.

In addition, prior art multi-port memory architectures are limited in design by the so-called raster circuits consisting essentially of the row and column decoder circuits. Especially with very many port ports, the control lines of the decoder circuits with the drivers contained therein can no longer lead to the corresponding memory cells. The number of port ports of such multi-port memory architectures is thus limited by design. By means of the invention, it is advantageously possible to adapt the design of the multi-port memory architecture to the given space requirements. The various raster circuits can be distributed over several hierarchy levels. In addition, the connection ports of the multi-port memory architecture can be distributed to the various hierarchy levels. Thus, the given multilevel hierarchy allows for any design freedom.

The further subclaims are directed to preferred embodiments and further developments of the memory.

The invention will be explained in more detail with reference to the embodiments specified in the figures of the drawing. It shows:<dl id="dl0001"><dt>FIG. 1</dt><dd>a static 1-port memory cell (a) in comparison with a static multi-port memory cell (b);</dd><dt>FIG. 2</dt><dd>an example of a multilevel memory architecture according to the invention with multi-level hierarchy.</dd></dl>

Figure 1 shows a static 1-port memory cell (a) in comparison with a static multi-port memory cell (b), which has two connection ports in the present example.

The 1-port memory cell in FIG. 1 (a) has two selection transistors AT1, AT2 and two inverters I1, I2. The first selection transistor AT1 is in this case connected between a data line B1 for reading in / reading out information and an input of the first inverter I1, wherein the second inverter I2 is fed back in parallel to the inverter I1. The second selection transistor AT2 of the memory cell is connected between an output of the first inverter I1 and a data line B<maths id="math0001"><math display="inline"><mrow><mover accent="true"><mrow><mtext>1</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0005.tif" /></maths> switched, wherein the second data line B<maths id="math0002"><math display="inline"><mrow><mover accent="true"><mrow><mtext>1</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0006.tif" /></maths>which has signals inverted to the first data line B1. The control terminals of the selection transistors AT1, AT2 are additionally connected to a word line WL1. Via the word lines WL1, the selection transistors AT1, AT2 can be controlled in the conductive state or in the blocked state.

FIG. 1 (b) shows a multi-port memory cell which has two ports in the present example. This so-called 2-port memory cell is constructed similarly to the 1-port memory line of FIG. 1 (a). The 2-port memory cell additionally has two further selection transistors AT3, AT4 which, like the selection transistors AT1, AT2, are coupled to the two inverters I1, I2 of the memory cell. Furthermore, the 2-port memory cell in FIG. 1 (b) has a second word line WL2 and two further data lines B2, B<maths id="math0003"><math display="inline"><mrow><mover accent="true"><mrow><mtext>2</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0007.tif" /></maths> on. The word line WL2 and the data lines B2, B<maths id="math0004"><math display="inline"><mrow><mover accent="true"><mrow><mtext>2</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0008.tif" /></maths> are connected as in Figure 1 (a) with the respective selection transistors AT3, AT4.

The lines WL1, B1, B form<maths id="math0005"><math display="inline"><mrow><mover accent="true"><mrow><mtext>1</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0009.tif" /></maths> the first port of the memory cell and the lines WL2, B2, B<maths id="math0006"><math display="inline"><mrow><mover accent="true"><mrow><mtext>2</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0010.tif" /></maths> the second port of the memory cell. Multi-port memory cells with a corresponding number of output ports are then provided starting from the memory cell in Figure 1 with a corresponding number of selection transistors or lines. As the number of ports of a memory cell increases, so does the wiring complexity as mentioned above. Starting from the area overhead, the 1-port memory cell is thus the most space-favorable form.

The inventive memory architecture uses an in-memory 2-level hierarchy to accomplish the transition of a single port implemented in each memory cell to the external ports of the multi-port memory. The principle of this multilevel multi-port memory architecture according to the invention is shown in FIG. In this example, two hierarchical levels and a number N output ports are shown.

The multi-level hierarchy memory architecture of the present invention has two hierarchical levels H1, H2 in the present example. It would also be conceivable to use more than two hierarchical levels for realizing the memory architecture according to the invention. In this case, the first hierarchical level is designated H1, while the second hierarchical level is designated H2. Furthermore, the elements of the first hierarchical level H1 are subsequently provided with the index 1, while the elements of the second hierarchical level H2 are provided with the index 2.

For the sake of clarity, the wiring lines, in particular the word lines and bit lines, have not been drawn in all hierarchy levels H1, H2.

In the present exemplary embodiment, both hierarchy levels H1, H2 are constructed equivalently and each contain a memory block matrix and selection means for specific readout of individual memory blocks, which in the present example are designed as row decoders and column decoders, as well as an interface to the next higher hierarchical level.

It is of course also conceivable that the memory blocks are arranged in different hierarchical levels in different ways. Thus, for example, it would be conceivable that the memory blocks are arranged in one of the hierarchical levels in a switching network arrangement, while the memory blocks are arranged in a different hierarchical level, for example in a known memory block matrix. It is thus not absolutely necessary for the different hierarchical levels H1, H2 to be arranged in a similar way to one another. The arrangement of the memory blocks in the respective hierarchy levels can thus be applied to the application or be adapted to the requirements of the user and is thus another degree of freedom in the design of the memory architecture.

The first hierarchical level H1 contains a first memory block matrix SBM1. Furthermore, the first hierarchical level H1 includes a word line decoder WLD, a bit line decoder BLD, a port selection buffer circuit PAP, and an address selection circuit AAS.

The memory block matrix SBM1 of the first hierarchical level H1 comprises a number in the present example <maths id="math0007"><math display="inline"><mrow><msup><mrow><mtext>M1 = 2</mtext></mrow><mrow><mtext>m1</mtext></mrow></msup></mrow></math><img file="EP0908893A2_D0011.tif" /></maths> different memory blocks SB1, which are arranged in a matrix. In the present example, the memory block matrix SBM1 comprises a number 2^m1-r1 Columns and a number 2^r1 Lines. The number of rows and columns of the memory block matrix SBM1 is thus a multiple of 2. Although this is not absolutely necessary, it is advantageous in the case of such a memory block matrix.

The memory blocks SB1 of the first hierarchical level H1 consist of different memory cells. In the present example, the memory cells in the first hierarchical level are 1-port memory cells with a single read / write port. It would of course also be conceivable that the said memory cells are so-called multi-port memory cells with a corresponding number of read / write ports. However, from the statements made in the introduction to the description and in connection with FIG. 1, the use of 1-port memory cells in the lowest hierarchical level H1 is particularly advantageous. However, the use of such multi-port memory cells in the lowest hierarchical level H1 may be favorable for certain requirements, such as access time and area optimization of a design. In particular, it may be advantageous to reduce the conflict probability of access for a small number of memory blocks on one of the higher hierarchical levels.

The memory cells in the first hierarchical level H1 can be designed as any nonvolatile memory cells (eg EEPROM memory cells), static memory cells (eg SRAM memory cells) or dynamic memory cells (eg DRAM memory cells). Of course, the peripheral circuits of the memory blocks must be designed to match the selected type of memory cells.

To select a single or of a plurality of memory cells in the lowest hierarchical level H1, a bit line decoder BLD and a word line decoder WLD are provided. In the present example, the bitline decoder BLD has a number of m1-r1 address bits and the wordline decoder WLD has a number of r1 address bits. Furthermore, the first hierarchical level H1 has an address selection circuit AAS, which is controlled by a number N of different addresses A11 to AN1. Each of these addresses has a width of m1 address bits.

Furthermore, the first hierarchical level H1 has a port selection buffer circuit PAP with a number N of different output ports D1 to DN.

The operation of the memory array in the first hierarchical level H1 takes place in a read-out process as follows: An address word is coupled in by the address selection circuit AAS via the address ports A11 to AN1. Starting from this coupled address word, the word line decoder WLD and bit line decoder BLD drives the respective memory cells in the memory block matrix SBM1 such that a data word can be read out. This data word is supplied to the port selection buffer circuit PAP. The port selection buffer circuit PAP assigns this data word to one of the output ports D1 to DN. For a write operation, this cycle is equivalent in the opposite direction.

Furthermore, the memory architecture according to FIG. 2 has a second hierarchical level H2. The second hierarchical level H2 comprises a second memory block matrix SBM2, a row selection generator RAG, a column selection generator SAG and an input / output buffer circuit IOP. In the second hierarchical level H2, the memory blocks SB2 in the present example are likewise designed as a memory block matrix SBM2.

The structure of the second memory block matrix SBM2 in the second hierarchical level H2 is equivalent to that in the first hierarchical level H1. Of course, another arrangement of the memory blocks, for example a switching network or memory blocks arranged in so-called banking technology, is also conceivable here. In the present example, the memory block matrix SBM2 has a number 2^m2-r2 different columns and a number 2^r2 different lines. Equivalent to the first memory block matrix SBM1 in the second memory block matrix SBM2, the number of rows or columns is a multiple of 2, whereby a common other number of columns and rows would be conceivable.

Furthermore, the second hierarchical level H2 has a row selection generator RAG for selecting the different rows and a column selection generator SAG for selecting the different columns of the second memory block matrix SBM2. The row selection generator RAG thus has N different ports, each with r2 different address bits. The column selection generator SAG also has N different ports, each with m2-r2 address bits.

The selection of the memory blocks SB2 in the second hierarchical level H2 via the so-called input / output buffer circuit IOP (I / O buffer circuit). The I / O buffer circuit IOP also has a number N of different output ports D1 to DN. The output ports thus represent the output ports of the multi-port memory architecture.

Of course, it would also be possible for one or more hierarchy levels H1, H2 to consist of only one memory block. In the case of the lowest hierarchical level H1, the memory block matrix SBM1 would then be reduced to a single memory block SB1 and thus to a single memory cell.

According to the invention, the memory blocks SB2 in the second hierarchical level H2 are each composed of memory blocks SB1 and the respective peripheral units of the first hierarchical level H1.

If the memory architecture is constructed from a plurality of hierarchical levels, then the structure of the memory results as follows: In the lowest hierarchical level H1, the memory blocks SB1 are composed of a number of at least one memory cell. The associated peripheral units, such as word line decoder WLD, bit line decoder BLD, port selection buffer circuit PAP, address selection circuit AAS are adapted to the respective arrangement of the memory blocks in the respective hierarchical level. Each next higher hierarchical level is then composed of memory blocks of the next lower hierarchical level. The uppermost hierarchical level then additionally has an I / O buffer circuit IOP with the corresponding output ports of the memory architecture. The number N of the different output ports D1 to DN are then the ports of the multi-port memory architecture.

The second hierarchy level H2 thus consists of a number <maths id="math0008"><math display="inline"><mrow><msup><mrow><mtext>M2 = 2</mtext></mrow><mrow><mtext>m2</mtext></mrow></msup></mrow></math><img file="EP0908893A2_D0012.tif" /></maths> different memory blocks SB2 together, each individual memory block SB2 a number <maths id="math0009"><math display="inline"><mrow><msup><mrow><mtext>M1 = 2</mtext></mrow><mrow><mtext>m1</mtext></mrow></msup></mrow></math><img file="EP0908893A2_D0013.tif" /></maths> contains different memory cells. The total number of memory cells of the memory architecture is thus calculated<maths id="math0010"><math display="inline"><mrow><msup><mrow><mtext>M = M1 * M2 = 2</mtext></mrow><mrow><mtext>m</mtext></mrow></msup></mrow></math><img file="EP0908893A2_D0014.tif" /></maths>, in which <maths id="math0011"><math display="inline"><mrow><mtext>m = m1 + m2</mtext></mrow></math><img file="EP0908893A2_D0015.tif" /></maths> is.

Furthermore, according to the invention, a circuit arrangement for handling access conflicts is provided in hierarchy level H2 according to the invention. This so-called access conflict evaluation circuit is absolutely necessary, in particular in the case of a multi-port memory architecture, if, for example, two or more ports access the same memory block.

In this case, a prioritization of the access selection must take place. The access conflict evaluation circuit ZKAS is necessary in all conventional N-port memory architectures and thus also in a single N-port memory cell, since the access of two or more ports to the same memory cell is at least not allowed for write access and constitutes a conflict.

The functions of the most important subcircuits are explained in more detail below. First, the function of the N-port memory architecture during access via the N-ports will be briefly described. For most circuits used in architecture there are well-known and used prior art solutions.

The row select generator RAG and column select generator SAG generate row and column select signals for each of the N ports from the respective m2 address bits of the second hierarchical level H2. In parallel, the access conflict evaluation circuit ZKAS checks the address bits of the second hierarchical level H2 for one or more conflict situations. The activation of the corresponding memory block SB2 is only released when the access conflict check is completed and if, in the case of access conflicts cases, a port is selected as access-authorized according to a given prioritization algorithm. Thus, only one memory block SB2 per port are activated on the second hierarchical level H2.

In N-port memory architectures, such as an N-port memory cell, an access conflict has so far been solved sequentially. This sequential access conflict solution, however, proves disadvantageous in an N-port memory architecture, since the performance of the entire memory architecture is dramatically reduced, especially in the case of multiple access conflicts.

For this reason, it is advantageous if access conflicts are processed completely in parallel over time. Such a parallel processing of access conflicts can, for example, take place via a prioritization algorithm, which in each case selects a port as authorized to access. For the prioritization algorithm, for example, a simple staggering of the ports can take place according to their meaning. In case of conflict, the most important port always gets the access right. A status signal indicates externally for each port whether the current access was successful or rejected.

In the first hierarchical level H1, only the m1 address bits of a single port are supplied to the word line decoder WLD and bit line decoder BLD. The activation signals of the memory blocks SB1 thus contain only the information about the port to be activated. This information is used by the address selection circuit AAS to switch the address bits of the associated port to the corresponding decoder. The port selection buffer circuit PAP then simultaneously connects the output of the bit line decoder BLD to the data lines associated with the port. In addition, the bit line decoder BLD comprises an integrated evaluation circuit and driver means for amplifying the read signals.

The three circuits, port selection buffer circuit PAP, address selection circuit AAS and access conflict evaluation circuit ZKAS, can be implemented according to known methods in conventional circuit technology. The first two circuits, that is, the port selection buffer circuit PAP and the address selection circuit AAS, are simple multiplexer and demultiplexer circuits, respectively.

The access conflict evaluation circuit ZKAS of course depends on the underlying prioritization algorithm. In particular, in the case of a completely parallel access conflict solution, the circuit can be made here on the basis of a comparison of the address bits via an EXOR gate. The underlying prioritization algorithm then determines how the outputs of the EXOR gate are linked to generate the corresponding port enable signals.

In FIG. 2, a word width of one bit per port has been assumed for the sake of simplicity. Of course, the word width within the proposed memory architecture may take on any value. The training then takes place according to the methods of the prior art.

In a further development, it is of course possible to use all known prior art techniques for shortening the access time in order to develop the multilevel memory architecture according to the invention with a multilevel hierarchy. In FIG. 2, however, the simplest, hierarchical arrangement for memory blocks in different hierarchical levels is indicated. In addition, one of the known techniques for shortening the access time, for example caching, banking, etc., can additionally also be used internally in each of these hierarchical levels. be used.

LIST OF REFERENCE NUMBERS

A11, ..., AN1,   A12, ..., AN2 = address lines AAS = address selection circuit AT1, AT2, AT3, AT4 = selection transistors B1, B2 = data lines B<maths id="math0012"><math display="inline"><mrow><mover accent="true"><mrow><mtext>1</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0016.tif" /></maths>, B<maths id="math0013"><math display="inline"><mrow><mover accent="true"><mrow><mtext>2</mtext></mrow><mo>¯</mo></mover></mrow></math><img file="EP0908893A2_D0017.tif" /></maths>  = Data lines with inverse signals BLD = bit line decoder D1, ..., DN = output ports H1 = first (lowest) hierarchical level H2 = second (highest) hierarchical level I1, I2 = inverter IOP = I / O buffer circuit M = total number of memory blocks or Memory cells of the memory architecture m1, m2 = number of address bits M1, M2 = total number of memory blocks of a hierarchy level N = number of ports PAP = port selection buffer circuit R1, R2 = address bits RAG = row selection generator SAG = column selection generator SB1, SB2 = memory blocks W1, W2 = word lines WLD = word line decoder ZKAS = access conflict evaluation circuit