Hybrid programmable gate arrays

<u>Field of the Invention</u>

0001The present invention relates to integrated circuits, and, in particular, to programmable gate arrays and application-specific integrated circuits.

<u>Description of the Related Art</u>

0002Programmable gate arrays constitute one family of integrated circuits. There are different types of programmable gate arrays. A mask-programmable gate array (MPGA) (also known as a factory-programmable gate array) is a type of mask-programmed integrated circuit that is programmed one time and typically by the manufacturer of the gate array. Other types of mask-programmed devices (MPDs) include full-custom devices and standard-cell devices. A field-programmable gate array (FPGA), on the other hand, is a type of gate-array integrated circuit that can be programmed by the user. An FPGA can be one-time programmable or re-programmable, in which case the user can re-program the gate array one or more times.

0003Fig. 1 shows a schematic diagram of a conventional FPGA <b>100</b>, having an array <b>102</b> of programmable logic cells (PLCs) surrounded by a ring <b>104</b> of programmable input/output (I/O) cells (PICs) and an outermost ring <b>106</b> of pads. The PLCs and PICs can be programmed (and possibly reprogrammed) in the field to implement a desired set of functions. This programming is typically done through the configuration interface of the FPGA, which reads a stream of bits and writes to the internal configuration storage (SRAM, EEPROM, anti-fuse, etc.), which in turn controls the programmable logic and routing. The PICs operate as the interfaces between the array of PLCs and individual pads, which provide connections to the "outside world," that is, circuitry external to the FPGA. Programmable general routing resources (not shown in Fig. 1) are used to implement specific connections between PLC array <b>102</b> and PIC ring <b>104</b> (i.e., PLC-PIC connections) as well as specific connections within PLC array <b>102</b> (i.e., PLC-PLC connections) and within PIC ring <b>104</b> (i.e., PIC-PIC connections).

0004Fig. 2 shows a detail of a portion of FPGA <b>100</b> of Fig. 1. According to one conventional design, each PIC in ring <b>104</b> is associated with four pads and has four corresponding sets of pad logic. Fig. 2 shows a schematic diagram of the circuitry of FPGA <b>100</b> that is associated with one of these sets of pad logic. PLC logic <b>202</b> and PLC local routing <b>204</b> are part of PLC array <b>102</b> of Fig. 1. Similarly, PIC local routing <b>208</b> and PIC logic <b>210</b> are part of PIC ring <b>104</b> of Fig. 1, while pad <b>212</b> is one of the pads of pad ring <b>106</b> of Fig. 1. General routing resources <b>206</b> correspond to the programmable routing and logic used to connect individual sets of PLC logic to individual sets of PIC logic. PIC logic <b>210</b> comprises an output buffer <b>216</b> and an input buffer <b>218</b>, as well as boundary scan and other miscellaneous PIC logic <b>214</b>, such as optional flip-flops and latches.

0005Fig. 3 shows a schematic diagram of one of the three main types of mask-programmed devices -- a conventional MPGA <b>300</b>, having an array of gates <b>302</b> surrounded by a ring of pads <b>306</b>. Typically, the array of gates and the ring of pads are interconnected with each other by conductive (typically metal) wires to implement a desired set of functions. The ring of pads serves the same purpose of interfacing to the "outside world" as the ring of pads in FPGA <b>100</b> of Fig. 1. In a typical MPGA, the array of gates and the array of pads are pre-defined and the user can only define how they are interconnected at the factory. The other two main types of MPDs are standard-cell devices, which have rows of standard cells instead of an array of gates, and full-custom devices, which have individual transistors instead of an array of gates. These two types of devices also differ from MPGAs in that the rows of standard cells and the arrays of transistors are not pre-fixed, thus allowing increased functionality.

0006An FPGA, such as FPGA <b>100</b> of Fig. 1, has the flexibility to implement many different logic functions using the same silicon, although the cost of this flexibility is in chip layout area, performance (i.e., speed and power dissipation), and dollar cost. An MPGA could be designed to implement the same piece of logic with less area and optimal performance, translating into a lower dollar cost. The cost of using an MPGA, however, is that, once it is manufactured, the logic function cannot be changed by the user.

0007The present invention is directed to a scheme for exploiting both the programming flexibility advantages of FPGAs and the size, speed, functionality, and dollar cost advantages of MPDs.

<u>Summary of the Invention</u>

0008In general, the present invention is directed to a single hybrid integrated circuit (IC) having one or more regions of MPD-type logic for implementing permanent functions and one or more regions of FPGA-type logic for implementing user-specified functions. The FPGA-type logic provides programming flexibility, while the MPD-type logic provides size, speed, functionality, and dollar cost advantages. In one embodiment, a hybrid IC has an array of programmable logic cells (PLCs) implemented using FPGA-type logic, an application-specific block (ASB) implemented using MPD-type logic, and a ring of pads. Fast interface switch hierarchy (FISH) cells provide the interface between the PLC array and the ASB. Muxes in the FISH cells can be programmed to cause the FISH cells to operate either (1) as programmable interface cells (PICs) that provide a direct interface between the PLC array and the pad ring or (2) as ASB-interface cells (AICs) that provide interfaces between the PLC array and the ASB.

0009Another aspect of the invention is the ability to program the FPGA portion of the hybrid device separate from the ASB portion. The invention also includes the ability to modify the logic functionality in the ASB portion by setting options in the FPGA portion.

<u>Brief Description of the Drawings</u>

0010Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which: <ul id="ul0001" list-style="none" compact="compact"><li>Fig. 1 shows a schematic diagram of a conventional FPGA;</li><li>Fig. 2 shows a detail of a portion of the conventional FPGA of Fig. 1 ;</li><li>Fig. 3 shows a schematic diagram of a conventional MPGA;</li><li>Fig. 4 shows a schematic diagram of a hybrid integrated circuit, according to one embodiment of the present invention; and</li><li>Fig. 5 shows a schematic diagram of the circuitry of the hybrid IC of Fig. 4 that is associated with one set of FISH-cell logic, according to one embodiment of the present invention.</li></ul>

<u>Detailed Description</u>

0011Depending on the type or types of applications for which a conventional FPGA is to be used, there may be certain functions that many users will want to program into their FPGAs. Such functions may include anything that, in the past, has been placed in an MPD. According to the present invention, this permanent functionality can be implemented in MPD-type logic, while other user-specified functionality is implemented in FPGA-type logic, all on the same chip.

0012The present invention is directed to hybrid circuitry that combines one or more regions of FPGA-type logic with one or more regions of MPD-type logic on a single integrated circuit (IC) chip. By combining both FPGA- and MPD-type logic on one die, the advantages of both may be reaped. A specific logic function that requires high performance and/or needs to be very dense and/or is not possible in an FPGA (e.g., implementing an analog circuit with critical characteristics) can be implemented in MPD-type logic on a die with FPGA-type logic around it. The invention permits changes to functionality, when needed, yet provides improved performance and smaller device size over conventional FPGAs.

0013In particular, the regions of MPD-type logic may be pre-programmed in the factory to implement functions that, with conventional FPGAs, would be programmed in the field. The regions of FPGA-type logic are then left for the user to program in the field. In this way, a hybrid IC of the present invention combines the programming flexibility of FPGA-type logic with the size and speed advantages of MPD-type logic. As a result, the hybrid IC can have faster speed, smaller area, and lower dollar cost than conventional FPGAs which have only FPGA-type logic, without losing the flexibility of field programming that give FPGAs an advantage over conventional MPDs. This allows applications to be split into two categories of functions: permanent functions and user-specified functions. According to the present invention, permanent functions can be implemented in MPD-type logic for fast speed, small area, and low power usage, while the user-specified functions are implemented in FPGA-type logic.

0014Fig. 4 shows a schematic diagram of a hybrid integrated circuit <b>400</b>, according to one embodiment of the present invention. Similar to conventional FPGA <b>100</b> of Fig. 1, hybrid IC <b>400</b> comprises an array <b>402</b> of programmable logic cells surrounded on three sides by a ring of programmable I/O cells <b>404</b> and an outermost ring of pads <b>406.</b> On its fourth side, however, PLC array <b>402</b> is bounded by sets of FPGA-ASB interface hardware <b>412</b> that allow PLC array <b>402</b> to interface with an application specific block (ASB) <b>408</b>, which is implemented using MPD-type logic. For purposes of this specification, each set of FPGA-ASB interface hardware is referred to as an ASB-interface cell (AIC).

0015In a preferred embodiment, the PICs and AICs are implemented using the same generic set of field-programmable logic and routing circuitry, which is programmed to function as either a PIC or an AIC. For purposes of this specification, this generic set of programmable logic and routing circuitry is referred to as a fast interface switch hierarchy (FISH) cell. Each FISH cell is preferably programmed in the factory to function either (1) as a PIC that forms an interface between PLC array <b>402</b> and the corresponding pads <b>406</b> or (2) as an AIC that forms interfaces between PLC array <b>402</b> and ASB <b>408</b>.

0016A FISH cell can be programmed in the factory or in the field to function as a PIC or as an AIC. Even when programmed in the factory, there are other aspects of a programmed FISH cell that are still field programmable. That is, when factory-programmed to function as a PIC, a FISH cell has the same field programmability of a conventional PIC, such as those used in conventional FPGA <b>100</b> of Fig. 1. Similarly, when factory-programmed to function as an AIC, a FISH cell has other field programmable aspects.

0017Fig. 5 shows a schematic diagram of the circuitry of hybrid IC <b>400</b> of Fig. 4 that is associated with one set of FISH-cell logic, when operating as an AIC, according to one embodiment of the present invention. PLC logic <b>502</b> and PLC local routing <b>504</b> are part of PLC array <b>402</b> of Fig. 4. General routing resources <b>506</b> correspond to the programmable routing and logic used to connect individual sets of PLC logic to individual sets of FISH-cell logic and any other logic blocks. Pad <b>512</b>, output buffer <b>516,</b> and input buffer <b>518</b> are analogous to pad <b>212</b>, output buffer <b>216,</b> and input buffer <b>218</b> of Fig. 2, respectively. Also, the optional boundary scan and miscellaneous logic <b>214</b> of Fig. 2 is broken into logic <b>514a</b> and <b>514b</b> of Fig. 5.

0018For this particular implementation, the FISH-cell of Fig. 5, according to the present invention, differs from the conventional PIC circuitry of Fig. 2 in a number of significant ways. First of all, the ASB block <b>520</b> includes mux <b>534</b>, which is used to select between signal <b>540</b> from FISH cell <b>508</b> or signal <b>542</b> from ASB logic <b>528,</b> to be sent to output buffer <b>516</b> through optional boundary scan block <b>514a</b>. This selection can be set by configuration RAM cell <b>524</b> in FISH cell <b>508</b>, whose output is tied to the control input of mux <b>534</b>. Optionally, signal <b>540</b> from FISH cell <b>508</b> can also be sent to ASB logic <b>528</b>. Another option would be to permanently tie the control lead to mux <b>534</b> at the factory, thus permanently selecting one of the signals to be sent to output buffer <b>516</b>. In the same manner, signals from the input buffer <b>518</b> can be sent to ASB logic <b>528</b> and/or to FISH cell <b>508</b> after passing through optional boundary scan block <b>514a</b>. Mux <b>532</b>, whose control lead is driven by the output of RAM cell <b>522,</b> is used to select either output signal <b>546</b> from ASB logic <b>528</b> or the signal from input buffer <b>518</b>, to be sent to FISH cell <b>508</b> through signal <b>544.</b> Optionally, the control lead to mux <b>532</b> could again be permanently tied.

0019Another significant difference between the FISH-cell circuitry of Fig. 5 and the conventional PIC circuitry of Fig. 2 is the addition of one or more extra programmable RAMs and/or other programming elements (<b>526</b>) within FISH cell <b>508</b>. FISH cell <b>508</b> and ASB logic <b>528</b> can use these memory cells to provide a limited amount of flexibility in the ASB.

0020In order for the FISH-cell circuitry of Fig. 5 to function as a conventional PIC, muxes <b>532</b> and <b>534</b> may be programmed to provide direct connections between boundary scan logic <b>514a</b> and other miscellaneous FISH-cell logic <b>514b</b>. On the other hand, in order for the FISH-cell circuitry of Fig. 5 to function as an ASB-interface cell, muxes <b>532</b> and <b>534</b> may be programmed to provide (1) connections between PLC logic <b>502</b> and ASB <b>520</b>, and (2) connections between ASB <b>520</b> and pad <b>512</b> via I/O logic <b>516</b> and <b>518</b>.

0021As mentioned previously, each FISH cell is both mask programmable and field programmable. It is optionally mask programmable in the factory to allow certain connections that dictate whether or not the FISH cell will be interfacing to an ASB or I/O logic, that is, whether the FISH cell will function as an AIC or a PIC. Whether or not a FISH cell is programmed to interface to an ASB, in one preferred embodiment, the FISH cell still looks like a PIC at the edge of the PLC array, thereby keeping the PLC-PIC boundary consistent around the chip. This alleviates any software issues involved in placing an ASB within an FPGA, because the PLC-PIC array connections are essentially unchanged. Although the chip size may change when an ASB is incorporated on an FPGA, the PLC array itself will not have to have a different architectural model. Timing models will also remain the same for the PLC array with or without an ASB. The FISH cell may be mask programmed in the factory to adjust the load on certain global signal distribution networks so as to keep the timing models the same.

0022One advantage of using a single generic FISH-cell design of Fig. 5 for both the PICs and the AICs of a hybrid IC of the present invention is that the hybrid IC will work with existing FPGA software tools that are used for conventional FPGAs, such as FPGA <b>100</b> of Fig. 1. In an IC having only FPGA-type logic and no ASB, each FISH cell will be mask programmed to operate as a PIC. As such, the generic FISH cell of Fig. 5 can be used in any FPGA-related circuit -- either those ICs having only FPGA-type logic or those hybrid ICs having both FPGA- and MPD-type logic.

0023Depending on the embodiment, the FPGA-type logic in a hybrid IC of the present invention may be implemented using any suitable type of field-programmable logic, such as SRAM-based, DRAM-based, fuse-programmable, anti-fuse-programmable, EPROM-based, or EEPROM-based gate-array logic. Similarly, the MPD-type logic may be implemented using any suitable type of mask-programmable logic, such as nMOS, pMOS, CMOS, GaAs, etc.

0024Programming of the FPGA-type logic is typically done through a configuration interface that reads a stream of bits and writes data into the configuration storage, which then controls the programmable logic and routing. Typically, this configuration interface can read this stream of data automatically from many external storage media, including serial PROMs, parallel PROMs, and by interfacing with a microprocessor. One embodiment of Fig. 4 allows ASB block <b>408</b> to interface with the configuration interface logic directly, thus allowing the ASB logic to write the configuration bits, as well as control the configuration process and receive the status of the configuration process.

0025In the embodiment of Fig. 4, hybrid IC <b>400</b> has one region of FPGA-type logic (i.e., PLC array <b>402</b>) and one region of MPD-type logic (i.e., ASB <b>408</b>). In general, the present invention can be implemented as a single IC having one or more regions of FPGA-type logic and one or more regions of MPD-type logic. Moreover, the type of logic used may differ from region to region. For example, a first region of FPGA-type logic may be implemented using SRAM-based gate-array logic, while a second region of FPGA-type logic of the same hybrid IC may be implemented using DRAM-based gate-array logic. Similarly, a hybrid IC of the present invention could have regions implemented using two different types of MPD-type logic.

0026It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the principle and scope of the invention as expressed in the following claims.