Device with two integrated circuits

0001The invention relates to a method for producing an emulation circuit arrangement from an integrated circuit and an arrangement with two integrated circuits.

0002When developing application systems consisting of integrated circuits, it is necessary for certain circuits, in particular microprocessors or microcontrollers, to be operated in real time in the application system, with a large number of electrical and temporal processes in the circuit itself which are not accessible in later normal operation being monitored, so-called In -Circuit emulation (ICE). The application system can be tested, optimized and further developed together with the microcontroller.

0003The production of a variant of the series product circuit suitable for in-circuit emulation is problematic. So far, a bond-out version has been produced for this purpose, in which additional internal signals can be tapped from the outside. In addition, a circuit periphery with external components is created, through which, for example, breakpoints can be set in the program sequence, data and / or program memories can be changed and register states can be recorded over time. An operating computer forms the interface to the developer.

0004The effort to produce an emulation circuit is extremely high. Compared to the series product version, it is usually available with a considerable delay. In addition, the emulation circuit has a different operating behavior compared to the product circuit, which applies in particular to interference signals and makes troubleshooting more difficult.

0005In the literature reference M. Yasumoto et. al .: "Promising new Fabrication Process Developed for Stagged LSI's", IEDM 84, pages 816 to 819, an arrangement of two integrated circuits has already been shown, which are connected to one another by their surfaces being opposite one another. The contact surfaces accessible on the surface lie one above the other and are connected to one another via gold contact points. The two circuits each contain only one type of transistor and collectively form a ring oscillator. One of the circuits contains external contacts.

0006The object of the invention is to provide a simpler method for producing an emulation circuit. Another object is to provide an appropriate circuit arrangement.

0007These objects are achieved by a method according to the features of patent claim 1, and also by an arrangement according to the features of patent claim 6.

0008The effort for the additional manufacturing process steps for the emulation variant compared to the mass product chip is justifiable. The additional effort in the product chip, for example the contact areas in the top wiring level that are only required for the emulation variant, hardly require any space. It is advantageous that the product chip and emulation variant are based on the same output chip and therefore have almost identical temporal operating behavior.

0009A second circuit is expediently provided for tapping internal signals, which is applied to the product chip supplemented by the additional manufacturing process steps by means of a method based on the flip-chip technology.

0010The additional second chip contains suitable circuitry for breakpoints, observation channel memory, ROM emulation memory and signal drivers. It can also be used for different product chips, provided that their contact areas are arranged in the top, additional wiring level in the same grid and provide the corresponding signals. The emulation circuit arrangement is therefore available for a short time and with reasonable effort and behaves almost identically to the product chip. Due to the close spatial coupling with a ROM emulation memory, maximum system frequency can be achieved.

0011The invention is explained in more detail below with reference to the figures shown in the drawing. Show it:<dl id="dl0001"><dt>Figure 1</dt><dd>a cross section through the emulation chip variant of the series product chip supplemented with the additional manufacturing process steps;</dd><dt>Figure 2</dt><dd>a cross section through an emulation circuit arrangement with the emulation variant of the series product chip and the output chip for additional logic and output driver;</dd><dt>Figure 3</dt><dd>a detailed view of the top wiring level of the emulation chip;</dd><dt>Figure 4</dt><dd>an overall supervision of the top wiring level;</dd><dt>Figure 5</dt><dd>an overall view of the emulation circuit arrangement with emulation chip, output chip and housing;</dd><dt>Figure 6</dt><dd>ESD protection structures for the emulation chip and</dd><dt>Figure 7</dt><dd>a block diagram of the output chip.</dd></dl>

0012The cross section shown in FIG. 1 shows doping regions 1, 2 in a semiconductor substrate. The doping regions are interconnected via interconnects in connection layers 4, 5, 6. The connecting layers can contain conductor tracks made of metal, polysilicon or other electrically conductive materials. Different conductor levels are isolated from one another by passive layers, which are formed, for example, with silicon oxides.

0013Conductor tracks of different layers are electrically connected to one another via contacts 7, 8, 9, which are provided within through holes arranged in the insulation layers. In the embodiment shown, the product chip provided for mass production has three connection levels 4, 5, 6, of which the top connection level 6 is covered with a protective and passivation layer (not shown).

0014The emulation variant shown in FIG. 1 differs from the series product chip in that a further connection layer 10, separated by a further insulation layer 11, is arranged above the uppermost connection layer 6. A contact 12 connects the conductor tracks of level 10 to the conductor tracks of level 6. As is conventional, the top of the chip is closed with a passivation (not shown). The top wiring layer 6 of the product chip has corresponding contact areas 13 for the vertical contacts 12. These contact areas are unused in the product chip due to the lack of wiring level 10 and are not required for its actual function. The additional space required for the contact areas is minimal. The additional wiring layer 10 and the contacts 12 carry signals to the chip surface that are not being routed to the outside in the product chip. In the emulation variant shown, however, they can be tapped externally via contacts 14, 15. The signal lines that can be tapped in this way are, for example, chip-internal data and signal buses. On the conductor track 16 shown on the left of the top wiring level 10 of the emulation chip, a contact protrusion 14 is applied, through which the signal of the conductor track 16 is further processed in an output chip (cf. FIG. 2). As an alternative contact method, a contact by means of a bonding wire 15 is shown in the conductor track 17 shown on the right. The bond wire leads to a housing pin.

0015In order to produce the emulation chip shown in FIG. 1, the series product chip is produced without modification up to its upper wiring layer 6. Instead of the otherwise usual passivation, the insulation layer 11, the further wiring layer 10 and contact warts 14 or bonding wires 15 are applied in further manufacturing steps known per se. This requires about 3 to 4 additional masking steps compared to the production of the series chip. It would also be conceivable to produce these additional layers by means of laser beam writing techniques known per se, since the emulation chips can only be produced in small numbers and the structure size is not critical.

0016In an advantageous development of the invention, a further circuit 20 is shown in FIG. 2, which is used to output the signals present on the conductor tracks 16, 17. The output chip 20 has further circuits and driver stages suitable for in-circuit emulation. To produce the emulation chip arrangement, contact nipples 21, 22 are applied to the corresponding contact points on the conductor tracks 16, 17. These consist of solderable material. Then the chip 20, which has corresponding contact areas at the respective location of the solder balls 21, 22, is soldered on. These processing operations are based on the flip-chip technology with which integrated circuits are contacted and attached to printed circuit boards. In the present case, however, two integrated circuits are interconnected. Those surfaces through which the circuit structures of the circuits and the connection areas are accessible face each other.

0017As an alternative to the orientation of the output chip 20 shown in FIG. 2, another output chip can be provided, which is arranged in the sense of vertical integration above the emulation chip 3, the substrate of the second integrated circuit being placed directly on the wiring layer 10, into which of the opposite one , the transistor structures are introduced from the wiring layer 10-repellent surface. Vertical shafts in the second chip are guided onto the connecting surfaces 16, 17 and ensure that these surfaces are connected to the functional units in the second chip.

0018The top view of the surface of the emulation chip 3 shown in FIG. 3 shows the conductor tracks of the uppermost connection layer 6 of the series product chip. In the detail shown in Figure 3, four bus lines are shown. The lines have contact areas 31, 32, on each of which a through hole and contact 33, 34 are arranged for the connection level 10 additionally present in the emulation chip. The contact surfaces 31, 32 are widened lines of the lines in accordance with the design rules. The lines 35, 36 of the connecting layer 10, which are expediently formed from metal, connect the contact surfaces 31, 32 to connection pads 37, 38, on which the contact is made to the outside by means of bonding wires or soldering pins 39, 40. The connection pads 37, 38 are expediently located at locations under which there are no sensitive components that could be destroyed by the bonding or soldering. The diameter of a conductor track of level 6 in today's technologies is in the order of 3 µm and below, the extent of a connection surface 37 or 38 in layer 10 is in the order of about 150 µm. The illustration shown in FIG. 3 is therefore not to scale for reasons of clarity.

0019The top view of the emulation chip shown in FIG. 4 with the additional manufacturing steps compared to the product chip shows a section 50 of the arrangement of the soldering nipples. In addition, the normal output pads, also present in the product chip, are provided, onto which the bonding wires to the housing pins are stamped. However, the contact to the output chip is only via the contact warts 50. Therefore, there are also<img file="EP0905779A2_D0001.tif" />normal "connection pads 52 to soldering pins 51 are guided through corresponding lines 53 in the wiring layer 10. These soldering pins are located in the outer area, while the other, inner surface soldering pins 54 are connected to on-chip signal lines which are not directly accessible from the outside in the product chip, such as for example chip-internal The soldering pins 50 are arranged in a predetermined grid. In the example shown, the soldering nails have the same distances from one another in each direction. The distances can generally be different for horizontal and vertical directions. The grid is expediently the same for different types of product chips. Likewise, the position of the soldering tabs that correspond to their position results in signals that correspond to their function. It is thereby possible for the same output chip to be used for different emulation chips and therefore different product chip types. This is inexpensive and reduces the time lag for producing the emulation chip arrangement.

0020FIG. 5 shows that the output chip 20 is larger in area than the emulation chip 3. The structure shown in FIG. 4 faces the output chip 20 in FIG. Circuits suitable for in-circuit emulation are arranged in the emulation chip 3. These are, for example, drivers by which the output signals are provided on external connection pads 60. Also useful are an observation channel memory (so-called trace buffer) in which a chronological review of registers selected for the function test of the circuit is stored, or a program emulation memory which contains the work program for the microcontroller to be tested. During normal operation, the work program is stored in a ROM memory in the microcontroller. Due to the close spatial coupling between the program emulation memory and the emulation chip, the corresponding connecting lines are short and the emulation memory can be operated at the system frequency. The output chip 20 also includes appropriate logic for setting and monitoring program breakpoints. The pads 60 of the output chip carry signals that are connected to the inner solder balls 54 of the emulation chip. Expediently, these pads 60 are assigned protective structures 64 against electrostatic discharges (ESD), which discharge the charge pulse to a supply voltage connection in the event of an electrostatic overvoltage. The output pad 63 is connected, for example, to one of the solder balls 51 of the emulation chip 3, which also represent an output in the product chip. There is therefore no ESD protection structure in the output chip. The pads are located on a pad ring on the edge of the output chip 20. The common arrangement of emulation chip 3 and output chip 20 is in turn enclosed in a housing 65 with output pins 66.

0021A block diagram of the output chip 20 is shown in FIG. The output chip contains a bus 80 over which the internal communication runs. On the output side in front of the pads 60, a driver 81 is connected in each output line, by means of which the signals to be output are amplified and decoupled from the internal circuit blocks. The function blocks 82, ..., 85 contain those functional units which are required for the in-circuit emulation and the processing of the signals to be output and monitored as described above. Function block 82 contains the trace buffer memory. Function block 83 contains the program emulation memory. Function block 84 contains the logic for setting and monitoring program breakpoints. Function block 85 forms an interface to the signals which are picked up by emulation chip 3. It contains corresponding buffer drivers.

0022The functional units of the output chip 20 can be provided in a hard-wired manner. The emulation chip 3 must then always be adapted to the fixed interface in the output chip 20. Interface-relevant functional units are advantageously designed to be programmable. Programmable logic is particularly suitable for this. They are integrated on the output chip together with the non-interface-relevant functional units that remain the same in all applications. The signals output and input by the emulation chip 3 are routed to the other functional units via the programmable logic. Such programmable logic circuit blocks are available, for example, as FPGA (Field Programmable Gate Array). An FPGA is built up in blocks. Each block essentially contains logic circuit elements and memory elements and adjustable switches. The switch position is selected so that the desired logic function results with a desired time behavior. The setting state of the switches is determined by the content of a volatile memory. Depending on the memory content, the logic functions of the interface can thus be adapted to the currently connected emulation circuit. In the present exemplary embodiment, function blocks 84 and 85 are preferably implemented in the FPGA. The functionality of the interface to the emulation chip can be adapted very flexibly both to the emulation chip and to the manufacturer of the other emulator hardware.

0023Instead of a programmable logic circuit, a gate array can also be provided. This is a regular arrangement of prefabricated transistors, which are then connected to conductor tracks in metal levels in further production steps. The adaptation of the output chip to the desired interface properties takes place here during the final steps of its manufacture by applying a suitable conductor track. This means that the interface is mask programmable with respect to the manufacturing masks for the wiring.

0024FIG. 6 shows a cross section through the arrangement of FIG. 5. The output pad 64 is connected to the emulation chip 3 via a solder ball 70, which is connected to an internal signal line. As long as the connection between solder ball 70 and output pad 64 has not yet been established during assembly, the line connected to solder ball 70 in the emulation chip is at risk of ESD. Therefore, a conductor track is formed in the wiring layer 10 of the emulation chip 3 between the solder ball 70 and a solder ball 71 provided for a connection for a supply potential, preferably ground. This conductor track has a constriction with a reduced cross section 72. This is dimensioned such that it can discharge an ESD pulse to the supply connection 71, but can be interrupted by a current pulse impressed from the outside. If, after the two chips have been assembled, the solder ball 70 is connected to the ESD-protected pad 70, the constriction 72 is interrupted by a current pulse impressed from the outside. The ground connection between the solder balls 70, 71 described above is then no longer effective.