Register arrangement

0001The invention relates to a register arrangement for the optional processing of different length input data words.

0002The invention finds use, for example, in integrated building blocks for GSM.

0003In integrated circuits interconnected by a bus such as a 3-wire bus, the word length of the bus is required to match that of the integrated circuits. Common are words with a length of 8, 16 or 24 bits.

0004So far, the adaptation of the word length between the bus and the integrated block has been made in terms of the hardware by adapting the shift register and data register lengths to the length of the input words during block development.

0005An object of the invention is to provide a register arrangement in which the adaptation of the processing to the length of the input words by software, that is, during operation, is adjustable.

0006The object of the invention is achieved by a register arrangement according to claim 1.

0007The register arrangement according to the invention has a first shift register and a control shift register, which form an input shift register. At the data input of the input shift register data with different word lengths can be applied. Furthermore, an output register is provided, which is connected to the output of the input shift register. The memory depth of the output register is equal to the memory depth of the input shift register with no control shift register.

0008Advantageous developments emerge from the dependent claims.

0009Thus, in one embodiment, a second and a third shift register are provided in the input shift register. Furthermore, a first, a second and a third data register are provided in the output register. In addition, a switching unit is provided which selectively connects the first or the second shift register to the second data register. The first shift register is connected to the first data register and via the switching unit to the second data register. The second shift register is also connected via the switching unit to the second data register. The switching unit is controlled via the control shift register. The third shift register is connected to the third data register.

0010The control shift register may be used to select the integrated circuit, the register block in the integrated circuit and to program the register arrangement to the word length prevailing at the data input.

0011The register arrangement may be used in a mobile radio system comprising one or more integrated devices and a bus.

0012The invention will be explained below with reference to two figures.<dl id="dl0001" compact="compact"><dt>FIG. 1</dt><dd>shows a first embodiment of the register arrangement according to the invention for processing data applied to the data input with different word lengths.</dd><dt>FIG. 2</dt><dd>shows a second embodiment of the register arrangement according to the invention for processing data applied to the data input with different word lengths.</dd></dl>

0013FIG. 1 shows a first embodiment which has an input shift register with a memory depth of 24 bits. The input shift register is divided into a 4-bit control shift register STR and a 20-bit shift register SR1. The 4-bits a0, a1, a2 and a3 in the control shift register STR are used to select the desired integrated circuit (chip select) or to select the desired register block (block select). The input shift register is connected via the data input DA to the bus, for example a 3-wire bus (not shown in the figure). The data words are serially shifted via the data input DA into the input shift register controlled by the clock present at the clock input CL. As soon as a corresponding enable signal is present via the input EN (enable), the data is transported from the 20-bit wide shift register SR1 into a data register DR1.

0014The control and evaluation of the data located in the control register STR via a decoding unit Dec.

0015Through the proposed solution, both 24-bit and 16-bit long words can be processed by software control. This gives an independence of the data word length prevailing at the data input DA.

0016In Figure 2, the 24-bit input shift register is divided into a 6-bit wide control register STR, a first shift register SR1 having a memory depth of 8 bits, a second shift register SR2 also having a memory depth of 8 bits, and a third shift register SR3, which has a memory depth of 2 bits. Via the data input DA of the input shift register, the data bits are shifted serially first into the control shift register STR, then into the first shift register SR1, the third shift register SR3 and finally into the second shift register SR2.

0017Likewise in FIG. 1, the bits a0, a1, a2 and a3 of the 6-bit control register STR serve to set the desired integrated circuit (chip select) and to set the desired register block (block select). In addition, the word length of the word present at the data input DA can be set via the bits a4 and a5. The contents of bits a4 and a5 can be used according to the following table.<tables id="tabl0001" num="0001"><img file="EP0905609A2_D0001.tif" /></tables>

0018The data output of the input shift register is connected to the data input of the output register as follows. The data output of the first shift register SR1 is connected to the data input of a first data register DR1, which as well as the first shift register SR1 has a memory depth of 8 bits. In addition, the data output of the first shift register SR1 is connected to the first input of a multiplexer MUX. Connected to the second input of the multiplexer MUX is the data output of the second shift register SR2. The output of the multiplexer MUX leads to the data input of the second data register DR2. The data output of the third shift register SR3 is connected to the data input of the third data register DR3, which, like the third shift register SR3, also has a memory depth of two bits.

0019For driving the enable inputs of the three data registers DR1, DR2 and DR3, the three gates G1, G2 and G3 are provided, which are controlled by the bits a4, a5, the decoding unit Dec and another signal input.

0020The multiplexer MUX is driven via a fourth gate G4, which in the present embodiment performs an AND connection of the bits a4 and a5. Depending on the logic output state of the gate G4, the multiplexer MUX switches either the data output of the first shift register SR1 or the data output of the second shift register SR2 to the data input of the data register DR2. For example, the data output of the shift register SR2 can be connected to the data input of the data register DR2, if at the control input of the multiplexer MUX and thus at the output of the gate G4 a logical <img file="EP0905609A2_D0002.tif" />1 "is present <img file="EP0905609A2_D0003.tif" />0 "then the data output of the shift register SR1 is connected to the data input of the data register DR2.

0021When a 24-bit word is applied to the data input DA of the input shift register, the multiplexer MUX is driven so that the data output of the shift register SR2 is connected to the data input of the data register DR2. Thus, an 18-bit word, which is located in the shift registers SR1, SR2 and SR3, can be directly taken over into the data registers DR1, DR2 and DR3.

0022In a 16-bit word, the multiplexer MUX is driven so that the data output of the shift register SR1 is connected to the data input of the data register DR2. As a result, the data can be transferred directly from the shift register SR1 and the following 2-bit shift register SR3 into the data registers DR1 and DR3. The 8 bits of the shift register SR2 and the 8 bits of the data register DR2 are not used.

0023Compared to the embodiment shown in FIG. 1, the embodiment shown in FIG. 2 has the advantage that the full memory depth of the output register (18 bits) can be used, although only 16-bit wide words are available at the data input DA. This is done by writing the registers twice in succession. First, the information (data) of the shift register SR1 and the shift register SR3 are taken in the two data registers DR1 and DR3 (8 and 2 bits). Subsequently, the second 16-bit word is loaded from the bus via the data input DA in the input shift register and only the data from the shift register SR1 are transferred via the multiplexer MUX to the data register DR2.

0024By means of the embodiment according to FIG. 2, 24-bit input words (with 18-bit payload data and 6-bit control data) can be converted into 18-bit output data. A 16-bit input word with 10-bit payload and 6-bit control data can be converted to a 10-bit output word. Finally, it is also possible to convert two 16-bit input words with 20-bit user data and 12-bit control data into an 18-bit output word.