Phase estimating circuit and demodulating circuit
Abstract
The presence or absence of a clock component is detected for an input signal. If the input signal does not comprise a clock component, the operation of a computing circuit is halted, thereby further improving the accuracy of phase estimation. A signal generating circuit(a) produces a twiddle factor for DFT. A DFT circuit(31) performs discrete Fourier transform on an input signal for a predetermined number of symbols based on the twiddle factor for DFT. A pattern detecting circuit(13) examines the input signal for its pattern based on the output from the DFT circuit(31). An averaging filter(32) turns on or off the operation of the subsequent averaging filter(32) according to the detected pattern, and averages the outputs from the DFT circuit(31) to remove a noise component.

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Projected expiry passed 18 June 2018, 8.3 years ago.
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1 sheet
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Every citation, both ways
| Document | Relation | Office | Category | Cited during | Relevant claims |
|---|---|---|---|---|---|
| EP0601605A2 | Cites | European Patent Office (EPO) | XD | Search report | 1 |
13 members in 7 offices
Priority claims4
| Document | Office | Kind | Date |
|---|---|---|---|
| 25564797 | Japan | A | |
| 25564797 | Japan | – | |
| 25564797 | – | – | – |
| JP19970255647 | – | – | – |
Members13
| Document | Office | Kind | |
|---|---|---|---|
| EP0903884A2 | European Patent Office (EPO) | A2 | |
| CN1212547A | China | A | |
| JPH1198209A | Japan | A | |
| AU7188198A | Australia | A | |
| AU708424B2 | Australia | B2 | |
| US5977820A | United States of America | A | |
| SG71127A1 | Singapore | A1 | |
| JP3186665B2 | Japan | B2 | |
| EP0903884A3This record | European Patent Office (EPO) | A3 | |
| EP0903884B1 | European Patent Office (EPO) | B1 | |
| CN1143492C | China | C | |
| DE69822391D1 | Germany | D1 | |
| DE69822391T2 | Germany | T2 |
27 legal events, as 3 offices reported them to INPADOC
Over the term
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|---|---|---|---|
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
| Lapsed in a contracting state [announced via postgrant information from national office to epo]LapsedPG25 | PG25 | EP | |
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| Request for extension of the european patentAL;LT;LV;MK;RO;SIAX | AX | EP | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI | EP |
Numbers
- Publication
- 0903884
- Publication, DOCDB
- 0903884
- Publication, EPODOC
- EP0903884
- Application
- 98111262
- Application, DOCDB
- 98111262
- Application, EPODOC
- EP19980111262
Titles3
- German
- Schaltung zur Phasenschätzung und Demodulatorschaltung
- English
- Phase estimating circuit and demodulating circuit
- French
- Cricuit d'estimation de phase et circuit de démodulateur
Classification
- CPC, 1
- H04L7/027
- IPC, 3
- H04L27 22
- H04L7 00
- H04L7 027
Designated states25
- Contracting states, 19
- Austria
- Belgium
- Switzerland
- Cyprus
- Germany
- Denmark
- Spain
- Finland
- France
- United Kingdom
- Greece
- Ireland
- Italy
- Liechtenstein
- Luxembourg
- Monaco
- Netherlands (Kingdom of the)
- Portugal
- Sweden
- Extension states, 6
- Albania
- Lithuania
- Latvia
- North Macedonia
- Romania
- Slovenia