Enhanced dram with embedded registers

An enhanced DRAM contains embedded row registers (56) in the form of SRAM cells (142, 144). The row registers (56) are adjacent to the DRAM array (40), and when the DRAM comprises a group of subarrays, the row registers (56) are located between DRAM subarrays (40). When used on-chip DRAM cache (48), these registers (56) hold frequently accessed data. This data corresponds to data stored in the DRAM (34) at a particular address. When an address is supplied to the DRAM (34), it is compared to the address of the data stored in the cache (56). If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM (34) is decoupled from this read. The DRAM (34) also remains idle during this cache read unless the system opts to precharge or refresh the DRAM (34). Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM (34) is accessed and the embedded register (56) is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM (34) is achieved by decoupling the row registers from the DRAM array (40), thus allowing the DRAM cells to be precharged or refreshed during a read of the row register (56).