Liquid crystal display device and method for driving the same with driving of both ends of display electrodes

Technical Field of the Invention

0001The present invention relates to a liquid crystal display device useful as a display for video appliance, computer or other information equipment, and more particularly to a liquid crystal display device and liquid crystal driving method for driving so as to minimize luminance unevenness of each pixel.

Background of the Invention

0002Fig. 49 is a block diagram of a conventional liquid crystal display device showing an equivalent circuit of a liquid crystal panel and a drive circuit for driving this liquid crystal panel. This liquid crystal display device comprises a liquid crystal panel 14, an upper signal line drive circuit 15, a lower signal line drive circuit 16, a scanning line drive circuit 17, a control circuit 18, and a drive power source circuit 19.

0003The liquid crystal panel 14 has plural signal lines provided in the y-direction (vertical direction) and plural scanning lines provided in the x-direction (horizontal direction). The signal line is composed of upper signal line 10 and lower signal line 11 divided equally in the vertical direction, and the number of upper and lower signal lines 10, 11 is M each. The number of scanning lines 12 is 2N. The addresses of the upper and lower signal lines 10, 11 are supposed to be Y1 to YM, the addresses of the upper half scanning line 12 to be X1 to XN, and the addresses of the lower half scanning line 12 to be XN+1 to X2N.

0004In the liquid crystal panel 14 of such simple matrix type, the upper signal lines 10, lower signal lines 11, and scanning lines 12 are arranged in a matrix, and a pixel 13 is formed each at the intersection of upper signal line 10 and scanning line 12, and the intersection of lower signal line 11 and scanning line 12. The pixel 13 has a liquid crystal cell and a transparent pixel electrode, or a driving terminal including liquid crystal cell and transparent pixel electrode, and its capacitance is determined by the liquid crystal cell and pixel electrode. Herein, the capacitance of the pixel 13 is called the pixel capacitance. Incidentally, in the case of a TFT type liquid crystal panel, for example, the pixel includes TFT, liquid crystal cell and others.

0005This liquid crystal panel 14 is driven as being divided into upper and lower halves. That is, the upper signal line 10 is driven by an upper signal line drive circuit 15, and the lower signal line 11 by a lower signal line drive circuit 16. The scanning line 12 is driven from one end side of the scanning line 12 by one scanning line drive circuit 17.

0006The liquid crystal panel 14 shown in Fig. 49 is driven from the left end of the scanning line 12, and such driving method of driving each pixel 13 by applying a driving voltage to the scanning line 12 from one end is called the scanning line one-end drive. The upper signal line drive circuit 15 and lower signal line drive circuit 16 are disposed around the liquid crystal panel 14 depending on the number of upper signal lines 10 and lower signal lines 11 and the number of scanning lines 12.

0007The control circuit 18 is a control circuit for controlling the upper signal line drive circuit 15, lower signal line drive circuit 16, and scanning line drive circuit 17 on the basis of an input image signal. The drive power source circuit 19 is a circuit for supplying a driving voltage to the upper signal line drive circuit 15, lower signal line drive circuit 16, and scanning line drive circuit 17. Herein, there are five driving voltages, V(+), V(-), VH, Vref, and VL, and the pixels 13 are driven by the combination thereof.

0008The scanning line drive circuit 17, for upper and lower divided driving of signal lines, scans parallel the scanning lines 12 of addresses X1 to XN and scanning lines 12 of addresses XN+1 to X2N. That is, the scanning line drive circuit 17 starts scanning simultaneously from the scanning lines 12 of addresses X1 and XN+1, and continues to scan sequentially at the same timing from address X1 to XN, and from address XN+1 to X2N.

0009As shown in Fig. 50, the scanning line drive circuit 17 scans the scanning lines 12 sequentially from address X1 to X2N, applies a driving voltage of V(+) or V(-) to a selected scanning line 12, and applies a operation reference voltage Vref to non-selected scanning lines 12. The upper signal line drive circuit 15 and lower signal line drive circuit 16 drive the signal lines 10, 11 at signal line driving voltages VH, VL which are first scanning pulses, depending on the control signal of the control circuit 18. Output sections of upper signal line drive circuit 15 and lower signal line drive circuit 16 are composed of two analog switches for selecting and issuing one out of two values (VH, VL). The relation of driving voltages V(+), V(-), VH, VL, and Vref should satisfy the following formula (1).<maths id="math0001" num="(1)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtext>VH-Vref=Vref-VL</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>V=V(+)-Vref=Vref-V(-)</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0001.tif" /></maths> where V is the amplitude of the scanning line driving voltage applied to the liquid crystal cell of each pixel 13.

0010The upper signal line drive circuit 15 in Fig. 49 issues a signal line driving voltage of either VH or VL to M upper signal lines 10 simultaneously in every horizontal scanning, corresponding to the scanning lines from address X1 to XN. The lower signal line drive circuit 16 issues a signal line driving voltage of either VH or VL to M lower signal lines 11 simultaneously in every horizontal scanning, corresponding to the scanning lines from address XN+1 to X2N. The scanning line drive circuit 17 selects the scanning line 12 sequentially in every horizontal scanning, and issues a scanning line driving voltage V(+) or V(-), which is a second scanning pulse, to the selected scanning line 12 from the left side end, and issues an operation reference voltage Vref to the non-selected scanning lines 12. Therefore, the output section of the scanning line drive circuit 17 is composed of three analog switches for selecting and issuing one out of three values, V(+), V(-), and Vref. The output resistance of these three analog switches (also called ON resistance) is named Ro.

0011In this way, the liquid crystal panel 14 is driven sequentially. As shown in Fig. 49, if the liquid crystal panel 14 is composed of upper and lower screens, the two screens are scanned simultaneously. Accordingly, the output ends of the upper signal line drive circuit 14 and lower signal line drive circuit 15 are provided by the same number.

0012In such conventional liquid crystal display device of one-end driving of scanning lines, a delay occurs in the driving voltage of each pixel due to presence of wiring resistance r of scanning line 12 and pixel capacitance c. Accordingly, the effective voltage differs slightly in each pixel from the driving end to terminal end of scanning line 12, and therefore the brightness of each pixel varies slightly from the driving end to terminal end of scanning line 12. Such luminance unevenness is called a lateral luminance error. Moreover, crosstalk occurs due to distortion of driving voltage of pixels. This is called lateral crosstalk. Similarly, in driving of signal lines, a delay occurs due to wiring resistance of signal line and pixel capacitance, and the brightness of each pixel differs slightly from the driving end to terminal end of signal line, which is a longitudinal luminance error, and crosstalk is caused due to distortion of waveform by signal line driving. It is called longitudinal crosstalk.

0013Such lateral or longitudinal luminance error or crosstalk become larger as the liquid crystal display device has a wider screen, which was a serious cause of deterioration of picture quality. For development of driving method capable of eliminating the lateral or longitudinal luminance error and crosstalk, drive analysis including the structure of liquid crystal panel and drive circuit is indispensable. However, as for lateral or longitudinal luminance error, crosstalk, or delay time of driving current and driving voltage of scanning line or signal line, results of calculation and measured values did not coincide in the conventional drive analysis method. Further, it requires much time and cost for development of optimum driving method and optimum drive circuit.

0014The above problems are described in detail below. Herein, problems are analyzed by referring to an example of lateral luminance error and scanning line driving current in the liquid crystal panel 14 of simple matrix type. Fig. 50 (A) is an output waveform diagram of upper signal line drive circuit 15 and lower signal line drive circuit 16 satisfying the relation of formula (1). Fig. 50 (B) is an output waveform diagram of scanning line drive circuit 17. Fig. 50 (C), (D) are voltage waveform diagrams applied to the pixels 13 located at the driving end and terminal end, respectively. In the diagrams, TH refers to the horizontal scanning time, TV is the vertical scanning time, and N is 1/2 of total number of scanning lines.

0015Point (XN, Y1) denotes the pixel 13 at the intersection of the XN-th scanning line 12 and Y1-th signal lines 10, 11, and (XN, YM) is the pixel 13 at the intersection of the XN-th scanning line 12 and YM-th signal lines 10, 11. The pixel 13 at (XN, Y1) in Fig. 50 (C) is at the driving end of the scanning line drive circuit 17, and the pixel 13 at (XN, YM) in Fig. 50 (D) is at the terminal end of the scanning line drive circuit 17. Thus, the voltage applied to the pixels 13 differs between the driving end and the terminal end of the scanning line 12. The driving end is driven by an ideal waveform (a combined rectangular waveform), but at the terminal end of the scanning line 12, as shown in Fig. 50 (D), a delay occurs, and the waveform is distorted at the rising edge of the rectangular waveform.

0016The fall time of the scanning line driving voltage is identical throughout the driving end to the terminal end in a same scanning line because the signal lines Y1 to YM are simultaneously driven by the upper and lower signal line drive circuits 15, 16, and is hence not related to occurrence of lateral luminance error. Signal line driving voltages VH, VL have a same delay time throughout the driving end to the terminal end in a same scanning line 12, and are hence not related to occurrence of lateral luminance error. Accordingly, in Fig. 50 (C) and (D), regarding the fall time of scanning line driving voltage to be 0, the signal line driving voltages VH, VL may be estimated to be ideal pulse waveforms. Moreover, if there is any change in the pixel capacitance due to driving voltage, it is not related to occurrence of lateral luminance error. Also change in pixel capacitance can be corrected later, and is hence assumed to be constant.

0017An equivalent circuit of the liquid crystal panel 14 is shown in Fig. 2. Herein, the wiring resistance per pixel of upper signal line 10 and lower signal line 11 is supposed to be rs, the wiring resistance per pixel of scanning line 12 to be r, and the pixel capacitance of the pixel 13 linked to the scanning line 12 to be c. In the liquid crystal panel 14, 2(N-1) scanning lines other than the scanning line 12 selected by the scanning line drive circuit 17 are driven at operation reference voltage Vref, and the upper signal line 10 and lower signal line 11 are driven at operation reference voltage Vref or signal line driving voltage VH or VL. Accordingly, the driving end of 2(N-1) scanning lines 12, and the driving end of upper signal line 10 and lower signal line 11 are at the potential of Vref in average. Therefore, as electrical characteristics, the potential of one side of each pixel capacitance c is regarded to be Vref. Hence, as shown in Fig. 51 (A), one scanning line 12 is expressed by a distributed parameter circuit composed of wiring resistance r and pixel capacitance c (formed at intersections of addresses Y1 to YM). Fig. 51 (A) shows a circuit in which M wiring resistances r and M pixel capacitance c are connected in ladder form. (Supposing the wiring resistance of signal line to be rs and the pixel capacitance linked to the signal line to be cs, one signal line is also expressed by a distributed parameter circuit, same as in Fig. 51 (A), composed of N wiring resistances rs and N pixel capacitance cs.)

0018In the prior art, the liquid crystal panel was driven and analyzed by the equivalent circuit shown in Fig. 51 (B). In this equivalent circuit, supposing the sum M · r of the scanning lines 12 to be RL and the sum M · c of the pixel capacitance c to be CL, the scanning lines 12 are expressed by a series circuit composed of resistance RL and pixel capacitance CL. Fig. 51 (B) shows a circuit for driving the scanning lines 12 at voltage V, supposing the output resistance of the scanning line drive circuit 17 to be Ro and the analog switch built in the scanning line drive circuit 17 to be SW. In this equivalent circuit, the terminal end voltage of the scanning line 12 is expressed as terminal voltage Vcm of a capacitor having a capacitance value of CL. Supposing SW to be ON when t=0, and, Ro=0, Vcm is given in formula (2).<maths id="math0002" num="(2)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtext>Vcm=V[1-exp{-t/(RL·CL)}]</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>RL=M·r, CL=M·c</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0002.tif" /></maths>

0019In scanning line one-end driving, the effective voltage of the pixel capacitance c differs between the driving end and terminal end. Accordingly, the transmittance of liquid crystal cell differs in the lateral direction, and a lateral luminance error occurs in the screen of the liquid crystal display device. Due to this lateral luminance error, display unevenness of screen appears, and the picture quality deteriorates. The lateral luminance error is more obvious when the display screen is larger, and it has no practical problem in a liquid crystal display device of, for example, 12.1 inches in the diagonal length, but display unevenness is visually recognized in a 17-inch liquid crystal display device.

0020Supposing the driving waveform of the signal line drive circuit shown in Fig. 50 (A) to be fs, and the driving waveform of the scanning line drive circuit shown in (B) to be fc, the driving waveform of the pixel 13 at the driving end shown in (C) is (fc+fs). The effective voltage Ve of the driving waveform (fc+fs) is obtained by integrating the value of (fc+fs)²dt over one period TV, dividing the integral value by the period, and extracting the square root of the obtained quotient. The effective value Vecl of the pixel voltage at the driving end of the scanning line 12 is obtained by formula (3).

0021Where,<maths id="math0003"><math display="block"><mrow><msup><mrow><mtext>Vecl=[(V+V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N+(N-1)(V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></math><img file="EP0875879A1_D0003.tif" /></maths><ul id="ul0001" list-style="none" compact="compact"><li>V: amplitude of scanning line driving voltage</li><li>N: 1/2 of total number of scanning lines</li><li>a: ratio of amplitude of scanning line driving voltage (<maths id="math0004"><math display="inline"><mrow><mtext>V=V(+)-Vref</mtext></mrow></math><img file="EP0875879A1_D0004.tif" /></maths>) and amplitude of signal line driving voltage (VH-Vref)<maths id="math0005" num="(3)"><math display="block"><mrow><mtext>V=a(VH-Vref)</mtext></mrow></math><img file="EP0875879A1_D0005.tif" /></maths> In formula (3), V denotes the scanning line driving voltage, and (V/a) refers to the signal line driving voltage, and therefore, supposing the signal line driving voltage to be an ideal pulse, to determine the effect of delay of the scanning line driving voltage at the terminal end, V in formula (3) must be replaced by Vcm in formula (2), but the calculation is complicated, and therefore it is approximated as follows:<maths id="math0006"><math display="block"><mrow><msup><mrow><mtext>∫(Vcm+V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·dt≒(1+1/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>∫(Vcm)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·dt</mtext></mrow></math><img file="EP0875879A1_D0006.tif" /></maths> Then, to determine the effective voltage Vecm of pixel at terminal end of the scanning line 12, the term of <maths id="math0007"><math display="inline"><mrow><msup><mrow><mtext>(V+V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>/N</mtext></mrow></math><img file="EP0875879A1_D0007.tif" /></maths> in formula (3) may be replaced by<maths id="math0008"><math display="block"><mrow><msup><mrow><mtext>{(V+V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/TV}·∫[1-exp{-t/RL·CL}]</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·dt</mtext></mrow></math><img file="EP0875879A1_D0008.tif" /></maths> The integration is performed in the horizontal scanning period TH. Since the liquid crystal display device is designed to satisfy <maths id="math0009"><math display="inline"><mrow><mtext>TV = N · TH</mtext></mrow></math><img file="EP0875879A1_D0009.tif" /></maths>, and <maths id="math0010"><math display="inline"><mrow><mtext>TH» CL · RL</mtext></mrow></math><img file="EP0875879A1_D0010.tif" /></maths>, the above formula is transformed into formula (4) by integrating from 0 to TH.<maths id="math0011"><img file="EP0875879A1_D0011.tif" /></maths> Therefore, the effective voltage Vecl at driving end of the scanning line 12 and effective voltage Vecm at terminal end are expressed as shown in formula (5). </li></ul><maths id="math0012" num="(5)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msup><mrow><mtext>Vecl=[(V+V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N +{(N-1)(V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N}]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></mtd></mtr><mtr><mtd><mrow><msup><mrow><mtext>Vecm=[{V+V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N}{1-1.5RL·CL/TH} +{(N-1)(V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N}]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0012.tif" /></maths>

0022The lateral luminance error is determined by effective voltage Vecl - effective voltage Vecm. Furthermore, the ratio γ of effective voltage Vecm at terminal end and effective voltage Vecl at driving end is as expressed in formula (6).<maths id="math0013"><math display="block"><mrow><mtext>γ=Vecm/Vecl</mtext><mspace linebreak="newline" /><msup><mrow><mtext> =[{(1-1.5RL·CL/TH)·(a+1)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N-1} /{(a+1)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N-1)}]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></math><img file="EP0875879A1_D0013.tif" /></maths>

0023From a >> 1, then<maths id="math0014" num="(6)"><math display="block"><mrow><msup><mrow><mtext>γ≒[1-1.5RL·CL/TH·a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N-1)]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></math><img file="EP0875879A1_D0014.tif" /></maths> The scanning line driving current I can be determined as follows. When the capacitor c is charged with v, the charge transfer by charging is v · c, and therefore supposing the number of scanning lines to be 2N, number of signal lines to be M, pixel capacitance of scanning line to be c, and vertical scanning time to be TH, formula (7) is obtained when the scanning line driving voltage is V(+) and V(-).

0024Drive current when driving voltage is V(+):<maths id="math0015"><math display="block"><mrow><mtext>I(+)=(2N/TV)M·c{V(+)-VL}=2N·M·c{V(+)-VL}/(TV)</mtext></mrow></math><img file="EP0875879A1_D0015.tif" /></maths>

0025Drive current when driving voltage is V(-):<maths id="math0016" num="(7)"><math display="block"><mrow><mtext>I(-)=2N·M·c{V(-)-VH}/(TV)</mtext></mrow></math><img file="EP0875879A1_D0016.tif" /></maths>

0026In the liquid crystal display devices of 12.1 inches and 17 inches in the screen diagonal length of liquid crystal panel, the value of the lateral luminance error (expressed in the difference of effective voltage) calculated from formulas (5) and (6), and the value of the scanning line driving current calculated from formula (7) in the condition of <maths id="math0017"><math display="inline"><mrow><mtext>VH = -VL = 2.1 V</mtext></mrow></math><img file="EP0875879A1_D0017.tif" /></maths> are shown below (calculation 1).

(1) In 12.1-inch liquid crystal display device

0027<ul id="ul0002" list-style="none" compact="compact"><li>Lateral luminance error =70.5mV</li><li>γ =0.975</li><li>Voltage Vecl =2.74V</li><li>Scanning line driving current I = 1.42 mA (measured value = 1.0 mA)</li></ul>

Measuring condition

0028<ul id="ul0003" list-style="none" compact="compact"><li>TH=27.8 µS, TV=8.34mS, c=0.26pF</li><li>r=1.5 Ω, N=300, M=800 × 3, a=14.5</li><li>V=30.5V, V(+)=31.55V</li></ul>

(2) In 17-inch liquid crystal display device

0029<ul id="ul0004" list-style="none" compact="compact"><li>Lateral luminance error =96.2mV</li><li>γ =0.963</li><li>Voltage Vecl =2.60V</li><li>Scanning line driving current I = 1.75 mA (measured value = 0.97 mA)</li></ul>

Measuring condition

0030<ul id="ul0005" list-style="none" compact="compact"><li>TH=28 µS, TV=14.34mS, c=0.19pF</li><li>r=1.5 Ω, N=512, M=1280 × 3, a=15.5</li><li>V=32.5V, V(+)=33.55V</li></ul>

0031In the above results, in the 12.1-inch liquid crystal display device, an effective voltage difference of 70.5 mV (lateral luminance error) is caused, whereas in the 17-inch liquid crystal display device, an effective voltage difference of 96.2 mV (lateral luminance error) is caused. Although variable with the display pattern, if the effective voltage difference of the liquid crystal is more than 10 mV, it can be distinguished by the human eye. Numerical expression of the distinguishable effective voltage difference is very difficult because the limit value differs in each display pattern and the human individual error is involved. However, the limit is generally considered to be somewhere between 10 and 15 mV, and at a double value of 20 to 30 mV, the lateral luminance error can be clearly distinguished regardless of the display pattern or human individual difference.

0032The above result of calculation is far more than the visually distinguishable value, and the lateral luminance error is sure to be recognized in both 12.1-inch and 17-inch liquid crystal display devices. Actually in the 12.1-inch device, if recognized visually, the error is small enough to be allowed practically. In this sense, the effective voltage difference is estimated in a range of 20 to 30 mV. In the 17-inch liquid crystal display device, there is an effect on the picture quality, and the effective voltage difference can be clearly recognized visually, and hence the effective voltage difference is estimated around 30 mV. It is not such a large value as 96 mV as in the result of calculation.

0033Furthermore, the calculation result of driving current of scanning line is much larger value than the measured value, and the error is significant. Similarly, the driving current of signal line can be determined, and the result of calculation is much larger than the measured value. Thus, in the equivalent circuit in Fig. 51 (B), the result of calculation and measured value do not coincide, and when the number of pixels in the liquid crystal panel increases, it cannot be applied in drive analysis.

0034Thus, the lateral luminance error caused by delay in the scanning line driving voltage appears as display unevenness of screen, and the picture quality deteriorates. In one-end driving of scanning line 12, the lateral luminance error is not a practical problem in the 12.1-inch liquid crystal panel, but it is a serious problem in the 17-inch liquid crystal panel. Incidentally, when driving the signal line from one end, a longitudinal luminance error is caused by the delay time of the signal line driving voltage, which also results in unevenness in the screen. Development of liquid crystal display device free from lateral or longitudinal luminance error or crosstalk requires drive analysis of scanning lines and signal lines, but in the conventional method, as mentioned above, the result of drive analysis does not agree with the measured value.

Summary of the Invention

0035The invention is devised in the light of the problems of the prior art discussed above, and hence proposes a liquid crystal display device capable of reducing the delay occurring in the driving voltage caused by the pixel capacitance and the wiring resistance of scanning lines 12 or signal lines 10, 11, in the liquid crystal panel 14. As a result, the lateral or longitudinal luminance error and crosstalk can be decreased, and the picture quality can be enhanced. Moreover, by employing the drive analysis method of higher precision, the scanning lines and signal lines can be expressed by a simple equivalent circuit, thereby realizing a liquid crystal display device and its driving method capable of realizing an optimum design of driving circuit efficiently and at low cost.

0036To solve the problems (described in the preceding section), the invention as set forth in claim 1 of the present application comprises: <ul id="ul0006" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, and disposing pixels at intersections of the signal lines and scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a first scanning line drive circuit for applying a second scanning pulse from each one end of the scanning lines to each pixel sequentially in every horizontal scanning,</li><li>a second scanning line drive circuit for applying the second scanning pulse from each other end of the scanning lines to each pixel sequentially, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the signal line drive circuit on the basis of an input image signal.</li></ul>

0037The invention as set forth in claim 2 comprises: <ul id="ul0007" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing the signal lines into plural upper signal lines and lower signal lines in the vertical direction, and disposing pixels at intersections of the upper and lower signal lines and scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a first signal line drive circuit for applying a first scanning pulse from one end of the upper signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a second signal line drive circuit for applying the first scanning pulse from one end of the lower signal line to each pixel simultaneously in every horizontal scanning,</li><li>a first scanning line drive circuit for applying a second scanning pulse from each one end of the scanning lines to each pixel sequentially in every horizontal scanning,</li><li>a second scanning line drive circuit for applying the second scanning pulse from each other end of the scanning lines to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal.</li></ul>

0038The invention as set forth in claim 3 comprises: <ul id="ul0008" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing the signal lines into plural upper signal lines and lower signal lines in the vertical direction, and disposing pixels at intersections of the upper and lower signal lines and scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a first signal line drive circuit for applying a first scanning pulse from each one end of the upper signal line to each pixel simultaneously in every horizontal scanning,</li><li>a second signal line drive circuit for applying the first scanning pulse from each one end of the lower signal line to each pixel simultaneously in every horizontal scanning,</li><li>a scanning line drive circuit for applying a second scanning pulse from each one end of the scanning lines to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal.</li></ul>

0039The invention as set forth in claim 4 comprises: <ul id="ul0009" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, and disposing pixels at intersections of the signal lines and scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a first signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a second signal line drive circuit for applying the first scanning pulse from each other end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a scanning line drive circuit for applying a second scanning pulse from each one end of the scanning lines to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal.</li></ul>

0040The invention as set forth in claim 5 comprises: <ul id="ul0010" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, and disposing pixels at intersections of the signal lines and scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a first signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a second signal line drive circuit for applying the first scanning pulse from each other end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a first scanning line drive circuit for applying a second scanning pulse from each one end of the scanning lines to each pixel sequentially in every horizontal scanning,</li><li>a second scanning line drive circuit for applying the second scanning pulse from each other end of the scanning lines to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal.</li></ul>

0041The invention as set forth in claim 6 comprises: <ul id="ul0011" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing the scanning lines into plural left scanning line and right scanning line in the horizontal direction, and disposing pixels at intersections of the signal lines and right and left scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a first scanning line drive circuit for applying a second scanning pulse from each one end of the left scanning line to each pixel sequentially in every horizontal scanning,</li><li>a second scanning line drive circuit for applying the second scanning pulse from each one end of the right scanning line to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the signal line drive circuit on the basis of an input image signal.</li></ul>

0042The invention as set forth in claim 7 comprises: <ul id="ul0012" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing the scanning lines into plural left scanning lines and right scanning lines in the horizontal direction, and disposing pixels at intersections of the signal lines and right and left scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the liquid crystal cells of pixels,</li><li>a first signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a second signal line drive circuit for applying the first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a first scanning line drive circuit for applying a second scanning pulse from each one end of the left scanning line to each pixel sequentially in every horizontal scanning,</li><li>a second scanning line drive circuit for applying the second scanning pulse from each one end of the right scanning line to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal.</li></ul>

0043The invention as set forth in claim 8 comprises: <ul id="ul0013" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing the signal lines into plural upper signal lines and lower signal lines in the vertical direction, dividing the scanning lines into plural left scanning lines and right scanning lines in the horizontal direction, and disposing pixels at intersections of the upper and lower signal lines and right and left scanning lines, where the optical state of liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a first signal line drive circuit for applying a first scanning pulse from each one end of the upper signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a second signal line drive circuit for applying the first scanning pulse from each one end of the lower signal line to each pixel simultaneously in every horizontal scanning,</li><li>a first scanning line drive circuit for applying a second scanning pulse from each one end of the left scanning line to each pixel sequentially in every horizontal scanning,</li><li>a second scanning line drive circuit for applying the second scanning pulse from each one end of the right scanning line to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal.</li></ul>

0044The invention as set forth in claim 9 relates to claim 1 or 6 of the invention, in which the first and second scanning line drive circuits and signal line drive circuit are driven so that the value of the effective voltage applied to each pixel may be within a specified range, supposing the number of scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, and the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, regarding each scanning line of 2N scanning lines to be M/2 stages of ladder form distributed rc circuit, and assuming the equivalent circuit of scanning lines as seen from the first and second scanning line drive circuits to be an RC series circuit composed of resistance R of <maths id="math0018"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0018.tif" /></maths> and capacitance C of <maths id="math0019"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0019.tif" /></maths>, or supposing the wiring resistance per pixel of the signal lines to be rs, and the pixel capacitance per pixel of the signal lines including the liquid crystal cell to be cs, regarding each signal line out of M signal lines to be 2N stages of ladder form distributed rscs circuit, and supposing the equivalent circuit of scanning lines as seen from the signal line drive circuit to be an RC series circuit composed of resistance R of <maths id="math0020"><math display="inline"><mrow><mtext>4N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0020.tif" /></maths> and capacitance C of <maths id="math0021"><math display="inline"><mrow><mtext>4N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0021.tif" /></maths>.

0045The invention as set forth in claim 10 relates to any one of claims 2, 5, 7 and 8 of the invention, in which the first and second scanning line drive circuits and first and second signal line drive circuit are driven so that the value of the effective voltage applied to each pixel may be within a specified range, supposing the number of scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, and the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, regarding each scanning line of 2N scanning lines to be M/2 stages of ladder form distributed rc circuit, and assuming the equivalent circuit of scanning lines as seen from the first and second scanning line drive circuits to be an RC series circuit composed of resistance R of <maths id="math0022"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0022.tif" /></maths> and capacitance C of <maths id="math0023"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0023.tif" /></maths>, or supposing the wiring resistance per pixel of upper and lower signal lines to be rs, and the pixel capacitance per pixel of the upper and lower signal lines including the liquid crystal cell to be cs, regarding each one of upper and lower signal lines out of M upper and lower signal lines to be N stages of ladder form distributed rscs circuit, and supposing the equivalent circuit of scanning lines as seen from the first and second signal line drive circuits to be an RC series circuit composed of resistance R of <maths id="math0024"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0024.tif" /></maths> and capacitance C of <maths id="math0025"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0025.tif" /></maths>.

0046The invention as set forth in claim 11 relates to claim 3 or 4 of the invention, in which the scanning line drive circuit and first and second signal line drive circuit are driven so that the value of the effective voltage applied to each pixel may be within a specified range, supposing the number of scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, and the number of pixels formed in one scanning line to be M, regarding the scanning lines to be M stages of ladder form distributed rc circuit, and assuming the equivalent circuit of scanning lines as seen from the scanning line drive circuits to be an RC series circuit composed of resistance R of <maths id="math0026"><math display="inline"><mrow><mtext>2M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0026.tif" /></maths> and capacitance C of <maths id="math0027"><math display="inline"><mrow><mtext>2M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0027.tif" /></maths>, or supposing the wiring resistance per pixel of signal lines to be rs, the pixel capacitance per pixel of the signal lines including the liquid crystal cell to be cs, and the number of pixels formed in one upper and lower signal line to be N, regarding the upper and lower signal lines to be N stages of ladder form distributed rscs circuit, and supposing the equivalent circuit of upper and lower signal lines as seen from the first and second signal line drive circuits to be an RC series circuit composed of resistance R of <maths id="math0028"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0028.tif" /></maths> and capacitance C of <maths id="math0029"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0029.tif" /></maths>.

0047The invention as set forth in claim 12 comprises: <ul id="ul0014" list-style="none" compact="compact"><li>a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, and disposing pixels at intersections of the signal lines and scanning lines, where the optical state of liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels,</li><li>a signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning,</li><li>a scanning line drive circuit for applying a second scanning pulse from each one end of the scanning lines to each pixel sequentially in every horizontal scanning, and</li><li>a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the signal line drive circuit on the basis of an input image signal,</li><li>said liquid crystal panel being driven by the scanning line drive circuit and signal line drive circuit so that the value of the effective voltage applied to each pixel may be within a specified range,</li><li>supposing the number of the scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, and the number of pixels formed in one scanning line to be M, regarding the scanning lines to be M stages of ladder form distributed rc circuit, and supposing the equivalent circuit of scanning lines as seen from the scanning line drive circuits to be an RC series circuit composed of resistance R of <maths id="math0030"><math display="inline"><mrow><mtext>2M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0030.tif" /></maths> and capacitance C of <maths id="math0031"><math display="inline"><mrow><mtext>2M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0031.tif" /></maths>, or</li><li>supposing the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance per pixel of the signal lines including the liquid crystal cell to be cs, and the number of pixels formed in one signal line to be 2N, regarding the signal lines to be 2N stages of ladder form distributed rscs circuit, and supposing the equivalent circuit of signal lines as seen from the signal line drive circuit to be an RC series circuit composed of resistance R of <maths id="math0032"><math display="inline"><mrow><mtext>4N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0032.tif" /></maths> and capacitance C of <maths id="math0033"><math display="inline"><mrow><mtext>4N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0033.tif" /></maths>.</li></ul>

0048The invention as set forth in claim 13 relates to a driving method of liquid crystal display device for driving a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing virtually, or dividing, said signal lines into plural upper signal line and lower signal line at the virtual terminal end, dividing virtually, or dividing, the scanning lines into plural left scanning line and right scanning line at the virtual terminal end, and disposing pixels at intersections of the upper and lower signal lines and right and left scanning lines, where the optical state of liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels, comprising: <ul id="ul0015" list-style="none" compact="compact"><li>a first signal line drive circuit for applying a first scanning pulse from one end of the upper signal line to each pixel simultaneously in every horizontal scanning, a second signal line drive circuit for applying the first scanning pulse from one end of the lower signal line to each pixel simultaneously in every horizontal scanning, a first scanning line drive circuit for applying a second scanning pulse from each one end of the left scanning line to each pixel sequentially in every horizontal scanning, a second scanning line drive circuit for applying the second scanning pulse from each one end of the right scanning line to each pixel sequentially in every horizontal scanning, and a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal,</li><li>in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, and the point intersecting with the x-th signal line from the drive end of the right and left scanning lines to be a virtual terminal end, or a divided terminal end, the voltage Vgw (x, t) of the second scanning pulse applied to the pixel positioned at the virtual terminal end or terminal end is,</li><li>supposing the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the voltage of the second scanning pulse at the drive end of right and left scanning lines to be changed from Vgn to Vgn+1 at time t=0, the operation reference voltage at this time to be Vref, the output resistance of the first and second scanning line drive circuits to be Rgw, and setting <maths id="math0034"><math display="inline"><mrow><mtext>x=M/2</mtext></mrow></math><img file="EP0875879A1_D0034.tif" /></maths>,</li><li>given as<maths id="math0035"><math display="block"><mrow><msup><mrow><mtext>Vgw(x, t) =(Vgn-Vgn+1)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·c·x·Rgw)} +Vgn+1-Vref</mtext></mrow></math><img file="EP0875879A1_D0035.tif" /></maths></li><li>or further supposing the point intersecting with the y-th scanning line from the drive end of the upper and lower signal lines to be virtual terminal end or divided terminal end, the voltage Vsw (y, t) of the first scanning pulse applied to the pixel positioned at the virtual terminal end or terminal end is,</li><li>supposing the wiring resistance per pixel of the upper and lower signal lines to be rs, the pixel capacitance per pixel of the signal line including the liquid crystal cell to be cs, the operation reference voltage of VH and VL to be Vref1 and Vref2, respectively, the voltage of the first scanning pulse at drive end of upper and lower signal lines to be VH and VL alternately repeated at every TH, the output resistance of the first and second signal line drive circuits to be R sw, and setting <maths id="math0036"><math display="inline"><mrow><mtext>y=N</mtext></mrow></math><img file="EP0875879A1_D0036.tif" /></maths>,</li><li>given, if changing over to VH at t=0, as<maths id="math0037"><math display="block"><mrow><msup><mrow><mtext>Vsw(y, t) =(VH-Vref1)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y·cs· Rsw)}]</mtext></mrow></math><img file="EP0875879A1_D0037.tif" /></maths></li><li>or, if changing over to VL at t=0, as<maths id="math0038"><math display="block"><mrow><msup><mrow><mtext>Vsw(y, t) =(VL-Vref2)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y·cs· Rsw)}]</mtext></mrow></math><img file="EP0875879A1_D0038.tif" /></maths></li></ul>

0049The invention as set forth in claim 14 relates to a driving method of liquid crystal display device for driving a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing virtually, or dividing, into plural left scanning line and right scanning line at the virtual terminal end of the scanning lines, and disposing pixels at intersections of the signal lines and right and left scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels, comprising: <ul id="ul0016" list-style="none" compact="compact"><li>a signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning, a first scanning line drive circuit for applying a second scanning pulse from each one end of the left scanning line to each pixel sequentially in every horizontal scanning, a second scanning line drive circuit for applying the second scanning pulse from each one end of the right scanning line to each pixel sequentially in every horizontal scanning, and a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the signal line drive circuits on the basis of an input image signal,</li><li>in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, and the point intersecting with the x-th signal line from the drive end of the scanning lines to be a virtual terminal end, or a divided terminal end, the voltage Vgw (x, t) of the second scanning pulse applied to the pixel positioned at the virtual terminal end or terminal end is,</li><li>supposing the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the voltage of the second scanning pulse at the drive end of right and left scanning lines to be changed from Vgn to Vgn+1 at time t=0, the operation reference voltage at this time to be Vref, the output resistance of the first and second scanning line drive circuits to be Rgw, and setting <maths id="math0039"><math display="inline"><mrow><mtext>x=M/2</mtext></mrow></math><img file="EP0875879A1_D0039.tif" /></maths>,</li><li>given as<maths id="math0040"><math display="block"><mrow><msup><mrow><mtext>Vgw(x, t) =(Vgn-Vgn+1)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4·r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·c·x· Rgw)}+Vgn+1-Vref</mtext></mrow></math><img file="EP0875879A1_D0040.tif" /></maths></li><li>or further supposing the point intersecting with the y-th scanning line from the drive end of the signal lines to be terminal end, the voltage Vss (y, t) of the first scanning pulse applied to the pixel positioned at the terminal end is,</li><li>supposing the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance per pixel of the signal line including the liquid crystal cell to be cs, the operation reference voltage of VH and VL to be Vref1 and Vref2, respectively, the voltage of the first scanning pulse at drive end of signal lines to be VH and VL alternately repeated at every TH, the output resistance of the signal line drive circuits to be Rss, and setting <maths id="math0041"><math display="inline"><mrow><mtext>y=2N</mtext></mrow></math><img file="EP0875879A1_D0041.tif" /></maths>,</li><li>given, if changing over to VH at t=0, as<maths id="math0042"><math display="block"><mrow><msup><mrow><mtext>Vss(y, t) =(VH-Vref1)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y· cs·Rss)}]</mtext></mrow></math><img file="EP0875879A1_D0042.tif" /></maths></li><li>or, if changing over to VL at t=0, as<maths id="math0043"><math display="block"><mrow><msup><mrow><mtext>Vss(y, t) =(VL-Vref2)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y· cs·Rss)}]</mtext></mrow></math><img file="EP0875879A1_D0043.tif" /></maths></li></ul>

0050The invention as set forth in claim 15 relates to a driving method of liquid crystal display device for driving a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, dividing virtually, or dividing, into plural upper signal lines and lower signal lines at the virtual terminal end of the signal lines, disposing pixels at intersections of the upper and lower signal lines and the scanning lines, and disposing a liquid crystal cell between electrodes of the pixels, comprising: <ul id="ul0017" list-style="none" compact="compact"><li>a first signal line drive circuit for applying a first scanning pulse from each one end of the upper signal line to each pixel simultaneously in every horizontal scanning, a second signal line drive circuit for applying the first scanning pulse from each one end of the lower signal line to each pixel simultaneously in every horizontal scanning, a scanning line drive circuit for applying a second scanning pulse from each one end of the scanning line to each pixel sequentially in every horizontal scanning, and a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the first and second signal line drive circuits on the basis of an input image signal,</li><li>in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, and the point intersecting with the x-th signal line from the drive end of the scanning lines to be a terminal end, the voltage Vgs (x, t) of the second scanning pulse applied to the pixel positioned at the terminal end is,</li><li>supposing the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the voltage of the second scanning pulse at the drive end of the right and left scanning lines to be changed from Vgn to Vgn+1 at time t=0, the operation reference voltage at this time to be Vref, the output resistance of the first and second scanning line drive circuits to be Rgs, and setting <maths id="math0044"><math display="inline"><mrow><mtext>x=M</mtext></mrow></math><img file="EP0875879A1_D0044.tif" /></maths>,</li><li>given as<maths id="math0045"><math display="block"><mrow><msup><mrow><mtext>Vgs(x, t) =(Vgn-Vgn+1)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·c·x· Rgs)}+Vgn+1-Vref</mtext></mrow></math><img file="EP0875879A1_D0045.tif" /></maths></li><li>or further supposing the point intersecting with the y-th scanning line from the drive end of the upper and lower signal lines to be virtual terminal end, or divided terminal end, the voltage Vsw (y, t) of the first scanning pulse applied to the pixel positioned at the virtual terminal end or terminal end is,</li><li>supposing the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance per pixel of the signal line including the liquid crystal cell to be cs, the operation reference voltage of VH and VL to be Vref1 and Vref2, respectively, the voltage of the first scanning pulse at drive end of the upper and lower signal lines to be VH and VL alternately repeated at every TH, the output resistance of the first and second signal line drive circuits to be Rsw, and setting <maths id="math0046"><math display="inline"><mrow><mtext>y=N</mtext></mrow></math><img file="EP0875879A1_D0046.tif" /></maths>,</li><li>given, if changing over to VH at t=0, as<maths id="math0047"><math display="block"><mrow><msup><mrow><mtext>Vsw(y, t) =(VH-Vref1)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y· cs·Rsw)}]</mtext></mrow></math><img file="EP0875879A1_D0047.tif" /></maths></li><li>or, if changing over to VL at t=0, as<maths id="math0048"><math display="block"><mrow><msup><mrow><mtext>Vsw(y, t) =(VL-Vref2)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y· cs·Rsw)}]</mtext></mrow></math><img file="EP0875879A1_D0048.tif" /></maths></li></ul>

0051The invention as set forth in claim 16 relates to a driving method of liquid crystal display device for driving a liquid crystal panel having plural signal lines and plural scanning lines disposed in a matrix, and disposing pixels at intersections of the signal lines and scanning lines, where the optical state of the liquid crystal cells of said pixels is changed by applying a voltage to the scanning lines and signal lines corresponding to the pixels, comprising: <ul id="ul0018" list-style="none" compact="compact"><li>a signal line drive circuit for applying a first scanning pulse from each one end of the signal lines to each pixel simultaneously in every horizontal scanning, a scanning line drive circuit for applying a second scanning pulse from each one end of the scanning line to each pixel sequentially in every horizontal scanning, and a control circuit for instructing generation of the first scanning pulse in synchronism with the second scanning pulse to the signal line drive circuits on the basis of an input image signal,</li><li>in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, and the point intersecting with the x-th signal line from the drive end of the scanning lines to be a terminal end, the voltage Vgs (x, t) of the second scanning pulse applied to the pixel positioned at the terminal end is,</li><li>supposing the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the voltage of the second scanning pulse at the drive end of right and left scanning lines to be changed from Vgn to Vgn+1 at time t=0, the operation reference voltage at this time to be Vref, the output resistance of the first and second scanning line drive circuits to be Rgs, and setting <maths id="math0049"><math display="inline"><mrow><mtext>x=M</mtext></mrow></math><img file="EP0875879A1_D0049.tif" /></maths>,</li><li>given as<maths id="math0050"><math display="block"><mrow><msup><mrow><mtext>Vgs(x, t) =(Vgn-Vgn+1)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·c·x· Rgs)}+Vgn+1-Vref</mtext></mrow></math><img file="EP0875879A1_D0050.tif" /></maths></li><li>or further supposing the point intersecting with the y-th scanning line from the drive end of the signal lines to be terminal end, the voltage Vss(y, t) of the first scanning pulse applied to the pixel positioned at the terminal end is,</li><li>supposing the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance per pixel of the signal line including the liquid crystal cell to be cs, the operation reference voltage of VH and VL to be Vref1 and Vref2, respectively, the voltage of the first scanning pulse at drive end of signal lines to be VH and VL alternately repeated at every TH, the output resistance of the signal line drive circuits to be Rss, and setting <maths id="math0051"><math display="inline"><mrow><mtext>y=2N</mtext></mrow></math><img file="EP0875879A1_D0051.tif" /></maths>,</li><li>given, if changing over to VH at t=0, as<maths id="math0052"><math display="block"><mrow><msup><mrow><mtext>Vss(y, t) =(VH-Vref1)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y· cs·Rss)}]</mtext></mrow></math><img file="EP0875879A1_D0052.tif" /></maths></li><li>or, if changing over to VL at t=0, as<maths id="math0053"><math display="block"><mrow><msup><mrow><mtext>Vss(y, t) =(VL-Vref2)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4rs·cs·y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·y· cs·Rss)}]</mtext></mrow></math><img file="EP0875879A1_D0053.tif" /></maths></li></ul>

0052The invention as set forth in claim 17 relates to any one of claims 1, 2, 5 to 8 of the invention, in which the output resistance Rgw of the first and second scanning line drive circuits is, supposing the number of the scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the pulse width of the second scanning pulse to be TH, the ratio of effective voltage of pixel at virtual terminal end or divided terminal end of the scanning lines to effective voltage of pixel at drive end of the scanning lines to be γ 1, the ON voltage of the liquid crystal panel at drive end of scanning lines to be Vgon, the OFF voltage of the liquid crystal panel to be Vgoff, the delay time of the liquid crystal panel to be Tdpw, the operation reference voltage to be Vref, the threshold voltage of the liquid crystal panel to be Vpthw, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, to satisfy either<maths id="math0054"><img file="EP0875879A1_D0054.tif" /></maths> or<maths id="math0055"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtext>Rgw≦-π·Tdpw/(M·c·1nβw)-M·r/π</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>βw=(Vpthw-Vgon+Vref)/(Vgoff-Vgon)</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0055.tif" /></maths>

0053The invention as set forth in claim 18 relates to any one of claims 3, 4 or 12 of the invention, in which the output resistance Rgs of the scanning line drive circuits is, supposing the number of the scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of the signal lines to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the pulse width of the second scanning pulse to be TH, the ratio of effective voltage of pixel at terminal end of the scanning lines to effective voltage of pixel at drive end of the scanning lines to be γ 2, the ON voltage of the liquid crystal panel at drive end of scanning lines to be Vgon, the OFF voltage of the liquid crystal panel to be Vgoff, the delay time of the liquid crystal panel to be Tdps, the operation reference voltage to be Vref, the threshold voltage of the liquid crystal panel to be Vpths, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, to satisfy either<maths id="math0056"><img file="EP0875879A1_D0056.tif" /></maths> or<maths id="math0057"><math display="block"><mrow><mtext>Rgs≦-π·Tdps/(2M·c·1nβs)-2M·r/π</mtext></mrow></math><img file="EP0875879A1_D0057.tif" /></maths>    where, <maths id="math0058"><math display="inline"><mrow><mtext>βs=(Vpths-Vgon+Vref)/(Vgoff-Vgon)</mtext></mrow></math><img file="EP0875879A1_D0058.tif" /></maths>

0054The invention as set forth in claim 19 relates to any one of claims 2, 3, 4, 5, 7 and 8 of the invention, in which the output resistance Rsw of the first and second signal line drive circuits is, supposing the number of the scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of the signal lines in the vertical direction to be M, the ratio of effective voltage of pixel at virtual terminal end or divided terminal end of the signal lines to effective voltage of pixel at drive end to be γ 1s, the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance to be cs, the width of the first scanning pulse to be TH, the number of scanning lines to be 2N, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, to satisfy either<maths id="math0059"><img file="EP0875879A1_D0059.tif" /></maths> or<maths id="math0060"><math display="block"><mrow><mtext>Rsw≦-2N·rs/π-π·TH/[2N·cs·ln{(1-γls)/2}]</mtext></mrow></math><img file="EP0875879A1_D0060.tif" /></maths>

0055The invention as set forth in claim 20 relates to any one of claims 1, 6 and 12 of the invention, in which the output resistance Rss of the signal line drive circuits is, supposing the number of the scanning lines in the horizontal direction of the liquid crystal panel to be 2N, the number of the signal lines in the vertical direction to be M, the ratio of effective voltage of pixel at terminal end of the signal lines to effective voltage of pixel at drive end to be γ 2s, the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance to be cs, the width of the first scanning pulse to be TH, the number of scanning lines to be 2N, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, to satisfy either<maths id="math0061"><img file="EP0875879A1_D0061.tif" /></maths> or<maths id="math0062"><math display="block"><mrow><mtext>Rss≦-4N·rs/π-π·TH/[4N·cs·ln{(1-γ2s)/2}]</mtext></mrow></math><img file="EP0875879A1_D0062.tif" /></maths>

0056The invention as set forth in claim 21 relates to any one of claims 1, 2, 5 to 8 of the invention, in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the pulse width of the second scanning pulse to be TH, and its repeating period TV to be 2N · TH, and assuming the first and second scanning line drive circuits to apply the scanning line driving voltages V(+), V(-) alternately in every period TV to the selected scanning line, to apply the operation reference voltage Vref to the non-selected scanning lines, and to apply VL to the signal lines when the V(+) is applied or VH when the V(-) is applied, the individual scanning line driving currents of the first and second scanning line drive circuits is    <maths id="math0063"><math display="inline"><mrow><mtext>2N · Mc (V(+)-VL)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0063.tif" /></maths> when V(+) is applied, or    <maths id="math0064"><math display="inline"><mrow><mtext>2N · Mc(V(-)-VH)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0064.tif" /></maths> when V(-) is applied.

0057The invention as set forth in claim 22 relates to any one of claims 3, 4 and 12 of the invention, in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the pulse width of the second scanning pulse to be TH, and its repeating period TV to be 2N · TH, and assuming the scanning line drive circuit to apply V(+), V(-) alternately in every period TV to the selected scanning line, to apply the operation reference voltage Vref to the non-selected scanning lines, and to apply VL to the signal lines when the V(+) is applied or VH when the V(-) is applied, the scanning line driving current of the scanning line drive circuit is    <maths id="math0065"><math display="inline"><mrow><mtext>4N · M · c (V(+)-VL)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0065.tif" /></maths> when V(+) is applied, or    <maths id="math0066"><math display="inline"><mrow><mtext>4N · M · c (V(-) -VH)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0066.tif" /></maths> when V(-) is applied.

0058The invention as set forth in claim 23 relates to any one of claims 1, 2, 5 to 8 of the invention, in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the pulse width of the second scanning pulse to be TH, and its repeating period TV to be 2N · TH, and assuming to apply the scanning line driving voltage Vgon in every period TV to the selected scanning line, to apply Vg(+) and Vg(-) alternately, and to apply Vgoff to the non-selected scanning lines, the individual scanning line driving currents of the first and second scanning line drive circuits are    <maths id="math0067"><math display="inline"><mrow><mtext>2N · Mc (Vgon-Vgoff)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0067.tif" /></maths> when Vgon is applied,    <maths id="math0068"><math display="inline"><mrow><mtext>N · Mc (Vg(+)-Vgoff)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0068.tif" /></maths> when Vg(+) is applied, or    <maths id="math0069"><math display="inline"><mrow><mtext>N · Mc (Vg(-)-Vgoff)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0069.tif" /></maths> when Vg(-) is applied.

0059The invention as set forth in claim 24 relates to any one of claims 3, 4 and 12 of the invention, in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of the scanning lines including the liquid crystal cell to be c, the pulse width of the second scanning pulse to be TH, and its repeating period TV to be 2N · TH, and assuming to apply the scanning line driving voltage Vgon in every period TV to the selected scanning line, to apply Vg(+) and Vg(-) alternately, and to apply Vgoff to the non-selected scanning lines, the scanning line driving current of the scanning line drive circuit is    <maths id="math0070"><math display="inline"><mrow><mtext>4N · Mc (Vgon-Vgoff)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0070.tif" /></maths> when Vgon is applied,    <maths id="math0071"><math display="inline"><mrow><mtext>2N · Mc (Vg(+)-Vgoff)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0071.tif" /></maths> when Vg(+) is applied, or    <maths id="math0072"><math display="inline"><mrow><mtext>2N · Mc (Vg(-)-Vgoff)/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0072.tif" /></maths> when Vg(-) is applied.

0060The invention as set forth in claim 25 relates to any one of claims 2 to 5, 7 and 8 of the invention, in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance per pixel of the signal lines including the liquid crystal cell to be cs, the operation reference voltage of VH to be Vref1, the operation reference voltage of VL to be Vref2, the width of the first scanning pulse to be TH, and the repeating period TV of the second scanning pulse to be 2N·TH, the first and second signal line drive circuits apply signal line driving voltages VH, VL alternately in every pulse width TH of the first scanning pulse to the signal lines, and the individual signal line driving currents of the first and second signal line drive circuits is    <maths id="math0073"><math display="inline"><mrow><msub><mrow><mtext>8(VH-Vref1)N</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext> · M · cs/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0073.tif" /></maths> when VH is applied, or    <maths id="math0074"><math display="inline"><mrow><msub><mrow><mtext>8(VL-Vref2)N</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext> · M · cs/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0074.tif" /></maths> when VL is applied.

0061The invention as set forth in claim 26 relates to any one of claims 1, 6 and 12 of the invention, in which supposing the number of the scanning lines in the horizontal direction of the liquid crystal cell to be 2N, the number of the signal lines in the vertical direction to be M, the wiring resistance per pixel of the signal lines to be rs, the pixel capacitance per pixel of the signal lines including the liquid crystal cell to be cs, the width of the first scanning pulse to be TH, the operation reference voltage of VH to be Vref1, the operation reference voltage of VL to be Vref2, and the repeating period TV of the second scanning pulse to be 2N · TH, the signal line drive circuit applies signal line driving voltages VH, VL alternately in every pulse width TH of the first scanning pulse to the signal lines, and the signal line driving current of the signal line drive circuit is    <maths id="math0075"><math display="inline"><mrow><msup><mrow><mtext>16(VH-Vref1)N</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext> · M · cs/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0075.tif" /></maths> when VH is applied, or    <maths id="math0076"><math display="inline"><mrow><msup><mrow><mtext>16(VL-Vref2)N</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext> · M · cs/(π · TV)</mtext></mrow></math><img file="EP0875879A1_D0076.tif" /></maths> when VL is applied.

0062The invention as set forth in claim 27 relates to any one of claims 1, 2, 5 to 8 of the invention, in which the delay time of the second scanning pulse of the central pixel of the scanning line by both-end driving for driving simultaneously from the right and left scanning lines is 1/4 or less of the delay time of the second pulse of the terminal end pixel in one-end driving by either first or second scanning line drive circuit only, when the output resistance of the scanning line drive circuit used in both-end driving is 1/2 or less of the output resistance of the scanning line drive circuit used in one-end driving.

0063The invention as set forth in claim 28 relates to any one of claims 2 to 5, 7 and 8 of the invention, the delay time of the first scanning pulse of the central pixel of the signal line by both-end driving for driving simultaneously from the upper and lower signal lines is 1/4 or less of the delay time of the first pulse of the terminal end pixel in one-end driving by either first or second signal line drive circuit only, and the output resistance of the signal line drive circuit used in both-end driving is 1/2 or less of the output resistance of the signal line drive circuit used in one-end driving.

0064The invention as set forth in claim 29 relates to any one of claims 1, 2, 5 to 8 of the invention, in which the liquid crystal panel is characterized by forming drive terminals at both ends of each scanning line, or forming or disposing a drive circuit outside of the image display region of the liquid crystal panel.

0065The invention as set forth in claim 30 relates to any one of claims 2 to 5, 7 and 8 of the invention, in which the liquid crystal panel is characterized by forming drive terminals at both ends of each signal line, or forming or disposing a drive circuit outside of the image display region of the liquid crystal panel.

0066The invention as set forth in claim 31 relates to any one of claims 2, 5, 7 and 8 of the invention, in which the liquid crystal panel is characterized by forming drive terminals at both ends of each scanning line and each signal line, or forming or disposing a drive circuit outside of the image display region of the liquid crystal panel.

0067The invention as set forth in claim 32 relates to claim 13 or 14 of the invention, in which the ratio γ gw(x) of effective voltage of pixels at virtual terminal end or divided terminal end x-th apart from the drive end of the scanning line to effective voltage of pixel at drive end of the scanning line is, supposing the wiring resistance per pixel of the scanning line to be r, the pixel capacitance per pixel of scanning line including the liquid crystal cell to be c, the second scanning pulse at drive end of scanning line to be changed over to selected voltage at time t=0, the operation reference voltage to be Vref, the width of the first scanning pulse to be TH, the output resistance of the first and second scanning line drive circuits to be Rgw, <maths id="math0077"><math display="inline"><mrow><mtext>x=M/2</mtext></mrow></math><img file="EP0875879A1_D0077.tif" /></maths>, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, given as:<maths id="math0078"><img file="EP0875879A1_D0078.tif" /></maths>

0068The invention as se forth in claim 33 relates to claim 16 of the invention, in which the ratio γ gs(x) of effective voltage of pixel at terminal end x-th apart from the drive end of the scanning line to effective voltage of pixel at drive end of the scanning line is, supposing the wiring resistance per pixel of the scanning line to be r, the pixel capacitance per pixel of scanning line including the liquid crystal cell to be c, the second scanning pulse at drive end of scanning line to be changed over to selected voltage at time t=0, the operation reference voltage to be Vref, the width of the first scanning pulse to be TH, the output resistance of the scanning line drive circuit to be Rgs, <maths id="math0079"><math display="inline"><mrow><mtext>x=M</mtext></mrow></math><img file="EP0875879A1_D0079.tif" /></maths>, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, given as:<maths id="math0080"><img file="EP0875879A1_D0080.tif" /></maths>

0069The invention as set forth in claim 34 relates to claim 13 or 15 of the invention, in which the ratio γ sw(y) of effective voltage of pixel at virtual terminal end or divided terminal end y-th apart from the drive end of the signal line to effective voltage of pixel at drive end of the signal line is, supposing the wiring resistance per pixel of the signal line to be rs, the pixel capacitance per pixel of signal line including the liquid crystal cell to be cs, the width of the first scanning pulse to be TH, the voltage of the first scanning pulse at drive end of signal line to be changed between VH and VL at every TH, the operation reference voltage at VH and VL to be Vref1 and Vref2, respectively, the output resistance of the first and second signal line drive circuits to be Rsw, <maths id="math0081"><math display="inline"><mrow><mtext>y=N</mtext></mrow></math><img file="EP0875879A1_D0081.tif" /></maths>, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, given as:<maths id="math0082"><img file="EP0875879A1_D0082.tif" /></maths>    or<maths id="math0083"><math display="block"><mrow><msup><mrow><mtext>γsw(y) =[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH/(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·rs·cs+2π·y·cs·Rsw)}]</mtext></mrow></math><img file="EP0875879A1_D0083.tif" /></maths>

0070The invention as set forth in claim 35 relates to claim 16 of the invention, in which the ratio γ ss(y) of effective voltage of pixel at terminal end y-th apart from the drive end of the signal line to effective voltage of pixel at drive end of the signal line is, supposing the wiring resistance per pixel of the signal line to be rs, the pixel capacitance per pixel of signal line including the liquid crystal cell to be cs, the width of the first scanning pulse to be TH, the voltage of the first scanning pulse at drive end of signal line to be changed between VH and VL at every TH, the operation reference voltage at VH and VL to be Vref1 and Vref2, respectively, the output resistance of the signal line drive circuit to be Rss, <maths id="math0084"><math display="inline"><mrow><mtext>y=2N</mtext></mrow></math><img file="EP0875879A1_D0084.tif" /></maths>, and the ratio of amplitude of scanning line driving voltage to amplitude of signal line driving voltage to be a, given as:<maths id="math0085"><img file="EP0875879A1_D0085.tif" /></maths> or<maths id="math0086"><math display="block"><mrow><msup><mrow><mtext>γss(y) =[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH/(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·rs·cs+2π·y·cs-Rss)}]</mtext></mrow></math><img file="EP0875879A1_D0086.tif" /></maths>

0071The invention as set forth in claim 36 relates to claim 13 or 14 of the invention, in which the threshold voltage Vpthw of the liquid crystal panel in the scanning line both-end driving is, supposing the delay time of the liquid crystal panel to be Tdpw, the ON voltage and OFF voltage of the liquid crystal panel to be Vgon and Vgoff, respectively, the x-th position from the drive end of the scanning lines to be virtual terminal end or divided terminal end, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of scanning lines including the liquid crystal cell to be c, the second scanning pulse at the drive end of scanning lines to be changed over from Vgoff to Vgon at time t=0, the operation reference voltage at this time to be Vref, the output resistance of the first and second scanning line drive circuits to be Rgw, and <maths id="math0087"><math display="inline"><mrow><mtext>x = M/2</mtext></mrow></math><img file="EP0875879A1_D0087.tif" /></maths>, given as:<maths id="math0088"><math display="block"><mrow><msup><mrow><mtext>Vpthw =(Vgoff-Vgon)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·Tdpw/(4x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·r·c+2π·x· c·Rgw)}+Vgon-Vref</mtext></mrow></math><img file="EP0875879A1_D0088.tif" /></maths>

0072The invention as set forth in claim 37 relates to claim 15 and 16 of the invention, in which the threshold voltage Vpths of the liquid crystal panel in the scanning line one-end driving is, supposing the delay time of the liquid crystal panel to be Tdps, the ON voltage and OFF voltage of the liquid crystal panel to be Vgon and Vgoff, respectively, the x-th position from the drive end of the scanning lines to be virtual terminal end or divided terminal end, the wiring resistance per pixel of the scanning lines to be r, the pixel capacitance per pixel of scanning lines including the liquid crystal cell to be c, the second scanning pulse at the drive end of scanning lines to be changed over from Vgoff to Vgon at time t=0, the operation reference voltage at this time to be Vref, the output resistance of the scanning line drive circuit to be Rgs, and <maths id="math0089"><math display="inline"><mrow><mtext>x = M/2</mtext></mrow></math><img file="EP0875879A1_D0089.tif" /></maths>, given as:<maths id="math0090"><math display="block"><mrow><msup><mrow><mtext>Vpths =(Vgoff-Vgon)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·Tdpw/(4x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·r·c+2π·x· c·Rgs)}+Vgon-Vref</mtext></mrow></math><img file="EP0875879A1_D0090.tif" /></maths>

0073Thus, according to the constitution and method described in claims 1 to 11, 13 to 15, 17, 19, 21, 23, 25 to 30, 32, 34, and 36, in scanning line both-end simultaneous driving, even in the condition of same driving current, the delay time of the scanning line driving voltage can be set smaller as compared with scanning line one-end driving. At the same time, in signal line both-end simultaneous driving, even in the condition of same driving current, the delay time of the signal line driving voltage can be set smaller as compared with signal line one-end driving. Therefore, the lateral luminance error, longitudinal luminance error, and crosstalk are extremely small, and display unevenness is less obvious. Moreover, by drive analysis on the basis of a simple equivalent circuit, design parameters such as lateral luminance error, longitudinal luminance error, pixel driving voltage, scanning line driving voltage, driving current of scanning line drive circuit can be obtained, an optimum design of drive circuit is obtained efficiently and at low cost, and the picture quality of the liquid crystal display device can be enhanced dramatically.

0074In particular, according to the liquid crystal display device of claims 9, 10 and 11, scanning lines and signal lines in scanning line both-end simultaneous driving or signal line both-end simultaneous driving can be expressed in an extremely simple equivalent circuit. Therefore, development of drive circuit and design of drive circuit are very easy.

0075According to the driving method of claims 12 to 15, in scanning line both-end simultaneous driving and signal line one-end driving, or scanning line one-end driving and signal line both-end simultaneous driving, or scanning line both-end simultaneous driving and signal line both-end simultaneous driving, the scanning line driving voltage and signal line driving voltage at arbitrary pixels in the liquid crystal panel can be obtained accurately.

0076According to the liquid crystal display device of claims 17 and 19, in scanning line both-end simultaneous driving and signal line both-end simultaneous driving, the optimum range of output resistance of the drive circuit can be obtained accurately.

0077According to the liquid crystal display device of claims 21, 23 and 25, in scanning line both-end simultaneous driving and signal line both-end simultaneous driving, the driving current of the drive circuit of scanning lines and signal lines can be obtained accurately.

0078According to the driving method of claims 32 and 34, in scanning line both-end simultaneous driving and signal line one-end driving, or scanning line one-end driving and signal line both-end simultaneous driving, or scanning line both-end simultaneous driving and signal line both-end simultaneous driving, the ratio of effective voltage of an arbitrary pixel in the liquid crystal panel to effective voltage of pixel at drive end of scanning lines, or the ratio of effective value of signal line driving voltage of an arbitrary pixel of the liquid crystal panel to effective value of signal line driving voltage of pixel at drive end of signal lines can be determined.

0079According to the driving method of claim 36, the range of threshold voltage of the liquid crystal panel in scanning line both-end simultaneous driving can be determined.

0080According to the driving method of claim 37, the range of threshold voltage of the liquid crystal panel in scanning line one-end driving can be determined.

0081According to the constitution and method described in claims 12, 16, 18, 20, 22, 24, 26, 33, 35 and 37, in scanning line one-end driving or signal line one-end driving, the output resistance of drive circuit, driving current of drive circuit, threshold voltage of liquid crystal panel, and driving voltage of arbitrary pixel can be obtained accurately.

Brief Description of the Drawings

0082Fig. 1 is a block diagram of a liquid crystal display device in embodiment 1 of the invention.

0083Fig. 2 is an equivalent circuit diagram of a liquid crystal panel in embodiment 1 of the invention.

0084Fig. 3 is an output waveform and its timing chart in scanning line both-end simultaneous driving method in the liquid crystal display device in embodiment 1 of the invention.

0085Fig. 4 is a distributed parameter circuit diagram of scanning lines of liquid crystal panel in scanning line both-end simultaneous driving.

0086Fig. 5 is a distributed parameter circuit diagram for analyzing transient response of driving voltage of scanning lines of liquid crystal panel.

0087Fig. 6 is a circuit diagram of replacing the distributed parameter circuit of scanning lines of liquid crystal panel with a lumped parameter circuit.

0088Fig. 7 is a general block diagram of a liquid crystal panel dividing signal lines into upper and lower halves.

0089Fig. 8 is a general block diagram of a liquid crystal panel having scanning line both-end driving terminals, with signal line driving terminals disposed at the upper end.

0090Fig. 9 is a general block diagram of a liquid crystal panel having scanning line both-end driving terminals, with signal line driving terminals disposed at the lower end.

0091Fig. 10 is an explanatory diagram showing transient response of scanning line driving voltage of a 17-inch liquid crystal panel.

0092Fig. 11 is an explanatory diagram showing lateral luminance error in one-end driving in a 12.1-inch liquid crystal display device.

0093Fig. 12 is an explanatory diagram showing lateral luminance error in a 17-inch liquid crystal display device.

0094Fig. 13 is an explanatory diagram showing lateral luminance error in a 20- or 24.4-inch liquid crystal display device.

0095Fig. 14 is a block diagram of a liquid crystal display device in embodiment 2 of the invention.

0096Fig. 15 is a block diagram of a liquid crystal display device in embodiment 3 of the invention.

0097Fig. 16 is a block diagram of a liquid crystal display device in embodiment 4 of the invention.

0098Fig. 17 is a block diagram of pixels in a TFT liquid crystal panel in embodiment 4.

0099Fig. 18 is a driving voltage waveform and timing chart of scanning lines in embodiment 4.

0100Fig. 19 is an explanatory diagram showing the relation of counter electrode voltage and signal line driving voltage in embodiment 4.

0101Fig. 20 is an equivalent circuit diagram of a liquid crystal panel in embodiment 4.

0102Fig. 21 is a distributed parameter circuit diagram in scanning line driving in embodiment 4.

0103Fig. 22 is a characteristic diagram of relation of gate voltage and drain current of TFT.

0104Fig. 23 is an explanatory diagram of switching characteristic of TFT at scanning line driving voltage.

0105Fig. 24 is a block diagram of pixel in embodiment 5 of the invention.

0106Fig. 25 is a block diagram of pixel in embodiment 6 of the invention.

0107Fig. 26 is a block diagram of pixel in TFT liquid crystal panel in embodiment 6.

0108Fig. 27 is a driving voltage waveform and timing chart of scanning lines in embodiment 6.

0109Fig. 28 is a block diagram of a liquid crystal display device in embodiment 7.

0110Fig. 29 is a block diagram of a liquid crystal display device in embodiment 8.

0111Fig. 30 is a diagram showing waveforms of signal line driving voltage and operation reference voltage.

0112Fig. 31 is an equivalent circuit diagram of signal lines for obtaining a signal line driving current.

0113Fig. 32 is a diagram showing an example of signal line driving voltage waveform.

0114Fig. 33 is a block diagram of a liquid crystal display device in embodiment 9.

0115Fig. 34 is a block diagram of a liquid crystal display device in embodiment 10.

0116Fig. 35 is a block diagram of a liquid crystal display device in embodiment 11.

0117Fig. 36 is a block diagram of a liquid crystal display device in embodiment 12.

0118Fig. 37 is a block diagram of a liquid crystal display device in embodiment 13.

0119Fig. 38 is a block diagram of a liquid crystal panel having drive terminals at both ends of signal lines, and having drive terminals at left end of scanning lines.

0120Fig. 39 is a block diagram of a liquid crystal panel having drive terminals at both ends of signal lines, and having drive terminals at right end of scanning lines.

0121Fig. 40 is a block diagram of a liquid crystal display device in embodiment 14.

0122Fig. 41 is a block diagram of a liquid crystal display device in embodiment 15.

0123Fig. 42 is a block diagram of a liquid crystal panel having drive terminals at both ends of scanning lines and signal lines.

0124Fig. 43 is a block diagram of a liquid crystal display device in embodiment 16.

0125Fig. 44 is a block diagram of a liquid crystal panel having drive terminals at the ends of right and left scanning lines and at both ends of signal lines.

0126Fig. 45 is a block diagram of a liquid crystal display device in embodiment 17.

0127Fig. 46 is a block diagram of a liquid crystal panel having drive terminals in right and left scanning lines and upper and lower signal lines.

0128Fig. 47 is a block diagram of a liquid crystal display device in embodiment 18.

0129Fig. 48 is a block diagram of a liquid crystal panel having drive terminals in right and left scanning lines.

0130Fig. 49 is a block diagram of a liquid crystal display device in a prior art.

0131Fig. 50 is a driving waveform diagram of pixels in the liquid crystal display device in the prior art.

0132Fig. 51 is an equivalent circuit diagram of scanning line driving in the liquid crystal display device in the prior art.

Description of the Preferred Embodiments

0133Referring now to the drawings, the liquid crystal display device and its driving method in the preferred embodiments of the invention are described in detail below. The same parts as in the constitution of the conventional liquid crystal display device are identified with same reference numerals and their description is omitted.

(Embodiment 1)

0134A liquid crystal display device in embodiment 1 of the invention is described below while referring to the block diagram in Fig. 1. This liquid crystal display device comprises a liquid crystal panel 14, an upper signal line drive circuit 15, a lower signal line drive circuit 16, a scanning line left drive circuit 17A, a control circuit 18, and a drive power source circuit 19, and also contains a scanning line right drive circuit 17B.

0135In this liquid crystal panel 14, a second scanning pulse is supplied sequentially from both ends of the scanning line 12 simultaneously through the scanning line left drive circuit 17A and scanning line right drive circuit 17B. In the explanation to follow, the liquid crystal panel 14 is explained as a simple matrix type liquid crystal panel.

0136The driving voltage is generated by combination of voltages V(+), V(-), VH, VL, and Vref in formula (1). Fig. 3 is a output waveform diagram in the case of simultaneous driving of both ends of scanning line by the scanning line left drive circuit 17A and scanning line right drive circuit 17B. The output sections of the right and left scanning line drive circuits 17A and 17B are composed of three analog switches. The output resistance of the three analog switches is supposed to be Ro. The driving voltages V(+), V(-) of the scanning line left drive circuit 17A and scanning line right drive circuit 17B, and the operation reference voltage Vref are exactly same as shown in Fig. 27, and are issued at the same timing, but the scanning directions of the scanning line left drive circuit 17A and scanning line right drive circuit 17B are opposite to each other.

0137To eliminate this problem, the scanning line left drive circuit 17A scans sequentially from address X1 to XN and from address XN+1 to X2N, and scanning line right drive circuit 17B scans in the reverse direction, from address XN to X1 and from address X2N to XN+1. For this purpose, the control circuit 18 issues a control signal, and controls the scanning in the forward direction of the scanning line left drive circuit 17A and the scanning in the reverse direction of the scanning line right drive circuit 17B, so that the above function is achieved.

0138This function is realized by providing the shift register in the scanning line drive circuit with a bidirectional property. This function is provided in the majority of LSIs for scanning line drive circuit usable on market. Therefore, for the purpose of scanning line both-end simultaneous driving of the invention, it is not necessary to develop new LSI exclusively for the scanning line drive circuit. That is, in Fig. 1, the scanning line left drive circuit 17A and scanning line right drive circuit 17B are distinguished, but identical LSIs for scanning line drive circuit can be used.

0139Terminal block diagrams of the liquid crystal panel 14 of the embodiment having terminals for scanning line both-end simultaneous driving are shown in Figs. 7,8 and 9. Fig. 7 shows the liquid crystal panel 14A of upper and lower divided driving, and Figs. 8 and 9 show the patterns of scanning lines and signal lines of the liquid crystal panel not divided into upper and lower halves. The liquid crystal panel 14C in Fig. 9 is a configuration of signal line drive terminals turning upside down the liquid crystal panel 14B. The left side scanning line drive terminal 21a and the right side scanning line drive terminal 21b mutually have mirror symmetrical patterns. Therefore, the mask pattern of the drive terminal of the liquid crystal panel for scanning line one-end driving may be inverted and added to the terminal end of the scanning line 12, and the mask pattern can be changed easily. The lateral length of the liquid crystal panel is slightly extended as the drive terminal is added, but it is not a problem substantially in the large-screen liquid crystal panel with a diagonal length of 17 inches or the like. The liquid crystal panels 14A, 14B in Figs. 7, 8, 9 can be manufactured nearly at the same cost as the conventional liquid crystal panel with scanning line one-end driving.

0140The output waveform and timing of the scanning line drive circuit in scanning line both-end driving are shown in Fig. 3. By upper and lower divided driving, scanning is started simultaneously from scanning lines of address X1 and address XN+1. As shown in Fig. 3, by the scanning line left drive circuit 17A and scanning line right drive circuit 17B, the scanning lines 12 are driven at same driving voltage simultaneously from both ends in every horizontal scanning. Accordingly, the scanning line both-end simultaneous driving can be expressed by the distributed parameter circuit composed of wiring resistance r and pixel capacitance c of scanning lines 12 as shown in Fig. 4 (A). In Fig. 4 (A), the analog switch incorporated in the right and left scanning line drive circuits is SW, the output resistance is Ro, and the equivalent circuit of the right and left scanning line drive circuits is enclosed by dotted lines. In Fig. 4, notation of Y(1), ..., Y(M/2) denotes the intersection of an arbitrary scanning line 12 and upper and lower signal lines 10, 11, and, for example, Y(1) represents the intersection of scanning line 12 and signal line 10 of address Y1.

0141The distributed parameter circuit shown in Fig. 4 (A) is symmetrical on both sides of the middle (center) of the scanning line. Therefore, in scanning line both-end simultaneous driving, the terminal voltage of the pixel capacitance c is symmetrical on both sides of the middle as shown in Fig. 4 (A), and the capacitor of the pixel capacitance c is charged so that Y(1) and Y(M) may be at the same potential, and that Y(2) and Y(M-1) may be at the same potential, being symmetrical on both sides of the center of the scanning line 12 sequentially from both ends.

0142In this way, on the basis of the middle of the scanning line 12, the potentials of pixel capacitance c at right and left sides of the scanning line 12 are symmetrical, and therefore the potentials of Y(M/2) and <maths id="math0091"><math display="inline"><mrow><mtext>Y(M/2+1)</mtext></mrow></math><img file="EP0875879A1_D0091.tif" /></maths> in Fig. 4 (A) are exactly identical, and whether these two terminals are short-circuited or separated, no change occurs in the electric characteristic, and hence it may be regarded as an independent circuit. That is, as shown in Fig. 4 (B), (C), separating the scanning line both-end simultaneous driving by dividing the scanning line 12 into two from the center, it may be regarded as one-side driving by the scanning line left drive circuit 17A and scanning line right drive circuit 17B.

0143In this embodiment, the middle of the scanning line is defined as the virtual terminal end. That is, in Fig. 4 (A), Y(M/Y2) and <maths id="math0092"><math display="inline"><mrow><mtext>Y(M/2+1)</mtext></mrow></math><img file="EP0875879A1_D0092.tif" /></maths> are virtual terminal ends. For two terminals with identical potential electrical characteristics are not changed if they are separated or short-circuited, and hence they may be handled as being independent electrically. Electrically, Fig. 4 (B) and (C) are completely identical with circuit diagrams of one-end driving.

0144When the driving voltage at terminal end can be determined accurately, great effects are expected in optimum design of drive circuit, development of new driving method, and improvement of picture quality in liquid crystal display device. In the embodiment, as shown in Fig. 4 (B), (C), by analyzing the scanning line drive as transient phenomenon in the distributed parameter circuit, a driving voltage at virtual terminal end may be obtained. Fig. 5 is a distributed parameter circuit diagram composed of x sets of resistance r and capacitor with capacitance c. In this distributed parameter circuit, when the voltage V (x, t) at terminal end is determined in the condition of open circuit at terminal end and output resistance Ro=0 of drive circuit, formula (8) is obtained. The deriving method of this formula (8) is mentioned in a college lecture course "Elementary electric circuit: transient nonlinear formulas" edited by Japan Society of Telecommunications (pp. 82-90).<maths id="math0093" num="(8)"><math display="block"><mrow><mtext>V(x,t) =V-4V/π·</mtext><apply><sum /><lowlimit><mtext>k=1</mtext></lowlimit><uplimit><mtext>∞</mtext></uplimit><mrow><msup><mrow><mtext>1(2k-1)·exp[-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·(2k-1)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c· x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>)]·sin[(2k-1)·π/2]</mtext></mrow></apply></mrow></math><img file="EP0875879A1_D0093.tif" /></maths> where the term of sin function is <maths id="math0094"><math display="inline"><mrow><mtext>sin {(2k-1) · π/2}</mtext></mrow></math><img file="EP0875879A1_D0094.tif" /></maths>, which is +1 or - 1 depending on the value of k. In this condition, when the degree of k increases, the value of cumulative sum of second and larger degree is a smaller value than the value of the first degree. Therefore, the operation of cumulative sum is small in error if determined only at k=1. Hence, concerning the driving voltage of terminal end of scanning line 12, the value of formula (8) is determined assuming k=1. That is, it is approximated by<maths id="math0095"><math display="block"><mrow><msup><mrow><mtext>V(x,t)=V-[(4V/π)·exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>)}]·α</mtext></mrow></math><img file="EP0875879A1_D0095.tif" /></maths> (where α is a constant).

0145By putting the initial condition in this formula, α is obtained. That is, if t=0 then V (M, 0)=0, and hence from<maths id="math0096"><math display="block"><mrow><mtext>V(M, 0)=V-(4V/π)α=0</mtext></mrow></math><img file="EP0875879A1_D0096.tif" /></maths><maths id="math0097"><math display="inline"><mrow><mtext>α=π/4</mtext></mrow></math><img file="EP0875879A1_D0097.tif" /></maths> is obtained. The formula is transformed into formula (9).<maths id="math0098" num="(9)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msup><mrow><mtext>V(x, t)=V[1-exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>)}]</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>where, x=M</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0098.tif" /></maths> From this formula (9), the equivalent circuit of scanning line 12 in this embodiment is derived. That is, formula (9) expresses an applied voltage of the capacitor in a series circuit composed of resistance of <maths id="math0099"><math display="inline"><mrow><mtext>(2/ π ) · r · x</mtext></mrow></math><img file="EP0875879A1_D0099.tif" /></maths> and capacitance of <maths id="math0100"><math display="inline"><mrow><mtext>(2/ π ) · c · x</mtext></mrow></math><img file="EP0875879A1_D0100.tif" /></maths>. Therefore, the distributed parameter circuit in Fig. 4 (A) can be approximated by a lumped parameter circuit, and the scanning lines 12 can be expressed in an RC series circuit. To apply the distributed parameter circuit in scanning line both-end simultaneous driving in Fig. 4 into formula (9), it is enough to suppose <maths id="math0101"><math display="inline"><mrow><mtext>x=M/2</mtext></mrow></math><img file="EP0875879A1_D0101.tif" /></maths>. Accordingly, as shown in Fig. 6, scanning line both-end simultaneous driving can be expressed by an equivalent circuit composed of resistance of <maths id="math0102"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0102.tif" /></maths> and capacitance of <maths id="math0103"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0103.tif" /></maths>.

0146Incidentally, it can be also expressed in formula (9) if separating the virtual terminal end point of the scanning line is separated physically into right scanning line and left scanning line, and driving the right and left scanning lines simultaneously. That is, in electrical characteristics, it is regarded the same to the scanning line physically divided into two and drive each one end simultaneously at a same driving voltage and to drive simultaneously from both ends of one scanning line, and therefore the scanning line both-end driving includes these two cases hereinafter. It is same for the signal lines.

0147Now we determine the voltage at the terminal end of the scanning line, when the scanning line driving voltage is changed from Vgn to Vgn+1. Supposing the operation reference voltage to be Vref, in an equivalent circuit composed of resistance of <maths id="math0104"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0104.tif" /></maths> and capacitance of <maths id="math0105"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0105.tif" /></maths> in Fig. 6, capacitance of <maths id="math0106"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0106.tif" /></maths> is not grounded, but is connected to Vref. Assuming the scanning line driving voltage to be changed from Vgn to Vgn+1 at t=0, the terminal end voltage, that is, the voltage V (x, t) at both ends of the capacitor is as shown in formula (9A).

0148Supposing <maths id="math0107"><math display="inline"><mrow><mtext>x=M/2</mtext></mrow></math><img file="EP0875879A1_D0107.tif" /></maths> in the case of scanning line both-end simultaneous driving, or    <maths id="math0108"><math display="inline"><mrow><mtext>x=M</mtext></mrow></math><img file="EP0875879A1_D0108.tif" /></maths> in the case of scanning line one-end driving,<maths id="math0109" num="(9A)"><math display="block"><mrow><msup><mrow><mtext>V(x, t)=(Vgn-Vgn+1)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·Ro· x·c}+Vgn+1-Vref</mtext></mrow></math><img file="EP0875879A1_D0109.tif" /></maths> Herein, using the symbols shown in Fig. 3, in the case of V(+), since <maths id="math0110"><math display="inline"><mrow><mtext>Vgn+1 = V(+)</mtext></mrow></math><img file="EP0875879A1_D0110.tif" /></maths>, <maths id="math0111"><math display="inline"><mrow><mtext>Vgn = Vref</mtext></mrow></math><img file="EP0875879A1_D0111.tif" /></maths>, <maths id="math0112"><math display="inline"><mrow><mtext>V(+) -Vref = V</mtext></mrow></math><img file="EP0875879A1_D0112.tif" /></maths>, hence formula (10) is obtained.

0149Supposing <maths id="math0113"><math display="inline"><mrow><mtext>x=M/2</mtext></mrow></math><img file="EP0875879A1_D0113.tif" /></maths> in the case of scanning line both-end simultaneous driving, or    <maths id="math0114"><math display="inline"><mrow><mtext>x=M</mtext></mrow></math><img file="EP0875879A1_D0114.tif" /></maths> in the case of scanning line one-end driving,<maths id="math0115" num="(10)"><math display="block"><mrow><msup><mrow><mtext>V(x, t)=V[1-exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·Ro·x·c})</mtext></mrow></math><img file="EP0875879A1_D0115.tif" /></maths> Similarly, it is also obtained as for V(-). Actually, V(+) and V(-) do not satisfy formula (1), and there is an error of <maths id="math0116"><math display="inline"><mrow><mtext>V(+) + V(-) - 2 Vref = Δ</mtext></mrow></math><img file="EP0875879A1_D0116.tif" /></maths>, but it is ignored because it is very small as compared with V (0.1 V or less). Formula (9A) is applied when generalizing including the scanning line drive voltage of the TFT liquid crystal panel. Formula (10) is applied in the case of simple matrix type.

0150As for the conventional scanning line one-end driving, the driving voltage is obtained from formulas (9), (10), supposing <maths id="math0117"><math display="inline"><mrow><mtext>x=M</mtext></mrow></math><img file="EP0875879A1_D0117.tif" /></maths> in formula (8), and the scanning line 12 can be expressed by the RC series circuit composed of resistance of <maths id="math0118"><math display="inline"><mrow><mtext>(2/ π) · M · r</mtext></mrow></math><img file="EP0875879A1_D0118.tif" /></maths> and capacitance of <maths id="math0119"><math display="inline"><mrow><mtext>(2/ π) · M · c</mtext></mrow></math><img file="EP0875879A1_D0119.tif" /></maths>. The capacitance value and resistance value of the conventional equivalent circuit of scanning lines shown in Fig. 51 (B) are (π /2) times as shown in the equivalent circuit in Fig. 6, and it is understood why the result of the conventional analysis does not coincide with the measured value.

0151In scanning line one-end driving, the time constant of the 17-inch liquid crystal panel obtained from measurement of rise time of driving voltage at terminal end is 2.0 µs. The time constant of the 17-inch liquid crystal panel calculated from formula (10) is 1.99 µs. Considering the measuring error, the result of calculation by the equivalent circuit in Fig. 6 and the measured value coincide very well with each other.

0152In this embodiment, at the pixel 13 at terminal end or virtual terminal end of scanning line 12, the scanning line driving voltage is approximately shown in formula (10). At the same time, the scanning line driving voltage of the 17-inch liquid crystal panel at an arbitrary address x of the signal line obtained from formula (8) is determined by numerical calculation. In this case, the number of k of cumulative addition of formula (8) should be as large as possible, and the change of the term of sin function in a range of - 1 to +1 depending on the value of k must be incorporated into the operation. The result is shown in Fig. 10. In Fig. 10, the curve of M=640 × 3 denotes the delay time of scanning line both-end driving (rise characteristic of scanning pulse), and the curve of M=1280 × 3 expresses the delay time of driving voltage at terminal end of scanning line one-end driving. At the scanning lines 12 identical in the number of pixels, it is known that the delay time is smaller in both-end driving.

0153Thus, the time constant τ 1 in scanning line both-end simultaneous driving of an arbitrary scanning line 12 is <maths id="math0120"><math display="inline"><mrow><mtext>(M · r/ π) · (M · c/ π)</mtext></mrow></math><img file="EP0875879A1_D0120.tif" /></maths>, and the time constant τ 2 in scanning line one-end driving is <maths id="math0121"><math display="inline"><mrow><mtext>[(2M · r/ π) · (2M · c/ π)]</mtext></mrow></math><img file="EP0875879A1_D0121.tif" /></maths>. Approximately, τ 2/ τ 1 is 4, and the delay time of scanning line both-end simultaneous driving is found to be 1/4 that of scanning line one-end driving. This is extremely important in scanning line driving. The wiring resistance r of the liquid crystal panel 14 is always present, and the picture quality of the liquid crystal display device deteriorates due to occurrence of lateral luminance error. The larger the screen, the bigger the lateral luminance error. In the liquid crystal panel 14 of matrix composition, it is impossible to nullify the wiring resistance of scanning lines, and in this sense the scanning line driving method in the embodiment capable of decreasing the lateral luminance error is important.

0154Referring now to the equivalent circuit in Fig. 6, driving current in scanning line both-end simultaneous driving is analyzed. First, the scanning line driving current is determined. From formula (7), the individual scanning line driving currents of scanning line left drive circuit 17A and scanning line right drive circuit 17B in scanning line both-end simultaneous driving are as follows.<maths id="math0122" num="(11)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtext>As for V(+), 2N·M·c(V(+)-VL)/(π·TV)</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>As for V(-), 2N·M·c(V(-)-VH)/(π·TV)</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0122.tif" /></maths>

0155Similarly, the driving current of scanning line one-end driving can be determined, and the same value as in scanning line both-end simultaneous driving is obtained. However, the driving current of right and left scanning line drive circuits in scanning line both-end simultaneous driving is half that of scanning line one-end driving.

0156As mentioned above, the scanning line left drive circuit 17A and scanning line right drive circuit 17B are composed of same LSI, but the leak current of output circuit is extremely small. Accordingly, the driving current can be determined by measuring the current at input terminal of driving voltage of scanning line left drive circuit 17A and scanning line right drive circuit 17B. The current measured at the input terminal when driven at one side by detaching either one of scanning line left drive circuit 17A and scanning line right drive circuit 17B in Fig. 1, and the current measured at the input terminal when driven by scanning line both-end simultaneous driving were proved to be nearly equal. This is an evidence that the equivalent circuit used in this embodiment is adequate. Results of calculation of scanning line driving current in formula (11) are mentioned later

0157By the equivalent circuit in Fig. 6, the effective voltage Vecl of pixel 13 at drive end of scanning line 12, effective voltage Vecn of pixel 13 at virtual terminal end, and effective voltage Vecm of pixel 13 at terminal end in scanning line one-end driving are obtained in the same deriving method as in formulas (5) and (6), of which results are expressed in formula (12).<maths id="math0123"><img file="EP0875879A1_D0123.tif" /></maths>

0158The effective voltage ratio γ 1 at virtual terminal end and at drive end, and effective voltage ratio γ 2 at terminal end and at drive end in scanning line one-end driving are expressed in formula (13)<maths id="math0124" num="(13)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msup><mrow><mtext>γ1=Vecn/Vecl [1-1.5(M·r+π·Ro)·M·c/(π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH)·a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N -1)]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></mtd></mtr><mtr><mtd><mrow><msup><mrow><mtext>γ2=Vecm/Vecl [1-3(2M·r+π·Ro)·M·c/(π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH)·a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N -1)]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0124.tif" /></maths>

0159From formulas (12) and (13), the lateral luminance error in scanning line both-end simultaneous driving is known to be about 1/4 that of scanning line one-side driving, and the scanning line both-end driving method of the embodiment is proved to be excellent.

0160The lateral luminance error (expressed by effective voltage difference), effective voltage Ve, and voltage ratio γ determined in the condition of Ro=0 from formulas (12) and (13), and the scanning line driving current determined in the condition of <maths id="math0125"><math display="inline"><mrow><mtext>VH= -VL=2.1 V</mtext></mrow></math><img file="EP0875879A1_D0125.tif" /></maths> from formula (11) are explained below in the cases of scanning line both-end simultaneous driving and scanning line one-end driving.

0161In this case, the liquid crystal display device was calculated at the diagonal length of 12.1, 17, 20, and 24.2 inches.

(Calculation 2)

0162Hereinafter, figures in parentheses refer to the lateral luminance error in scanning line one-end driving. <ul id="ul0019" list-style="none"><li>(1) 12.1-inch liquid crystal display device <ul id="ul0020" list-style="none" compact="compact"><li>Lateral luminance error =(30.7mV)</li><li>One-end driving voltage ratio γ 2 =0.9899</li><li>Drive end voltage Vecl =2.82V</li><li>Scanning line driving current =0.9mA (measured value =1.0mA)</li><li>Condition (Mr/ π)(Mc/ π)=0.23 µS, TH=27.8 µS TV=8.34mS, N=300, M=800 × 3, a=14.5 V=30.5V, c=0.26pF, r=1.5 Ω, rs=4.5 Ω</li></ul></li><li>(2) 17-inch liquid crystal display device <ul id="ul0021" list-style="none" compact="compact"><li>Lateral luminance error =9.6mV (38.7mV)</li><li>Both-end driving voltage ratio γ 1 =0.9963</li><li>Drive end voltage Vecl =2.60V</li><li>One-end driving voltage ratio γ 2 =0.9851</li><li>Scanning line driving current =1.11mA (measured value =1.0mA)</li><li>Condition (Mr/ π)(Mc/ π)=0.426 µS, TH=28 µS TV=14.34mS, N=512, M=1280 × 3, a=15.5 V=32.5V, c=0.19pF, r=1.5 Ω, rs=4.5 Ω</li></ul></li><li>(3) 20-inch liquid crystal display device <ul id="ul0022" list-style="none" compact="compact"><li>Lateral luminance error =17.7mV (71.5mV)</li><li>Both-end driving voltage ratio γ 1 =0.9932</li><li>Drive end voltage Vecl =2.60V</li><li>One-end driving voltage ratio γ 2 =0.9725</li><li>Scanning line driving current =1.91mA</li><li>Condition (Mr/ π)(Mc/ π)=0.753 µS, TH=23.8 µS TV=14.34mS, N=600, M=1600 × 3, a=15.5 V=32.5V, c=0.215pF, r=1.5 Ω, rs=4.5 Ω</li></ul></li><li>(4) 24.2-inch liquid crystal display device <ul id="ul0023" list-style="none" compact="compact"><li>Lateral luminance error =21.6mV (87.4mV)</li><li>Both-end driving voltage ratio γ 1 =0.9917</li><li>Drive end voltage Vecl =2.60V</li><li>One-end driving voltage ratio γ 2 =0.9664</li><li>Scanning line driving current =2.31mA</li><li>Condition (Mr/ π)(Mc/ π)=0.911 µS, TH=23.8 µS</li><li>TV=14.34mS, N=600, M=1600 × 3, a=15.5</li><li>V=32.5V, c=0.26pF, r=1.5 Ω, rs=4.5 Ω</li></ul></li></ul>

0163It is shown from the calculation that the lateral luminance error can be ignored in the 17-inch liquid crystal display device. In the 17-inch liquid crystal display device in scanning line both-end simultaneous driving method, since the lateral luminance error cannot be distinguished visually, the result of calculation coincides very well with the measured value. In the 20- and 24.2-inch liquid crystal display devices, the lateral luminance error can be visually distinguished, but practically it may be considered to be free from problem. Thus, considering from the coincidence between the calculated value and visual observation, the equivalent circuit in Fig. 6 is known to be suited for analysis of scanning line drive. Moreover, in the 17-inch liquid crystal display device, lateral crosstalk in scanning line both-end simultaneous driving is confirmed to be extremely small as compared with scanning line one-end driving. Since the lateral crosstalk is caused by waveform distortion due to delay in scanning line driving voltage, the both-end driving of which delay time is about 1/4 of one-end driving is an extremely excellent method also for reducing the lateral crosstalk.

0164The lateral luminance error along the address of signal line calculated by formula (8) is shown in Figs. 11, 12 and 13. Fig. 11 shows the lateral luminance error in scanning line one-end driving determined in the condition of Ro=0 ohm in the 12.1-inch liquid crystal display device. Fig. 12, relating to the 17-inch liquid crystal display device, shows the lateral luminance error in scanning line both-end simultaneous driving determined in the condition of Ro=0 ohm, 600 ohms, and 1 kohm, and the lateral luminance error in scanning line one-end driving determined in the condition of Ro=0 ohm and 600 ohms. Fig. 13, relating to the 20- and 24.2-inch liquid crystal display devices, shows the lateral luminance error in scanning line both-end simultaneous driving determined in the condition of Ro=0 ohm. Herein, the output resistance Ro refers to the output resistance of an analog switch delivering an output of V(+) or V(-).

0165Fig. 12 more clearly proves the superiority of scanning line both-end simultaneous driving. Results of visual observation and results of driving analysis in Figs. 11 to 13 coincide very well with each other. In particular, in the case of a large liquid crystal panel such as 20 or 24.2 inches, it is obviously shows that the practical problem of lateral luminance error can be solved by employing the scanning line both-end simultaneous driving. Moreover, formula (8) agrees with the visual observation as the formula for expressing the driving voltage of an arbitrary pixel from the drive end to the terminal end or virtual terminal end, and hence the conformity of this formula is supported. Thus, accurate simulation of scanning line driving is realized.

0166In the above calculation 2, the output resistance Ro of the scanning line drive circuit was assumed to be 0. This is for the sake of simplicity of calculation, and the actual output resistance is not Ro=0. By formula (14) derived from formula (13), appropriate output resistance Rgw of both-end driving of scanning line drive circuit and output resistance Rgs of one-end driving can be determined.<maths id="math0126"><img file="EP0875879A1_D0126.tif" /></maths>

0167By using formula (14), an appropriate output resistance required in the scanning line drive circuit can be easily obtained. According to formula (14), in scanning line both-end simultaneous driving, in the condition of <maths id="math0127"><math display="inline"><mrow><mtext>γ 1= γ 2</mtext></mrow></math><img file="EP0875879A1_D0127.tif" /></maths>, the output resistance of scanning line drive circuit can be about 2 times that of scanning line one-end driving. Furthermore, ITO is often used to connect the drive circuit with the scanning line drive terminal. Since the ITO is high in specific resistance, the wiring resistance cannot be ignored. In formula (14) of the invention, the output resistance may be regarded as sum of wiring resistance of ITO and output resistance of drive circuit. Therefore, once the output resistance of the drive circuit is determined, an appropriate range of wiring resistance of ITO is obtained, so that the pattern design of liquid crystal panel may be appropriate and easy. Thus, the invention may be applied in a wide range.

0168Since the output resistance of the scanning line drive circuit can be increased, the chip size of the LSI for composing the scanning line drive circuit can be reduced, and the LSI cost can be lowered. The chip size of LSI is determined by the demanded output resistance, and the smaller the demanded output resistance, the larger is the chip size. Thus, in scanning line both-end simultaneous driving, since the chip size of the LSI for composing the scanning line drive circuit is reduced, the LSI cost is lower.

(Embodiment 2)

0169A liquid crystal display device in embodiment 2 of the invention is briefly described below. Fig. 14 is a block diagram of the liquid crystal display device of this embodiment. Same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In this liquid crystal display device, the signal line 9 of the liquid crystal display panel 14B is not divided into upper and lower halves, but the scanning line of the liquid crystal panel 14B is driven simultaneously at both ends. In such constitution, too, the same effects as in embodiment 1 are obtained.

(Embodiment 3)

0170A liquid crystal display device in embodiment 3 of the invention is briefly described below. Fig. 15 is a block diagram of the liquid crystal display device of this embodiment. Same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In this liquid crystal display device, the signal line drive terminal of the liquid crystal panel 14 in Fig. 14 is disposed upside down, and the scanning line of the liquid crystal panel 14C is driven simultaneously at both ends. In such constitution, too, the same effects as in embodiment 1 are obtained.

(Embodiment 4)

0171A liquid crystal display device in embodiment 4 of the invention is briefly described below. Fig. 16 is a block diagram of the liquid crystal display device of this embodiment. Same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. Each pixel 13 of the liquid crystal panel 14D in this embodiment is composed of a switching element of thin film transistor (TFT), and a liquid crystal cell. This liquid crystal panel 14D has undivided signal lines 9 and (2N+1) scanning lines 12, and both ends of the scanning lines 12 are driven simultaneously.

0172In Fig. 16, an element P at the intersection of a signal line 9 and a scanning line 12 includes a TFT which drives the liquid crystal cell. A counter electrode 23 indicated by broken line is an electrode for applying an operation reference voltage of the TFT type liquid crystal panel 14D, and a terminal 23a is provided in a part thereof. From a drive power source circuit 19B, a voltage Vcom is applied to the counter electrode 23 through the terminal 23a.

0173The element P (also called pixel 13) is expressed in an equivalent circuit including a TFT as shown in Fig. 17. The pixel 13 is expressed by circuit element, such as TFT, liquid crystal cell (capacitance Cls), capacitance Cgd between drain and gate of TFT, capacitance Ccs between TFT source and liquid crystal cell, capacitance Cgs between source and gate of TFT, capacitance Ccg between TFT gate and liquid crystal cell, and capacitance Cst between TFT drain and pre-stage gate.

0174The capacitance Cls is a capacitance of the liquid crystal cell formed between the TFT drain electrode and counter electrode. The source electrode is connected to the signal line 9, and the gate electrode is connected to the scanning line 12. In thus constituted pixel 13, supposing the capacitance between the scanning line 12 and counter electrode 23 to be c, the capacitance c is expressed in formula (17).<maths id="math0128" num="(17)"><math display="block"><mrow><mtext>c=Ccg+Cst·Cls/(Cst+Cls)+Cgd·Cls/(Cgd+Cls) +CGS·Ccs/(Cgd+Ccs)</mtext></mrow></math><img file="EP0875879A1_D0128.tif" /></maths>

0175In Fig. 16, the pixel 13 at the intersection of XN scanning line 12 and YN signal line 9 is expressed as (XN, YN). The drain of the TFT at (XN, YN) is coupled to the gate of the TFT at (XN-1, YN) capacitance Cst. The TFT thus constituted is called the TFT of pre-stage capacitive coupling type. Fig. 16 shows the constitution of the TFT type liquid crystal panel 14C of this pre-stage capacitive coupling type. In other TFT, the drain of the TFT at (XN, YN) is coupled to the gate of the TFT at (XN+1, YN) capacitance Cst. This is called the TFT of post-stage capacitive coupling type.

0176In such TFT type liquid crystal panel of pre-stage capacitive coupling type, the scanning line driving voltage waveform and its timing are shown in Fig. 18. In the diagram, Vgon is the driving voltage for turning on the TFT, and Vgoff is the driving voltage for turning off the TFT. Meanwhile; Vg+ and Vg- are compensation voltages. The scanning line left drive circuit 17A scans sequentially from scanning line 12 of address X1 to address X2N, and simultaneously the scanning line right drive circuit 17B scans sequentially from address X2N to address X1. As explained in embodiment 1, since the configuration of the scanning line drive circuit is reverse, the driving voltage is delivered in the same direction from upper to lower side in Fig. 18.

0177Fig. 19 shows an example of relation between voltage Vcom of the counter electrode 23 (hereinafter called Vref) and the output of the upper signal line drive circuit 15. As shown in the diagram, the output of the upper signal line drive circuit 15 is inverted in polarity in every time of one horizontal scanning line on the basis of Vref. Herein, since the upper signal line driving voltage is VH and VL, the relation of <maths id="math0129"><math display="inline"><mrow><mtext>VH - Vref = Vref - VL</mtext></mrow></math><img file="EP0875879A1_D0129.tif" /></maths> is established. To simplify the explanation, the upper signal line drive circuit 15 in Fig. 16 is identical with reference numeral 15 in Fig. 49. Actually, a DA (digital-to-analog) converter is often built in the signal line circuit of the TFT type liquid crystal panel, and the output circuit is regarded as an analog amplifier. Since it is indifferent to explanation of the invention, it is assumed to be a signal line drive circuit of binary output.

0178Signal lines 9 and scanning lines 12 are coupled by distributed capacitance Ccs, Cgs, Ccg. Since the average of the driving voltage of the signal lines 9 can be regarded as Vref as shown in Fig. 19, the equivalent circuit for the scanning line driving of the liquid crystal panel 14D in Fig. 16 can be shown as Fig. 20 with the capacitance c of the pixel 13 formed between the scanning line and counter electrode as indicated in formula (18).

0179As shown in the equivalent circuit in Fig. 20, since the liquid crystal panel 14D can be expressed by the distributed parameter circuit in which an arbitrary scanning line 12 is composed of element capacitance c and wiring resistance r of scanning line, as shown in Fig. 4 relating to embodiment 1, by dividing into two sections from the virtual terminal end, it can be expressed by the distributed parameter circuit for driving each at one end. This is shown in Fig. 21.

0180In Fig. 21, the output resistances of right and left scanning line drive circuits 17, 20 can be expressed by SW1 to SW4 and the resistance Ro connected in series to each SW. Herein, SW1 to SW4 are analog switches, the resistance Ro is the output resistance of the scanning line drive circuit, and Vref is the operation reference voltage. Vref is a voltage applied to the counter electrode. From Fig. 21, in scanning line driving of the capacitive coupled TFT liquid crystal panel 14D, too, the scanning line 12 can be expressed as a series circuit of resistance <maths id="math0130"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0130.tif" /></maths> and capacitance <maths id="math0131"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0131.tif" /></maths>. That is, the output circuits of scanning line drive circuits 17 and 20 are composed of four analog switches, and all output resistances are supposed to be Ro.

0181The switching characteristic of the TFT is shown in Fig. 22. The switching characteristiCcan be expressed by the relation of gate voltage Vg and drain current Id. Although the TFT operates as a switching element, its switching characteristic is considerably inferior to an ideal switch. As shown in Fig. 22, the gate voltage at which the TFT is completely turned on is supposed to be the threshold voltage Vth. When the scanning line driving voltage exceeds Vth, the TFT is turned on, and the signal line driving voltage is applied to the liquid crystal cell of capacitance Cls.

0182Therefore, at terminal end of the scanning line 12, due to delay by the wiring resistance r from the drive end and pixel capacitance c, the ON time of the TFT becomes shorter, and between the drive end and terminal end, the ON time of the TFT is different as shown in Fig. 23. In Fig. 23, the timing when the scanning line driving voltage at terminal end reaches Vth is expressed as Tgd. This Tgd is the delay time of the gate voltage of the TFT at the terminal end, and is determined from the above formula (9A). At the drive end, for the time of one horizontal scanning period TH the TFT is ON, and the liquid crystal capacitance Cls is charged up to the signal line driving voltage. By contrast, at the terminal end, the liquid crystal capacitance Cls must be charged in the ON time of (TH-Tgd).

0183When the drain current Id of the TFT is sufficiently large, and the output resistance Rd of the TFT is small, the liquid crystal capacitance can be charged up to the signal line driving voltage within the time of (TH-Tgd). However, when the screen size of the liquid crystal panel is large, and the pixel composition is at high definition such as (1600 × 3) × 1200, the horizontal scanning time TH becomes shorter, and the Tgd is larger. Therefore, in the pixel at the terminal end, as compared with the time constant Cls × Rd determined by the liquid crystal capacitance Cls and output resistance Rd of TFT, the value of (TH-Tgd) is smaller, and the liquid crystal capacitance cannot be charged up to the signal line driving voltage.

0184Therefore, in the scanning line one-end driving, as described in embodiment 1, the brightness differs slightly from the drive end to the terminal end, and a lateral luminance error occurs. In the TFT type liquid crystal display device by scanning line one-end driving with the screen size of 20 inches in the composition of (1600 × 3) × 1200 pixels, the charging time of the liquid crystal capacitance Cls in the condition of TH=17 µs, Tgd=6 µs is estimated around 14 µs. In this case, a visually distinguishable lateral luminance error occurs, and display unevenness occurs.

0185However, by employing the scanning line both-end simultaneous driving of the invention, since the delay time becomes 1/4, Tgd is 6 µs/4 = 1.5 µs, and the lateral luminance error is at an ignorable level. In this case, display unevenness does not occur. Moreover, since the delay time is 1/4, lateral crosstalk due to waveform distortion is smaller than in scanning line one-end driving. Incidentally, if the liquid crystal display device is composed of post-stage capacitive coupled TFT type liquid crystal panel, exactly the same effects are obtained.

0186Next, in the capacitive coupled TFT type liquid crystal panel, the scanning line driving voltage, threshold voltage, delay time, and output resistance of scanning line drive circuit are numerically expressed, assuming the operation of the TFT to be an ideal switch.

0187The scanning line driving voltage is changed over from Vgoff to Vgon at the timing of turning on the TFT disposed in each pixel. The time when the scanning line driving voltage is changed over from Vgoff to Vgon is supposed to be t, and using the pixel capacitance c of the scanning line in formula (17), and supposing the output resistance of the scanning line drive circuit to be Rgw in both-end driving or Rgs in one-end driving, and <maths id="math0132"><math display="inline"><mrow><mtext>Vgn = Vgoff</mtext></mrow></math><img file="EP0875879A1_D0132.tif" /></maths>, <maths id="math0133"><math display="inline"><mrow><mtext>Vgn+1 = Vgon</mtext></mrow></math><img file="EP0875879A1_D0133.tif" /></maths>, formula (18) can be derived from formula (9A).

0188In scanning line both-end simultaneous driving, assuming <maths id="math0134"><math display="inline"><mrow><mtext>x≦M/2</mtext></mrow></math><img file="EP0875879A1_D0134.tif" /></maths>,<maths id="math0135"><math display="block"><mrow><msup><mrow><mtext>Vgw(x,t) =(Vgoff-Vgon)·exp{π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·c·x ·Rgw)}]+Vgon-Vref</mtext></mrow></math><img file="EP0875879A1_D0135.tif" /></maths>

0189In scanning line one-end driving, assuming x≦M<maths id="math0136" num="(18)"><math display="block"><mrow><msup><mrow><mtext>Vgs(x,t) =(Vgoff-Vgon)·exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4r·c·x</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+2π·c·x ·Rgs)}]+Vgon-Vref</mtext></mrow></math><img file="EP0875879A1_D0136.tif" /></maths>

0190Supposing the output resistance to be 0, the delay time of scanning line both-end simultaneous driving is 1/4 that of one-end driving, same as in the simple matrix type liquid crystal panel.

0191In formula (9A), putting <maths id="math0137"><math display="inline"><mrow><mtext>Vgn = Vgon</mtext></mrow></math><img file="EP0875879A1_D0137.tif" /></maths>, <maths id="math0138"><math display="inline"><mrow><mtext>Vgn+1 = Vg+</mtext></mrow></math><img file="EP0875879A1_D0138.tif" /></maths>, the voltage of Vg+ at virtual terminal end or terminal end can be determined (so is Vg-). Herein, suppose <maths id="math0139"><math display="inline"><mrow><mtext>Vg+ = Vg(+)</mtext></mrow></math><img file="EP0875879A1_D0139.tif" /></maths>, and <maths id="math0140"><math display="inline"><mrow><mtext>Vg- = Vg(-)</mtext></mrow></math><img file="EP0875879A1_D0140.tif" /></maths>. Since formula (11) expressing the scanning line driving current cannot be applied to the capacitive coupled TFT type, supposing the scanning line driving currents of the outputs Vgon, Vg(+), Vg(-) of the right and left scanning line drive circuits to be I gw(g), I gw(+), I gw(-), formula (11A) applicable to the TFT type is obtained on the basis of the method of deriving formula (11) as follows.<maths id="math0141" num="(11A)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtext>Igw(g)=(2N/TV)(M·c/π)(Vgon-Vgoff)</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>Igw(+)=(N/TV)(M·c/π)(Vg(+)-Vgoff)</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>Igw(-)=(N/TV)(M·c/π)(Vg(-)-Vgoff)</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0141.tif" /></maths>

0192In scanning line one-end driving, the scanning line driving current of each voltage is 2 times that of formula (11A).

0193As mentioned above, if the threshold voltage of the TFT of each pixel is identical, the time for the TFT of each pixel to reach the threshold voltage varies due to delay depending on the wiring resistance and pixel capacitance, and therefore the required gate ON voltage of each pixel differs. Therefore, hereinafter, the voltage at which the liquid crystal panel displays the image appropriately is defined to be the ON voltage Vgon of the liquid crystal panel, and the voltage not displaying completely is the OFF voltage Vgoff of the liquid crystal panel. Further, in formula (18), the driving voltage at <maths id="math0142"><math display="inline"><mrow><mtext>x=M/2</mtext></mrow></math><img file="EP0875879A1_D0142.tif" /></maths>, <maths id="math0143"><math display="inline"><mrow><mtext>t=Tdpw</mtext></mrow></math><img file="EP0875879A1_D0143.tif" /></maths> is supposed to be threshold voltage Vpthw of the liquid crystal panel and Tdpw to be the delay time of the liquid crystal panel in scanning line both-end simultaneous driving, and the driving voltage at <maths id="math0144"><math display="inline"><mrow><mtext>x=M</mtext></mrow></math><img file="EP0875879A1_D0144.tif" /></maths>, <maths id="math0145"><math display="inline"><mrow><mtext>t=Tdps</mtext></mrow></math><img file="EP0875879A1_D0145.tif" /></maths> is supposed to be threshold voltage Vpths of the liquid crystal panel and Tdps to be the delay time of the liquid crystal panel in one-end driving. Hence, it is known that the threshold voltage of the liquid crystal panel should satisfy formula (19). That is,

0194In scanning line both-end simultaneous driving,<maths id="math0146"><math display="block"><mrow><msup><mrow><mtext>Vpthw=(Vgoff-Vgon)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·Tdpw/(M</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·r·c+π· M·c·Rgw)}+Vgon-Vref</mtext></mrow></math><img file="EP0875879A1_D0146.tif" /></maths>

0195In scanning line one-end driving,<maths id="math0147" num="(19)"><math display="block"><mrow><msup><mrow><mtext>Vpths=(Vgoff-Vgon)exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·Tdps/(4M</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·r·c+ 2π·M·c·Rgs)}+Vgon-Vref</mtext></mrow></math><img file="EP0875879A1_D0147.tif" /></maths>

0196If Vgon, Vgoff, Vpths, Vpthw are known, the delay time of the liquid crystal panel can be determined in formula (20).

0197In scanning line both-end simultaneous driving,<maths id="math0148"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msup><mrow><mtext>Tdpw=-1nβw·(M</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·r·c+π·M·c·Rgw)/π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></mtd></mtr><mtr><mtd><mrow><mtext>βw=(Vpthw-Vgon+Vref)/(Vgoff-Vgon)</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0148.tif" /></maths>

0198In scanning line one-end driving,<maths id="math0149" num="(20)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msub><mrow><mtext>Tdps=-1nβs·(4M</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msup><mrow><mtext>·r·c+2π·M·c·Rgw)/π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></mtd></mtr><mtr><mtd><mrow><mtext>βs=(Vpths-Vgon+Vref)/(Vgoff-Vgon)</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0149.tif" /></maths>

0199As known from formula (19), in scanning line both-end simultaneous driving, since the margin of threshold voltage of the liquid crystal panel is wider than in scanning line one-end driving, lateral luminance error is less likely to occur. When the ON voltage of the liquid crystal panel is more than the threshold voltage of the liquid crystal panel, no lateral luminance error occurs, and therefore the scanning line both-end simultaneous driving is more effective when used in the TFT type liquid crystal panel than in the simple matrix type.

0200Moreover, when the delay time of the liquid crystal panel is determined, a more appropriate output resistance range of the scanning line drive circuit can be determined from formula (19) and given by formula (21). Herein, Rgw and Rgs refer to the output resistance of the analog switch for delivering Vgon of the scanning line drive circuit.<maths id="math0150" num="(21)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtext>Rgw≦-π·Tdpw/(M·c·lnβw)-M·r/π</mtext></mrow></mtd></mtr><mtr><mtd><mrow><mtext>Rgs≦-π·Tdps/(2M·c·lnβs)-2M·r/π</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0875879A1_D0150.tif" /></maths>

0201By using the formulas (18) to (21) of the invention, design and driving analysis of the capacitive coupled TFT type liquid crystal display device are accurate and easy, and the margin of the design value can be predicted from the comparison between the measured value and calculated value. Thus, according to the embodiment, same as in the case of Fig. 1, even by using the capacitive coupled TFT type liquid crystal panel, the liquid crystal display device which is small in lateral luminance error and lateral crosstalk, free from display unevenness, and high in display quality is realized. It can be similarly applied to the liquid crystal panel in which the drive circuit of signal lines and scanning lines are formed or disposed outside of the image display region of the liquid crystal panel.

0202Also, same as in embodiment 1, driving can be analyzed by expressing the scanning line 12 by a series circuit composed of resistance of <maths id="math0151"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0151.tif" /></maths> and a capacitance of <maths id="math0152"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0152.tif" /></maths> in scanning line both-end simultaneous driving, or expressing the scanning line 12 by a series circuit composed of resistance of <maths id="math0153"><math display="inline"><mrow><mtext>2M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0153.tif" /></maths> and a capacitance of <maths id="math0154"><math display="inline"><mrow><mtext>2M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0154.tif" /></maths> in scanning line one-end driving.

(Embodiment 5)

0203A liquid crystal display device in embodiment 5 of the invention is described below. Fig. 24 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 and Fig. 16 are identified with same reference numerals, and their explanation is omitted. The signal line drive terminal of the liquid crystal panel 14D in Fig. 16 is disposed upside down, and the scanning line of the liquid crystal panel 14E is driven simultaneously at both ends. In such constitution, too, the same effects as in embodiment 4 are obtained.

(Embodiment 6)

0204A liquid crystal display device in embodiment 6 of the invention is briefly described below. Fig. 25 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In the liquid crystal panel 14F in the embodiment, each pixel 13 (element P) is composed of TFT which is not coupled capacitively and liquid crystal cell. The liquid crystal panel 14 has non-divided signal lines 9 and 2N scanning lines 12, and both ends of scanning lines are driven simultaneously.

0205The others are same as shown in Fig. 16, and same effects as in embodiment 4 are obtained. An equivalent circuit of pixel 13 is shown in Fig. 26. As shown in the diagram, the TFT is not coupled capacitively, and it is the constitution omitting the coupling capacitance Cst from the composition in Fig. 17. Therefore, the pixel capacitance c is expressed in formula (22).<maths id="math0155" num="(22)"><math display="block"><mrow><mtext>c=Ccg+Cgd·Cls/(Cgd+Cls)+Cgs·Ccs/(Cgs+Ccs)</mtext></mrow></math><img file="EP0875879A1_D0155.tif" /></maths>

0206An example of output waveform of scanning line drive circuits 17A, 17B in Fig. 25 is shown in Fig. 27. In the case of TFT type liquid crystal panel not coupled capacitively, too, the scanning line 12 can be expressed by a series circuit composed of resistance of <maths id="math0156"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0156.tif" /></maths> and a capacitance of <maths id="math0157"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0157.tif" /></maths> in scanning line both-end simultaneous driving, and the scanning line 12 can be expressed by a series circuit composed of resistance of <maths id="math0158"><math display="inline"><mrow><mtext>2M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0158.tif" /></maths> and a capacitance of <maths id="math0159"><math display="inline"><mrow><mtext>2M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0159.tif" /></maths> in scanning line one-end driving. Therefore, driving analysis can be done in the same manner as in embodiment 4, and same effects as in embodiment 4 are obtained, and all of formulas (18) to (21) can be applied similarly.

(Embodiment 7)

0207A liquid crystal display device in embodiment 7 of the invention is described below. Fig. 28 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 and Fig. 25 are identified with same reference numerals, and their explanation is omitted. The signal line drive terminal of the liquid crystal panel 14F in Fig. 25 is disposed upside down, and the scanning line of the liquid crystal panel 14G is driven simultaneously at both ends. In such constitution, too, the same effects as in embodiment 6 are obtained.

(Embodiment 8)

0208A liquid crystal display device in embodiment 8 of the invention is described below. Fig. 29 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In Fig. 29, in the simple matrix type liquid crystal panel 14H, the scanning line 12 is driven at one end, and the signal line 9 is driven simultaneously from both ends without dividing into two. The embodiment is applied to the liquid crystal display device longitudinally long in the screen composition.

0209The terminal structure of the liquid crystal panel 14H of the embodiment having terminals for signal line both-end simultaneous driving is shown in Figs. 38 and 39. Same reference numerals as in Fig. 7 are used, and the explanation is omitted. Fig. 39 shows a terminal structure of the liquid crystal panel 14I in which the scanning line drive terminal is disposed opposite against the liquid crystal panel 14H. The terminal structure of the liquid crystal panels 14J, 14L described later is same as in Fig. 38, and the terminal structure of liquid crystal panels 14K, 14M is same as in Fig. 39. In Fig. 38 and Fig. 39, the block diagrams of drive terminals are shown, but the scanning lines and signal lines may be formed or disposed outside of the image display region of the liquid crystal panel.

0210The signal line, same as the scanning line, may be regarded as a distributed parameter circuit composed of wiring resistance and pixel capacitance, and in signal line both-end simultaneous driving, the signal line driving voltage can be determined from formula (8). The signal line driving voltage is as shown in Fig. 50, and the signal line driving voltage is supposed to be changed over from VL to VH, or from VH to VL, at drive end at t=0. The operation reference voltage of VH is supposed to be Vref1, and the operation reference voltage of VL to be Vref2. In the simple matrix type liquid crystal panel, the relation is <maths id="math0160"><math display="inline"><mrow><mtext>Vref1 = Vref2</mtext></mrow></math><img file="EP0875879A1_D0160.tif" /></maths>, but in driving of TFT type liquid crystal panel, the operation reference voltage may be changed over at every horizontal scanning time. Supposing the output resistance of the signal line drive circuit to be Rsw, the number of scanning lines to be 2N, the wiring resistance per pixel of signal line to be rs, and the capacitance per pixel of signal line to be cs, the signal line driving voltage of the y-th pixel from the drive end of the signal line in the vertical direction is expressed in formula (23) which is derived from formula (9), assuming the y-th pixel to be virtual terminal end or divided terminal end. Formula (23) is derived from the fact shown in the following. When the voltage +V is applied at t=0 to the RC series circuit previously charged with -V, the charging voltage of C is expressed by <maths id="math0161"><math display="inline"><mrow><mtext>V · [1-2exp(-t/CR)]</mtext></mrow></math><img file="EP0875879A1_D0161.tif" /></maths>.

0211In the case of signal line both-end simultaneous driving, up to <maths id="math0162"><math display="inline"><mrow><mtext>y=N</mtext></mrow></math><img file="EP0875879A1_D0162.tif" /></maths>,

0212When changed over to VH at t=0, Vsw (y, t) is<maths id="math0163"><math display="block"><mrow><msup><mrow><mtext>(VH-Vref1)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·rs·cs+2π·y·cs· Rsw)}]</mtext></mrow></math><img file="EP0875879A1_D0163.tif" /></maths>

0213When changed over to VL at t=0, Vsw (y, t) is<maths id="math0164" num="(23)"><math display="block"><mrow><msup><mrow><mtext>(VL-Vref2)[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·t/(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·rs·cs+2π·y·cs· Rsw)}]</mtext></mrow></math><img file="EP0875879A1_D0164.tif" /></maths>

0214The signal line driving voltage of signal line one-end driving is up to <maths id="math0165"><math display="inline"><mrow><mtext>y=2N</mtext></mrow></math><img file="EP0875879A1_D0165.tif" /></maths>, and Rsw may be replaced by the output resistance Rss of the signal line drive circuit of signal line one-end driving. Formula (23) may be applied also to signal line both-end simultaneous driving of the TFT type liquid crystal panel. In the case of simple matrix type liquid crystal panel, it is general to keep the relation of <maths id="math0166"><math display="inline"><mrow><mtext>Vref1 = Vref2</mtext></mrow></math><img file="EP0875879A1_D0166.tif" /></maths>.

0215From formula (23), provided the output resistance is 0, it is known that the signal line can be driven at the delay time of 1/4 of signal line one-end driving in the signal line both-end simultaneous driving same as in scanning line both-end simultaneous driving, and the longitudinal luminance error and longitudinal crosstalk can be decreased extremely.

0216An example of waveform of signal line driving voltage and operation reference voltage is shown in Fig. 30. When the pixels at odd-number scanning lines are displayed in white, pixels at even-number scanning lines in black, or vice versa, on the screen, the signal line driving current is nearly maximum, and the waveform of signal line driving voltage and operation reference voltage becomes as shown in Fig. 30 in all signal lines. In this case, the equivalent circuit of the signal line 9 is, as shown in Fig. 31, expressed by applying the signal line driving voltage to one end and operation reference voltage to other end of the capacitor <maths id="math0167"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0167.tif" /></maths>, and hence formula (24) is obtained in the upper and lower signal line drive circuits in signal line both-end simultaneous driving.

0217When VH is applied, the signal line driving current Isw(+) is<maths id="math0168"><math display="block"><mrow><mtext>Isw(+)=2(VH-Vref1)·(2N/TV)(2N·M·cs/π)</mtext><mspace linebreak="newline" /><msub><mrow><mtext> =8(VH-Vref1)·N</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>·M·cs/(π·TV)</mtext></mrow></math><img file="EP0875879A1_D0168.tif" /></maths>

0218When VL is applied, the signal line driving current I ss(-) is<maths id="math0169" num="(24)"><math display="block"><mrow><msup><mrow><mtext>Isw(-)=-8(VL-Vref2)N</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·M·cs/(π·TV)</mtext></mrow></math><img file="EP0875879A1_D0169.tif" /></maths>

0219Formulas (23) and (24) can be applied not only to the simple matrix type liquid crystal panel, but also to the TFT type liquid crystal panel. In signal line one-end driving, since the equivalent circuit of signal lines can be expressed by the capacitor of <maths id="math0170"><math display="inline"><mrow><mtext>4N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0170.tif" /></maths>, the signal line driving currents Iss (+) and Iss (-) are 2 times that of formula (24). Incidentally, the pixel capacitance cs of signal line is same value as the pixel capacitance c of scanning line in simple matrix type, but in the liquid crystal panel of active matrix type such as TFT type liquid crystal panel, it is different from the pixel capacitance cs of scanning line.

0220The effective voltage at the y-th pixel from the drive end of the signal line is derived by the same method as in embodiment 1. Fig. 32 shows an example of signal line driving voltage waveform. At the terminal end, as shown in the diagram, the waveform is distorted by the wiring resistance and pixel capacitance. To obtain an effective voltage of pixel connected to the signal line, integration may be operated from t=0 to TH as shown below so as to have the time dependence shown in formula (23) in V/a of the term of <maths id="math0171"><math display="inline"><mrow><msub><mrow><mtext>(N-1) · (V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>/N</mtext></mrow></math><img file="EP0875879A1_D0171.tif" /></maths> in formula (3). That is,<maths id="math0172"><img file="EP0875879A1_D0172.tif" /></maths> Hence, the effective value of pixel at terminal end of signal line is<maths id="math0173" num="(25)"><math display="block"><mrow><msup><mrow><mtext>Vecns=[{V+V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N} +{(N-1)·(V/a)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>/N}{1-2RL·CL/TH}]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></math><img file="EP0875879A1_D0173.tif" /></maths> Therefore, the effective voltage ratio <maths id="math0174"><math display="inline"><mrow><mtext>γ s = Vecns/Vecl</mtext></mrow></math><img file="EP0875879A1_D0174.tif" /></maths> is given in formula (25A)<maths id="math0175" num="(25A)"><math display="block"><mrow><msup><mrow><mtext>γs=[1-(2RL·CL/TH)·N/(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N-1)}]</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></math><img file="EP0875879A1_D0175.tif" /></maths>

0221Accordingly, in signal line both-end simultaneous driving, assuming the pixel at the intersection of the y-th scanning line from the drive end of signal line to be the virtual terminal end or divided terminal end, the ratio of effective voltage of pixel disposed at the virtual terminal end or divided terminal end to effective voltage of pixel at drive end of signal line, and the ratio of effective voltage assuming the pixel at the intersection of the y-th scanning line in signal line one-end driving to be the terminal end are given in formula (26) by applying the relation of <maths id="math0176"><math display="inline"><mrow><msup><mrow><mtext>RL · CL = 4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext> · rs · cs + 2 π · y · cs · Rsw</mtext></mrow></math><img file="EP0875879A1_D0176.tif" /></maths> and others in formula (25A).

0222In the case of signal line both-end simultaneous driving, up to <maths id="math0177"><math display="inline"><mrow><mtext>y=N</mtext></mrow></math><img file="EP0875879A1_D0177.tif" /></maths>,<maths id="math0178"><math display="block"><mrow><msup><mrow><mtext>γsw(y)= {1-2(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·rs·cs+2π·y·cs·Rsw)·N/(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N-1)/ (π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH)}</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></math><img file="EP0875879A1_D0178.tif" /></maths>

0223In the case of signal line one-end driving, up to <maths id="math0179"><math display="inline"><mrow><mtext>y=2N</mtext></mrow></math><img file="EP0875879A1_D0179.tif" /></maths>,<maths id="math0180" num="(26)"><math display="block"><mrow><msup><mrow><mtext>γss(y)= {1-2(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·rs·cs+2π·y·cs·Rss)·N/(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+N-1)/ (π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH)}</mtext></mrow><mrow><mtext>(1/2)</mtext></mrow></msup></mrow></math><img file="EP0875879A1_D0180.tif" /></maths>

0224It is known from formula (26) that the lateral luminance error in signal line both-end simultaneous driving is about 1/4 as compared with signal line one-end driving.

0225Supposing the effective voltage ratio of virtual terminal end and drive end of signal line in signal line both-end driving to be γ 1s, and the effective voltage ratio of terminal end and drive end in one-end driving to be γ 2s, the output resistance of the signal line drive circuit is obtained in formula (27).

0226In the case of signal line both-end simultaneous driving, the output resistance is<maths id="math0181"><math display="block"><mrow><msup><mrow><mtext>Rsw≦[1-(γ1s)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>]·π·TH/(4N·cs)·(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+N-1)/N-2N· rs/π</mtext></mrow></math><img file="EP0875879A1_D0181.tif" /></maths>

0227In the case of signal line one-end driving, the output resistance is<maths id="math0182" num="(27)"><math display="block"><mrow><msup><mrow><mtext>Rss≦[1-(γ2s)</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>]·π·TH/(8N·cs)·(a</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+N-1)/N-4N· rs/π</mtext></mrow></math><img file="EP0875879A1_D0182.tif" /></maths>

0228As shown above, also in the case of signal line both-end simultaneous driving of the invention, the signal line can be expressed by a series circuit composed of resistance of <maths id="math0183"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0183.tif" /></maths> and a capacitance of <maths id="math0184"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0184.tif" /></maths>, and therefore the liquid crystal display device small in longitudinal luminance error and longitudinal crosstalk and high in display quality is realized.

(Embodiment 9)

0229A liquid crystal display device in embodiment 9 of the invention is described below. Fig. 33 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In this example, scanning line drive terminals of the liquid crystal panel 14H in Fig. 25 are disposed in reverse right and left relation, and the signal line of the liquid crystal panel 14I is driven simultaneously at both ends. In such constitution, too, the same effects as in embodiment 8 are obtained.

(Embodiment 10)

0230A liquid crystal display device in embodiment 10 of the invention is described below. Fig. 34 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In Fig. 34, the both ends of the signal line 9 of the capacitive coupled TFT liquid crystal panel 14J are driven simultaneously, and the left end of the scanning line 11 is driven. The other constitution is same as in Fig. 24. As mentioned above, mostly, the signal line drive circuit of the TFT type liquid crystal panel incorporates a DA converter for realizing multi-gradation display, and the output circuit may be regarded as an analog amplifier, but for the sake of simplicity of explanation, the signal line drive circuit is composed of the same reference numerals as in Fig. 49.

0231The pixel capacitance of the TFT type liquid crystal panel is determined on the basis of the counter electrode as shown in embodiment 4, and therefore its constitution is different from the pixel capacitance of the simple matrix type liquid crystal panel. In Fig. 20, replacing the scanning lines by the signal lines, and supposing the wiring resistance to be rs and the pixel capacitance between the signal line and counter electrode to be cs, the signal line, same as the scanning line, can be regarded as a distributed parameter circuit, and in signal line both-end simultaneous driving, by dividing into two (or more) from the virtual terminal end, each can be expressed by the distributed parameter circuit driven at one end, and hence the signal line may be regarded as a lumped parameter circuit composed of resistance of 2N · rs and capacitor of 2N · cs from formulas (8) and (9). From the composition of the pixel shown in Fig. 17, cs may be approximated by formula (28).<maths id="math0185" num="(28)"><math display="block"><mrow><mtext>Cs=Ccs+Cgs·Ccg/(Cgs+Ccg)</mtext></mrow></math><img file="EP0875879A1_D0185.tif" /></maths>

0232Therefore, the signal line driving voltage is determined by using the pixel capacitance of formula (28) in formula (23). In driving of capacitive coupled TFT type liquid crystal panel, as shown in Fig. 17 and Fig. 18, when an ON voltage is applied to the gate of the TFT, simultaneously, the coupling voltage due to Vg+ or Vg- is applied to the drain of the TFT through the coupling capacitance Cst at the same time. This coupling voltage is supposed to be η (+) and η (-). These values η (+) and η (-) are constants determined by Cst, Cls, Cgd, etc. The voltage of the pixel selected by the scanning line is regarded to be combined with these coupling voltages η (+) and η (-) in addition to the signal line driving voltage. Accordingly, in driving of capacitive coupled TFT type liquid crystal panel, the amplitude of the signal line driving voltage can be decreased.

0233The effective voltage of the pixel of the capacitive coupled TFT type liquid crystal panel 14J is sample-held value of the signal line driving voltage at <maths id="math0186"><math display="inline"><mrow><mtext>t=TH</mtext></mrow></math><img file="EP0875879A1_D0186.tif" /></maths> by the TFT. The TFT is similar to the ideal SW, and supposing the increase of effective voltage due to η (+) and η (-) to be δ , and the voltage for compensating the polarization voltage caused in the pixel as a result to be Δ, the substantial signal line driving voltage is <maths id="math0187"><math display="inline"><mrow><mtext>V sig = VH - Vref1 + Δ</mtext></mrow></math><img file="EP0875879A1_D0187.tif" /></maths> , or <maths id="math0188"><math display="inline"><mrow><mtext>V sig = Vref2 + Δ - VL</mtext></mrow></math><img file="EP0875879A1_D0188.tif" /></maths>. When this relation is applied to formula (23), and assuming <maths id="math0189"><math display="inline"><mrow><mtext>t=TH</mtext></mrow></math><img file="EP0875879A1_D0189.tif" /></maths>, the effective voltage of the pixel is obtained. That is, supposing the output resistance of the signal line drive circuit of the capacitive coupled TFT type liquid crystal panel to be Rsw in the case of signal both-end simultaneous driving or Rss in the case of one-end driving, and the pixel at the intersection with the y-th scanning line from the drive end of signal line to be virtual terminal end or divided terminal end, the effective voltage of the pixel is expressed in formula (29), in which the number of scanning lines is 2N, the horizontal scanning time is TH, the operation reference voltage at VH is Vref1, and the operation reference voltage at VL is Vref2.

0234In signal line both-end simultaneous driving, the effective voltage of the pixel, assuming y≦N, is<maths id="math0190"><math display="block"><mrow><msup><mrow><mtext>Vrmssw(y)= (Vsig-Δ)·[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msub><mrow><mtext>·TH/(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>·rs·cs·+2π· y·cs·Rsw}]+δ</mtext></mrow></math><img file="EP0875879A1_D0190.tif" /></maths>

0235In signal line one-end driving, the effective voltage of the pixel, assuming y≦2N, is<maths id="math0191" num="(29)"><math display="block"><mrow><msup><mrow><mtext>Vrmsss(y)= (Vsig-Δ)·[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH/(4y</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·rs·cs·2π· y·cs·Rss}]+δ</mtext></mrow></math><img file="EP0875879A1_D0191.tif" /></maths>

0236The effective voltage ratio of virtual terminal end or terminal end and drive end of signal line is given in formula (30) by using the effective voltage at drive end <maths id="math0192"><math display="inline"><mrow><mtext>(Vsig - Δ) + δ</mtext></mrow></math><img file="EP0875879A1_D0192.tif" /></maths> and formula (29).

0237In signal line both-end simultaneous driving, the effective voltage ratio γ sw, assuming <maths id="math0193"><math display="inline"><mrow><mtext>y = N</mtext></mrow></math><img file="EP0875879A1_D0193.tif" /></maths>, is<maths id="math0194"><math display="block"><mrow><msup><mrow><mtext>γsw≒[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH/(4N</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·rs·cs+2π·N·cs· Rsw}]</mtext></mrow></math><img file="EP0875879A1_D0194.tif" /></maths>

0238In signal line one-end driving, the effective voltage ratio γ ss, assuming <maths id="math0195"><math display="inline"><mrow><mtext>y = 2N</mtext></mrow></math><img file="EP0875879A1_D0195.tif" /></maths>, is<maths id="math0196" num="(30)"><math display="block"><mrow><msup><mrow><mtext>γss≒[1-2exp{-π</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>·TH/(16N</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>·cs·rs+4π·N·cs· Rss}]</mtext></mrow></math><img file="EP0875879A1_D0196.tif" /></maths>

0239Also in the capacitive coupled TFT type liquid crystal panel in signal line both-end simultaneous driving, the longitudinal luminance error is smaller than in signal line one-end driving as shown in formula (30). The waveform distortion is also about 1/4, and the longitudinal crosstalk is smaller.

0240Supposing the effective voltage ratio of virtual terminal end and drive end of signal line in signal line both-end simultaneously driving to be γ ls and the effective voltage ratio of terminal end and drive end in one-side driving to be γ 2s, the output resistance range of signal line driving circuit of TFT type liquid crystal panel is obtained from formula (30) as expressed in formula (31).

0241In signal line both-end simultaneous driving,<maths id="math0197"><math display="block"><mrow><mtext>Rsw≦-2N·rs/π-π·TH/[2N·cs·ln{(1-y1s)/2}]</mtext></mrow></math><img file="EP0875879A1_D0197.tif" /></maths>

0242In signal line one-end driving,<maths id="math0198" num="(31)"><math display="block"><mrow><mtext>Rss≦-4N·rs/π-π·TH/[4N·cs·ln{(1-γ2s)/2}]</mtext></mrow></math><img file="EP0875879A1_D0198.tif" /></maths>

0243Thus, in signal line both-end simultaneous driving of the capacitive coupled TFT type liquid crystal panel, too, the signal line can be expressed as a series circuit composed of resistance of <maths id="math0199"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0199.tif" /></maths> and capacitance of <maths id="math0200"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0200.tif" /></maths> , and the same effects as in embodiment 8 are obtained.

(Embodiment 11)

0244A liquid crystal display device in embodiment 11 of the invention is described below. Fig. 35 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In this embodiment, scanning line drive terminals of the liquid crystal panel 14J in Fig. 34 are disposed in reverse right and left relation, and the signal line of the liquid crystal panel 14K is driven simultaneously at both ends. In such constitution, too, the same effects as in embodiment 10 are obtained.

(Embodiment 12)

0245A liquid crystal display device in embodiment 12 of the invention is described below. Fig. 36 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. The liquid crystal panel 14L in Fig. 36 is for signal line both-end simultaneous driving of the TFT type liquid crystal panel not coupled capacitively. In such constitution, too, the formulas (23), (24), and (28) to (31) can be applied, and the same effects as in embodiments are obtained.

(Embodiment 13)

0246A liquid crystal display device in embodiment 13 of the invention is described below. Fig. 37 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In this embodiment, scanning line drive terminals of the liquid crystal panel 14L in Fig. 36 are disposed in reverse right and left relation, and the signal line of the liquid crystal panel 14M is driven simultaneously at both ends. In such constitution, too, the same effects as in embodiment 11 are obtained.

(Embodiment 14)

0247A liquid crystal display device in embodiment 14 of the invention is described below. Fig. 40 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In the embodiment, both ends of signal lines 9 and scanning lines 12 of the capacitive coupled TFT type liquid crystal panel 14N are driven simultaneously.

0248This embodiment is applied to driving of extra-large liquid crystal panel. Besides, this embodiment is also suited for the case necessary to use a drive circuit insufficient in driving capacitance, for example, a liquid crystal panel having a drive circuit formed (a liquid crystal panel using polysilicon TFT, etc.) or disposed (by mounting technology of chip-on-glass, etc.) outside of the image display region of the liquid crystal panel. A drive terminal structure of the liquid crystal panel 14N is shown in Fig. 42.

0249The results and effects about signal line both-end simultaneous driving and scanning line both-end simultaneous driving already explained can be applied directly. That is, the signal line can be expressed as a series circuit composed of resistance of <maths id="math0201"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0201.tif" /></maths> and capacitance of <maths id="math0202"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0202.tif" /></maths>, and the scanning line can be expressed as a series circuit composed of resistance of <maths id="math0203"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0203.tif" /></maths> and capacitance of <maths id="math0204"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0204.tif" /></maths>.

(Embodiment 15)

0250A liquid crystal display device in embodiment 15 of the invention is described below. Fig. 41 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In this embodiment, both ends of signal lines 9 and scanning lines 12 of TFT type liquid crystal panel 14P not coupled capacitively are driven simultaneously. In such constitution, too, the same effects as in embodiment 14 are obtained.

(Embodiment 16)

0251A liquid crystal display device in embodiment 16 of the invention is described below. Fig. 43 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In the embodiment, both ends of signal lines 9 of the capacitive coupled TFT type liquid crystal panel 14Q, and right scanning line and left scanning line are driven simultaneously. The embodiment is applied to an extra-large liquid crystal display device, and it is also effective when dividing the display screen into two sections and displaying different pieces of information. It is similarly applied with same effects also in the TFT type liquid crystal panel not coupled capacitively, simple matrix type liquid crystal panel, and liquid crystal panel forming or disposing drive circuit of signal lines and scanning lines outside of the image region of the liquid crystal panel. The drive terminal structure of the liquid crystal panel 14Q is shown in Fig. 44. The results and effects about signal line both-end simultaneous driving and scanning line both-end simultaneous driving already explained can be applied directly. That is, the signal line can be expressed as a series circuit composed of resistance of <maths id="math0205"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0205.tif" /></maths> and capacitance of <maths id="math0206"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0206.tif" /></maths>, and the scanning line can be expressed as a series circuit composed of resistance of <maths id="math0207"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0207.tif" /></maths> and capacitance of <maths id="math0208"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0208.tif" /></maths>.

(Embodiment 17)

0252A liquid crystal display device in embodiment 17 of the invention is described below. Fig. 45 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In the embodiment, signal lines and scanning lines are divided into too respectively, and the capacitive coupled TFT type liquid crystal panel 14R is driven simultaneously at both ends. The embodiment is applied to an extra-large liquid crystal display device, and it is also effective when dividing the display screen into four sections and displaying different pieces of information. It is similarly applied with same effects also in the TFT type liquid crystal panel not coupled capacitively, simple matrix type liquid crystal panel, and liquid crystal panel forming or disposing drive circuit around the liquid crystal panel. The drive terminal structure of the liquid crystal panel 14R is shown in Fig. 46.

0253The results and effects about signal line both-end simultaneous driving and scanning line both-end simultaneous driving already explained can be applied directly. That is, the signal line can be expressed as a series circuit composed of resistance of <maths id="math0209"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0209.tif" /></maths> and capacitance of <maths id="math0210"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0210.tif" /></maths>, and the scanning line can be expressed as a series circuit composed of resistance of <maths id="math0211"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0211.tif" /></maths> and capacitance of <maths id="math0212"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0212.tif" /></maths>.

(Embodiment 18)

0254A liquid crystal display device in embodiment 18 of the invention is described below. Fig. 47 is a block diagram of the liquid crystal display device of this embodiment, and same parts as in the liquid crystal display device in Fig. 1 are identified with same reference numerals, and their explanation is omitted. In the embodiment, the scanning line is divided into left scanning line 12 and right scanning line 12a, and in this liquid crystal panel 14S, the right and left scanning lines are driven simultaneously, while the signal line 9 is driven at one end. This embodiment is suited to a large display device with a wide screen, for dividing the screen into two sections and displaying independent pieces of information.

0255In the embodiment, too, the results and effects about signal line one-end simultaneous driving and scanning line both-end simultaneous driving already explained can be applied directly. That is, the signal line can be expressed as a series circuit composed of resistance of <maths id="math0213"><math display="inline"><mrow><mtext>4N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0213.tif" /></maths> and capacitance of <maths id="math0214"><math display="inline"><mrow><mtext>4N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0214.tif" /></maths>, and the scanning line can be expressed as a series circuit composed of resistance of <maths id="math0215"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0215.tif" /></maths> and capacitance of <maths id="math0216"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0216.tif" /></maths>.

0256The liquid crystal panel 14S in Fig. 47 is of capacitive coupled TFT type, same effects are obtained in the TFT type not coupled capacitively, or the liquid crystal panel forming or disposing a drive circuit outside of the image display region of the liquid crystal panel. The drive terminal structure of the liquid crystal panel 14S is shown in Fig. 48.

0257Incidentally, when the signal line drive terminals are formed upside down of the liquid crystal panel 14S in Fig. 48, the same effects are obtained by one-end driving by lower signal line drive circuit.

0258The ratio of time constant for both-end driving and one-end driving is determined as follows. Supposing the time constant at terminal end of one-end driving of scanning line to be α gs, and the time constant at virtual terminal end or terminal end of scanning line divided into two in both-end driving to be α gw (screen central pixel), by using formula (18), the ratio of α gs/ α gw is expressed as shown in formula (32).<maths id="math0217" num="(32)"><math display="block"><mrow><msup><mrow><mtext>αgs/αgw=(4r·c·M</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>+2π·M·c·Rgs)/(r·c·M</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>+π· M·c·/Rgw)</mtext><mspace linebreak="newline" /><mtext> ={4+2π·Rgs/(r·M)}/{1+π·Rgw/(r·M)}</mtext></mrow></math><img file="EP0875879A1_D0217.tif" /></maths> Herein, supposing the constant to be k and α gas/ α gw ≧ k, from formula (32), the following is obtained.<maths id="math0218"><math display="block"><mrow><mtext>Rgs≧(k-4)r·M/(2π)+k·Rgw/2</mtext></mrow></math><img file="EP0875879A1_D0218.tif" /></maths> Assuming k = 4, when the time constant in both-end driving is 1/4 of the time constant in one-end driving, and there is no effect of wiring resistance, the relation of Rgs and Rgw is obtained. That is,<maths id="math0219" num="(33)"><math display="block"><mrow><mtext>Rgs≧2Rgw</mtext></mrow></math><img file="EP0875879A1_D0219.tif" /></maths> Thus, if the output resistance of the both-end driving is 1/2 or less of the output resistance at one end, the time constant is 1/4 of one-end driving, and it is known that there is no effect of wiring resistance. Formula (33) is very effective when estimating the output resistance in one-end or both-end driving. This is because the output resistance in both-end driving can be easily predicted from the drive circuit of one-end driving. The same results are obtained in the signal lines.

0259In the diagrams of the foregoing embodiments, the scanning line drive circuit and signal line drive circuit are disposed outside of the liquid crystal panel, but they may be also formed in the portion outside of the image display region of the liquid crystal display panel by COG (chip on glass) technique, or by TAB (tape automated bonding) technique outside of the image display region, even in the region overlapping with the liquid crystal panel.

0260Finally, reference numerals used in the drawings are briefly explained. The signal line drive circuits are indicated by the same reference numerals 15 and 16 throughout all the drawings. Actually, however, between the TFT type liquid crystal panel and simple matrix type liquid crystal panel, the constitution of the signal line drive circuit is different, and the signal line drive circuit in Fig. 1 cannot be applied in Fig. 16. In principle, they should be expressed differently, but in such a case the reference numerals are increased and complicated, and since the functions of driving the signal lines are the same, the same reference numerals are commonly used for the signal line drive circuits throughout the drawings (it is not meant that the detail of the specification is identical).

0261As for the drive power source circuit, since the function of supplying driving voltage to the scanning line or the signal line drive circuit is same in all drive power source circuits, the reference numeral 19 is commonly used in all drawings (it is not meant that the detail of the specification is identical). The reference numerals of scanning line drive circuits and control circuits are also given according to the same concept.

0262Incidentally, the scanning line and signal line drive circuits, drive power source circuit, control circuit and others in the drawings are mass-produced at the present, and the structure and operating principle of these circuits are known, and hence the explanation is omitted except for the parts particularly necessary for description of the invention of the present application (for example, the analog switch for composing the output circuit of drive circuit).

0263In the equivalent circuit of liquid crystal panel, and equivalent circuit of TFT, only the parameters that can be clearly handled numerically in design or in theory were included (for example, wiring resistance, capacitance between electrodes of TFT, liquid crystal capacitance, capacitance at intersection of signal line and scanning line). The coincidence between the calculated values using these parameters and measured values is proved.

0264However, for example, by wiring to connect the drive end of scanning line or signal line and the drive circuit, wiring resistance and parasitic capacitance are formed, and parameters not expressed in the invention are actually present, but they are omitted. This is because such parasitic capacitance and wiring resistance are small numerically and induce only small errors if ignored, and, if necessary, they can be calculated later by using the formulas presented in the invention

0265Thus, according to the invention as set forth in claims 1 to 11, by driving the scanning lines or signals lines of the liquid crystal panel simultaneously at both ends, if the driving current of scanning lines or signal lines is same as in one-end driving, the delay time of the scanning line driving voltage or signal line driving voltage applied to each pixel of the liquid crystal panel can be reduced as compared with one-end driving. As a result, in the large-sized liquid crystal display device of long diagonal length and large in the number of pixels in the horizontal direction and vertical direction, luminance unevenness can be decreased. Moreover, in two scanning line drive circuits or signal line drive circuits necessary for both-end simultaneous driving of scanning lines or signal lines of the liquid crystal panel, ICs of identical pattern can be used, so that the cost required for simultaneous driving is not so much increased.

0266In particular, according to the invention as set forth in claims 9 to 11, by expressing the scanning lines driven simultaneously at both ends, being divided virtually into two at virtual terminal end or divided evenly into two, by a lumped parameter circuit composed of resistance of <maths id="math0220"><math display="inline"><mrow><mtext>M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0220.tif" /></maths> and capacitance of <maths id="math0221"><math display="inline"><mrow><mtext>M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0221.tif" /></maths>, or by expressing the signal lines driven simultaneously at both ends, being divided virtually into two at virtual terminal end or divided evenly into two, by a lumped parameter circuit composed of resistance of <maths id="math0222"><math display="inline"><mrow><mtext>2N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0222.tif" /></maths> and capacitance of <maths id="math0223"><math display="inline"><mrow><mtext>2N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0223.tif" /></maths>, the luminance distribution in the scanning line direction of each pixel or the luminance distribution in the signal line direction can be accurately predicted. By using such equivalent circuit, a liquid crystal display device setting the luminance unevenness within a specified value can be designed.

0267In particular, according to the invention as set forth in claims 17 and 19, the output resistance of the drive circuit for scanning line both-end simultaneous driving or signal line both-end simultaneous driving can be determined optimally.

0268In particular, according to the invention as set forth in claims 21, 23 and 25, the driving current of the drive circuit for scanning line both-end simultaneous driving or signal line both-end simultaneous driving can be obtained accurately.

0269In particular, according to the invention as set forth in claims 32 and 34, in the liquid crystal panel by scanning line both-end simultaneous driving or signal line both-end simultaneous driving, the ratio of effective voltage applied to the pixel at the center of the scanning line or signal lines to effective voltage applied to the pixel at the drive end can be obtained accurately.

0270In particular, according to the invention as set forth in claim 36, the threshold voltage of the TFT type liquid crystal panel by scanning line both-end simultaneous driving can be obtained.

0271Also, according to the invention as set forth in claims 12, 16, 18, 20, 22, 24, 26, 33, 35 and 37, even in the case of one-end driving of scanning lines or signal lines of the liquid crystal panel, by expressing the equivalent circuit of each scanning line by a lumped parameter circuit composed of resistance of <maths id="math0224"><math display="inline"><mrow><mtext>2M · r/ π</mtext></mrow></math><img file="EP0875879A1_D0224.tif" /></maths> and capacitance of <maths id="math0225"><math display="inline"><mrow><mtext>2M · c/ π</mtext></mrow></math><img file="EP0875879A1_D0225.tif" /></maths>, and similarly by expressing the equivalent circuit of each signal line by a lumped parameter circuit composed of resistance of <maths id="math0226"><math display="inline"><mrow><mtext>4N · rs/ π</mtext></mrow></math><img file="EP0875879A1_D0226.tif" /></maths> and capacitance of <maths id="math0227"><math display="inline"><mrow><mtext>4N · cs/ π</mtext></mrow></math><img file="EP0875879A1_D0227.tif" /></maths>, the driving voltage of each pixel, effective voltage ratio of drive end and terminal end, threshold voltage of liquid crystal panel, output resistance of drive circuit, and driving current of drive circuit can be analyzed or set more accurately.