Module-configurable, full-chip power profiler

Technical Field of the Invention

This invention relates to power profilers, and more particularly relates to a power profiler for integrated circuits including one or more microprocessors, wherein the profiler provides power data at an instruction level, for software instruction optimization for low power.

Background of the Invention

Low power optimization in the area of integrated circuits ("ICs") is a known goal. Numerous tools exist for IC designers, including designers of microprocessors, to optimize their designs for low power. In addition, tools have been described to assist programmers of software to be executed on microprocessors to optimize instruction selection for low power.

For example, in an article entitled, "Power Analysis of Embedded Software: A First Step Towards Software Power Minimization," by Vivek Tiwari, et al., IEEE Trans. on VLSI Systs., Vol. 2, No. 4, Dec., 1994, a methodology is proposed for instruction level power modeling in which the current drawn by a microprocessor is measured. The authors suggest that simulation based power analysis tools might be used in generating CPU models, without indicating how that might be done in any practical scale. In fact, for embedded system design the authors pointed out problems they believed would exist in attempting such an approach. Instead, the authors recommended a methodology based on laboratory measurements of CPU power consumption during execution of selected instructions. Based on such measurements, the authors propose a model in which the total IC power consumption is broken down into components such as "base energy cost," "inter-instruction effects," "effects of resource constraints," etc. These components are provided for each instruction in a program, and summed, to yield an estimated power consumption for the program.

In a subsequent article entitled, "Power Analysis of a Programmable DSP for Architecture/Program Optimization," by Hirotsugu Kojima, et al., ICSPAT Conf., 1995, the authors propose a power modeling methodology based on power analysis of a digital signal processor ("DSP") using switch level and cell based simulation. The authors draw certain conclusions in their paper about relative contributions to overall power consumption of the DSP under analysis of, e.g., clock and bus circuits vs. data path. No proposals are made as to practical application of any results to software optimization, however.

In U.S. Patent No. 5,557,557, entitled "Processor Power Profiler," which issued on September 17, 1996, to Gene A. Frantz, et al., and which is commonly assigned, a method is presented for determining the energy consumption of a processor when executing a program. The method is embodied in a power profiler program, and initially selects the processor which will execute the program. It then creates a model of energy used by the processor as a function of a plurality of instructions operable by the processor. The model is constructed based on measurements of the processor current taken under various controlled conditions. The program whose energy consumption is to be determined is then executed using the energy model to determine the energy consumption of the program on the processor. The energy model relates information regarding instruction opcodes, data values, processor environment, etc., to power data provided by a processor simulator or evaluator program, and adds the power data. The method groups certain instructions by common power considerations, and so partitioning of instructions is done in an early phase of the method, to take advantage of this grouping.

The patent to Frantz, et al. provides an excellent method for power analysis of a microprocessor at the instruction level. However, there is a desire for a method for power analysis of a microprocessor with expanded capabilities, for even greater accuracy.

Summary of the Invention

According to the principles of the present invention, a method is provided for determining the power consumption, resulting from execution of a block of code, of an integrated circuit that includes a processor module and one or more other circuit modules. The method involves the steps of, first, providing a set of average current values for each of said modules, for a predetermined plurality of sets of conditions based on predetermined sets of signal line states associated with said module, for each instruction in the instruction set of said processor module, said sets of conditions being selected for dominant power consumption effect on the module. For each module, for each instruction in a block of code to be executed on said processor module, a set of signal line states is generated, associated with said module, for each processor cycle, in sequence. The generated set of signal line states are then tested for said set of conditions. One of said average current values is assigned for each condition so tested that is met. Finally, the running total of said average current values so met is accumulated for each such processor cycle.

The average current values can be translated for different frequencies and supply voltages. Also, average current can be converted to average power consumption.

Thus, the present invention provides a method for power analysis of an integrated circuit that includes a processor module, at the sub-block level. The present invention allows instruction-level power profiling and, for processors with parallelized architectures, execute-packet level power profiling. The analysis may be done on a cycle-by-cycle basis. Further, the power components are provided on an algorithm basis, as compared with prior art look-up table basis. This provides greatly expanded capabilities over prior art methods, including modeling of sensitivities due to different types of instructions, use of different functional units, internal switching activity, effects of other instructions in the pipeline, varying degrees of parallelism, changes in data operands, and conditional execution.

These and other features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.

Brief Description of the Drawings

<ul id="ul0001" list-style="none" compact="compact"><li>Fig. 1 is a block diagram of a multi-module integrated circuit that includes a processor module;</li><li>Fig. 2 is a signal diagram that shows baseline current drawn from the processor module of Fig. 1;</li><li>Fig. 3 is a signal diagram that shows the averaging of the baseline current of Fig. 2;</li><li>Fig. 4 is a signal diagram that shows non-baseline current drawn from the processor module of Fig. 1;</li><li>Fig. 5 is a signal diagram that shows the averaging of the baseline current of Fig. 4;</li><li>Fig. 6 is a flow chart showing the steps involved in the general method of the preferred embodiment of the present invention; and</li><li>Fig. 7 is a diagram showing module typing considerations for principal power component determination.</li></ul>

Detailed Description of the Preferred Embodiment

Figure 1 is a block diagram of a highly integrated circuit ("IC") 10 implemented in complementary metal oxide semiconductor ("CMOS") technology, for which it is desired to know power consumption, as a function of the execution of a given instruction set. The IC 10 includes several modules: a central processing unit ("CPU") core 12, input-output ("I/O") buffers 14, memory modules 16 which include Program Memory PM and Data Memory DM, a cache control unit 18, a phase lock loop ("PLL") clocking unit 20, various peripheral modules 22, a test unit 24 including scan and boundary scan circuitry, and customizing logic unit 26 which contains logic for customizing the IC 10 for a particular application. The CPU 12 includes various units, such as a program generator unit PGEN, an instruction dispatch unit IDU, predecoder unit PDU, first and second decoder units DCU 1, DCU 2, two register files REGFILE 1, REGFILE 2, two or more execution units EU associated with each of the register files, and various other control and test-related units, such as control registers CR, clock generation units and buffers DTP_CCU, and emulation circuitry MTAP, represented collectively as CR in Figure 1. The circuit design of IC 10 utilizes conventional master/slave latching, driven by conventional master/slave clock signals. The particular architecture and circuit methodology of a given IC for which it is desired to know power consumption are not critical to the application of the principles of the present invention. The present invention is applicable to a wide variety of circuitry, as will be appreciated after the principles, presented hereinbelow, are understood. For purposes of description hereinbelow, it is assumed that the IC 10 under consideration is a customizable IC utilizing a CPU 12 core that is a Texas Instruments ® TMS320C60 digital signal processor ("DSP"). This processor core has a very large instruction word ("VLIW") architecture, capable of processing up to eight instructions per clock cycle, and it utilizes two data paths, with two REGFILEs and two sets of EUs.

The preferred embodiment of the present invention provides a method for generating an accurate estimate of the power consumption of IC 10 as a function of the execution of instructions from the instruction set of the CPU 12. This, in turn, permits the optimization for low power operation of IC 10 of a block of code, or program, to be executed on CPU 12. Very broadly, the method involves determining the current flow to the individual modules of IC 10 using a simulation tool, and analyzing power consumption, for the various instructions in the instruction set of CPU 12. From the data so generated, an algorithm is generated for each module that can operate in conjunction with, e.g., an instruction-level simulator, or a behavioral/logic simulator (e.g., Quick HDL®), or a Quick Turn Box/environment, to provide accurate modeling of power consumption as a function of the instructions in the block of code under consideration.

Figure 2 is a diagram showing the current flow 28, i_vmn(t), for a module n, over time t, plotted against the waveform 30 of a master clock pulse and the waveform 32 of a slave clock pulse, during a single system clock cycle in which only NOP instructions are being executed. In other words, the module is exhibiting minimum switching behavior. The diagram may be generated using any of the conventional circuit simulation tools that provide a value for current flow, such as the Power Mill™ simulator tool and Turbowave™ graphical display tool, manufactured by the Synopsys Physical Tools Group, formerly EPIC Design Technology, Inc. As can be seen, at the rising edge 34 of the master clock waveform 30 a burst 36 of current i_vmn occurs, at the falling edge 38 of the master clock waveform 30 a burst 40 of current i_vmn occurs, at the rising edge 42 of the slave clock waveform 32 a burst 44 of current i_vmn occurs, and at the falling edge 46 of the slave clock waveform 32 a burst 48 of current i_vmn occurs. Since these current bursts are measured during a series of NOP instructions, which produce the minimum switching in the IC, they are considered representative of the switching activity in the module that occurs regardless of the instruction, and the energy they represent is referred to as the baseline energy for the module.

Figure 3 is a diagram showing the conversion of the pulse waveform representation, or view, of the current burst waveforms 36, 40, 44, 48, to an average current representation, or view, for the single clock cycle. The area under the waveforms 36, 40, 44, 48, is summed and averaged over the clock cycle 50 - 52, to yield an average baseline current 54, I_BL. Thus, denominating the energy under waveform 36 as <i>A1</i>, denominating the energy under waveform 40 as <i>A2,</i> denominating the energy under waveform 44 as <i>A3,</i> and denominating the energy under waveform 48 as <i>A4,</i> the average current per clock cycle ("<i>clockperiod</i>") for this baseline state, I_AVG(NOP), is:<maths id="math0001" num=""><math display="block"><mrow><msub><mrow><mtext>I</mtext></mrow><mrow><mtext>AVG</mtext></mrow></msub><msub><mrow><mtext>(NOP) = I</mtext></mrow><mrow><mtext>BL</mtext></mrow></msub><mtext> = </mtext><mfrac><mrow><mtext>Σ</mtext><mtext mathvariant="italic">A</mtext><mtext>1+</mtext><mtext mathvariant="italic">A</mtext><mtext>2+</mtext><mtext mathvariant="italic">A</mtext><mtext>3+</mtext><mtext mathvariant="italic">A</mtext><mtext>4</mtext></mrow><mrow><mtext mathvariant="italic">clockperiod</mtext></mrow></mfrac><mtext> .</mtext></mrow></math><img file="EP0875833A1_D0001.tif" /></maths>

Figure 4 is a diagram similar to Figure 2, showing the current flow 56, i_vmn(t), for a module n, over time t, plotted against the waveform 30 of a master clock pulse and the waveform 32 of a slave clock pulse, during a single system clock cycle in which a non-NOP instruction is executed. As in Figure 2, the baseline current burst waveforms 36, 40, 44, 48, can be seen, representing energy components <i>A1, A2, A3</i> and <i>A4.</i> However, two additional current burst waveforms 58, 60, can be seen. These additional current burst waveforms 58, 60, represent non-baseline activity, having energy components <i>A5, A6,</i> respectively. The current flow 56 is typical for, e.g., the CPU module 12 (Fig. 1). The current burst waveform 58 appears after the energy burst 44 associated with the rising edge 42 of the slave clock waveform 32. The rising edge 42 of the slave clock waveform 32, in conventional master/slave latch methodology circuitry, provides the signals, latched in a given stage in the previous clock cycle, to the next stage for operation thereon. This triggers a burst of switching, which is shown by the appearance of current burst waveform 58. The current burst waveform 60 appears at the point in time when data, requested by the instruction dispatch unit ("IDU") within the CPU module 12 (Fig. 1), appears at the input of the IDU. In other words, the time lag of waveform 60 from waveform 44 reflects the latency for data retrieval to the IDU.

Figure 5 is a diagram similar to that of Figure 3, showing the conversion of the pulse waveform representation, or view, of the current burst waveforms 36, 40, 44, 48, 58, 60, to an average current representation, or view, for the single clock cycle. The baseline and non-baseline energy components are distinguished by cross hatching having different directions. Thus, baseline energy components <i>A1, A2, A3</i> and <i>A4,</i> can be seen, and non-baseline energy components <i>A5, A6,</i> can be seen as well but with different cross-hatching. As in Figure 3, the area under the waveforms 36, 40, 44, 48, is summed and averaged over the clock cycle 50 - 52, to yield the average baseline current 54, I_BL. In addition, the area under the waveforms 58, 60, is summed and averaged over the clock cycle 50 - 52, to yield an average non-baseline current 62, I_NBL. Thus, the total average current in this situation, I_AVG(NNOP), is the sum of the baseline current IBL and the non-baseline current I_NBL:<maths id="math0002" num=""><math display="block"><mrow><msub><mrow><mtext>I</mtext></mrow><mrow><mtext>AVG</mtext></mrow></msub><msub><mrow><mtext>(NNOP) = I</mtext></mrow><mrow><mtext>BL</mtext></mrow></msub><msub><mrow><mtext> + I</mtext></mrow><mrow><mtext>NBL</mtext></mrow></msub><mtext> = </mtext><mfrac><mrow><mtext>Σ</mtext><mtext mathvariant="italic">A</mtext><mtext>1+</mtext><mtext mathvariant="italic">A</mtext><mtext>2+</mtext><mtext mathvariant="italic">A</mtext><mtext>3+</mtext><mtext mathvariant="italic">A</mtext><mtext>4+Σ</mtext><mtext mathvariant="italic">A</mtext><mtext>5+</mtext><mtext mathvariant="italic">A</mtext><mtext>6</mtext></mrow><mrow><mtext mathvariant="italic">clockperiod</mtext></mrow></mfrac><mtext> .</mtext></mrow></math><img file="EP0875833A1_D0002.tif" /></maths>

Thus, in the practice of the preferred embodiment of the present invention, it is necessary to determine the average baseline current I_BL. This is always a constant for a given block of circuitry. Then, the average non-baseline current I_NB is determined, and for a given sequence, or block, of instructions, the average baseline and non-baseline components are added to form the average current for the current cycle I_AVG(cc).

In general, the non-baseline current I_NBL for a block of circuitry consists of multiple components, and determination of the values for this current can be quite complex, depending on the complexity of the logic function implemented in the given block. However, application of the inventive principles is straightforward, no matter what the function of the block, as will be seen from the description hereinbelow.

In some cases, the non-baseline components can be expressed in an absolute manner, i.e., based on the number of bits changing in input and/or output signals. In other cases, a more heuristic approach must be used which, while often less accurate, may be the only practical way to provide a reasonable estimate of current, and, hence, energy consumption.

The detailed steps in the method of the preferred embodiment will now be described. Derivation of actual algorithms for exemplary functional units will be presented, to illustrate the application of the principles of the present invention. Current values are obtained by running the Power Mill® simulator program, with parameter settings as indicated.

Figure 6 is a flow chart showing the method of the preferred embodiment at a high level. The method is implemented in program code, that can be written by those of ordinary skill in the IC simulation tool art, once the principles of the invention, as described herein, are understood. The method of Figure 6 provides the power consumption of the CPU 12. By the application of the principles described herein the ordinary practitioner can readily implement the method for other modules, as well. Values used in the method include I_CPU and P_CPU, sometimes referred to as I_MM and P_MM. I_CPU is the total current drawn by the CPU 12, while P_CPU is the total power consumed by the CPU 12.

The method starts 100 at time t = 0. Clock cycle count ("cc") is initiated 102 to 1, cc = 1. At this point, I_CPU and P_CPU are both 0. A new clock cycle is computed 104.

It is then determined whether the CPU 12 is in power down mode 1 or 2, 106. These are power down modes that are available in the TMS320C60 architecture. The significance for the present discussion of these power down modes, and power down mode 3, discussed below, is that in power down modes 1 and 2 some clocks are still active in the CPU 12 to support circuitry in certain control blocks, so that the CPU 12 can respond to interrupts. In power down mode 3, all clocks to the CPU 12 are disabled.

If the CPU 12 is in power down mode 1 or 2, then the average drawn by the CPU 12 for the current cycle, I_CPU(cc), is fixed at 0.14 mA/MHz 108. Then, housekeeping/profiling 110 is performed, followed by certain accumulation steps 112 being performed. For example, for the specified power supply voltage, V_DD and clock frequency I_CPU(cc) is stored to memory. Then the power consumed by the CPU 12 for the current cycle, P_CPU(cc)is calculated, P_CPU = V_DD * I_CPU(cc), and stored to memory, as well. The cumulative I_CPU total is then calculated, I_CPU total = I_CPU total + I_CPU(cc), and the result stored to memory. Likewise, the cumulative P_CPU total is then calculated, P_CPU total = P_CPU total + P_CPU(cc), and the result stored to memory.

It is then determined whether the current clock cycle is the last clock cycle 114. If not, the clock counter is incremented 116, cc = cc + 1, and the routine returns to step 104. If it is the last clock cycle, however, three sub-steps 118 are performed. The total average current is calculated, being I_CPU total, divided by the total number of clock cycles. The total average power is also calculated, being P_CPU total, divided by the total number of clock cycles. Finally, the total energy is calculated, being the total average power, times the number of clock cycles, times the clock period. The routine then ends 120.

If it is determined in step 106 that the CPU 12 is not in power down mode 1 or 2, it is then determined whether the CPU 12 is in power down mode 3. If it is, then the average drawn by the CPU 12 for the current cycle, I_CPU(cc), is fixed at 0 mA/MHz 124. Then, the housekeeping/profiling 110 is performed, followed by accumulation steps 112, and so on, as before.

On the other hand, if it is determined that CPU 12 is not in power down mode 3, then I_CPU(cc) is the sum of the individual block currents 126, and a full power synthesis sequence 128 is begun. In the full power synthesis 128, a power determination algorithm for each module is performed. Thus, there can be seen in Figure 6 the power determination algorithm blocks for the following modules: the control registers, etc. 130, the IDU 132, the PGEN 134, the PREDECODE 136, the DECODE 1 138, the DECODE 2 140, the DATAPATH 1 142, and the DATAPATH 2 144. Note that the DATAPATH 1 142 block is further decomposed into power algorithm blocks for: REGFILE 1 146, M-UNIT 1 148, S-UNIT 1 150, L-UNIT 1 152, DAU 1 154, LD1 156 AND ST1 158. Likewise, note that the DATAPATH 2 144 block is further decomposed into power algorithm blocks for: REGFILE 2 160, M-UNIT 2 162, S-UNIT 2 164, L-UNIT 2 166, DAU 2 168, LD2 170 AND ST2 172.

The results of the performance of algorithms 130, 132, 134, 136, 138 and 140 are summed 174, as are the results of the performance of the various algorithms for DATAPATH 1 176, and the results of the performance of the various algorithms for DATAPATH 2 178. In turn, the sums from steps 174, 176 and 178 are summed 180, and the resulting value for I_CPU(cc) 182 is then treated as above 184, by executing the housekeeping/profiling steps 110, etc.

After cycling the foregoing method though each instruction in the block of code under consideration, the accumulated values for I_CPU total, P_CPU total, total average current, total average power and total energy, provide the results of the test 118.

Various inventive techniques involved in generating the algorithms for the various functional blocks will now be described. The general approach involves a clock-cycle-by-clock-cycle summation algorithm using current data (mA/MHz) located in a look-up table, providing a programmable, configurable approach. The data in the table is process/technology dependent, and can be linearly scaled for different supply voltage, V_DD, and clock frequencies. The source of the data for the preferred embodiment is, as mentioned above, Power Mill simulation/characterization using module level transistor netlists with extracted parasitics. Note that the QuickVHDL™ tool, by Mentor Graphics Corporation, and Design Power™ tool, by Synopsys, Inc., may be used as well, as sources for data. In some cases, such tools may be preferable, for example for creating algorithms for processor peripherals such as serial ports, timers, cache control, and the like.

The algorithm is the result of an analysis of the instantaneous current for a clock cycle, which leads to the synthesis of a discrete average current estimate based on a summation of the individual baseline and non-baseline current components.

The first step in generating the algorithms is to group the functional units according to the primary power consumption dependencies. This is done by considering the physical design of the unit, and considering the function performed by each unit, the inputs and outputs of the unit, and how code execution, as a general matter, affects power consumption by the unit. A useful way of grouping, for example, is as a digital unit, memory unit, or linear unit. Digital units are, for example, control logic, buffers, I/O, multiplier, arithmetic logic unit ("ALU"), serial port, timer, interface logic, etc. Linear units are, for example, differential amplifiers, reference generators, resistor trees, current mirrors, etc.

For the CPU 12 under consideration, for example, it was found that the functional units can be separated into three groups, shown in Table I The units identified as DATAPATH 1 and DATAPATH 2 are the REGFILE 1 and its associated EUs, and REGFILE 2 and its associated EUs, respectively. <tables id="tabl0001" num="0001"><table frame="all"><title>Table I</title><tgroup cols="3" colsep="1" rowsep="1"><colspec colnum="1" colname="col1" colwidth="52.50mm" /><colspec colnum="2" colname="col2" colwidth="52.50mm" /><colspec colnum="3" colname="col3" colwidth="52.50mm" /><thead valign="top"><row rowsep="1"><entry namest="col1" nameend="col1" align="left">Group 1</entry><entry namest="col2" nameend="col2" align="left">Group 2</entry><entry namest="col3" nameend="col3" align="left">Group 3</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">PGEN</entry><entry namest="col2" nameend="col2" align="left">DATAPATH 1</entry><entry namest="col3" nameend="col3" align="left">CR</entry></row><row><entry namest="col1" nameend="col1" align="left">IDU</entry><entry namest="col2" nameend="col2" align="left">DATAPATH 2</entry><entry namest="col3" nameend="col3" align="left">DTP_CCU</entry></row><row><entry namest="col1" nameend="col1" align="left">PREDECODE</entry><entry namest="col2" nameend="col2" /><entry namest="col3" nameend="col3" align="left">MTAP</entry></row><row><entry namest="col1" nameend="col1" align="left">DECODE 1</entry><entry namest="col2" nameend="col2" /><entry namest="col3" nameend="col3" /></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">DECODE 2</entry><entry namest="col2" nameend="col2" /><entry namest="col3" nameend="col3" /></row></tbody></tgroup></table></tables>

Power consumption in the functional units in Group 1 is dependent primarily on how the code is written, i.e., the extent of parallelism in the code, slot assignment of instructions from one clock cycle to the next clock cycle, and the like. Power consumption in the functional units in Group 2 is dependent primarily on how many functional units are exercised during execution phases in the current clock cycle and the previous clock cycle. Finally, power consumption in the functional units in Group 3 is substantially constant, i.e., independent of the code, to within ten percent, which is considered acceptable.

Then, the average baseline components of the total average current are determined. For example, baseline components may arise due to clock switching, e.g., in many of the blocks in the CPU 12. They may also arise from pre-charging activity, e.g., in PLAs. They may arise from intentional DC paths, e.g., voltage dividers.

Then, the non-baseline components of the total average current are determined. These components are determined across the clock cycle. These components may be further segmented into unique intervals of non-baseline activity. Based on these components, a model is developed which quantifies the activity for each interval, wherein each interval represents a different component. The total average current is, then, the sum of all baseline and non-baseline components.

The application of the above methodology to the functional units in CPU 12 will now be explained in detail. Generally, the step of defining/distinguishing the block type by physical design and/or functionality results in an identification of factors that affect power consumption. This is shown clearly in Figure 7, which shows the result of identifying the distinguishing factors for each of the major types of functional units in the IC 10. Note that all units include a baseline component, that may, depending upon the specific design of the unit, be a significant factor or not.

Thus, power consumption for memory 200 is affected by the modes of operation, READ, WRITE and STANDBY. It is also affected by data pattern dependencies, e.g., the specific data values read or written, and the changes in such data values from cycle to cycle.

Power consumption for the I/O 202 is affected by the output capacitance, the number of inputs changing from 0 to 1 and 1 to zero, as well as the number of outputs changing from 0 to 1 and from 1 to zero.

Power consumption for control logic 204 is affected by the number of bits changing on the input signals, the number of bits changing on the control signals and the number of bits changing on the output signals. In addition, different modes of operation, such as receiving data versus processing data, have an affect on power consumption, as well. Pipeline phase differences also have an affect. Appendix 1 presents the role of the various control blocks and functional units for different pipeline phases of the six instruction types.

Power consumption for buffers, such as clock buffers and data buffers 206 is baseline only, if clock buffers, and is affected by the number of bits changing as well, if data buffers.

Power consumption for multipliers, ALUs, etc. 208, is affected by the instruction type from the previous cycle, by the current operation and the data pattern, including the source data for the current operation, as well as factors specific to the particular current operation. This latter component is derived using a math model of the arithmetic or logical algorithm that is implemented in the circuitry, as an indicator of internal node activity. For example, for a functional unit that executes ADD operations, factors include the number of carries, and/or bit changes.

Power consumption for peripherals and interfaces 210, is affected by the number of bit changes of the data pattern, frame size and data size. A frame is a group of data bits that are handled by a particular peripheral or interface.

Power consumption for registers and register files 212, is affected by the number of register READ operations, the number of register WRITE operations, and also by data pattern dependencies (i.e., number of bit changes).

In detail, turning first to Group 1, the derivation of the algorithm for the IDU will now be described. In the IDU, the input signals for non-baseline current activity determination are the program data bus input, from Program Memory. As mentioned above, the CPU 12 is a VLIW core, capable of executing up to eight instructions per clock cycle. The bus for Program Memory fetch is eight 32-bit words wide, to permit a fetch of eight 32-bit instructions in a single cycle.

The output signals for the IDU are the eight instruction bus to the PDU. In the TMS320C60 CPU 12, a parallel, or "p", bit is stripped from each instruction. Therefore, these instructions are only 31 bits wide as output. Also output from the IDU are the Program Address Strobe, for strobing the address to Program Memory, and the Program Data Strobe, for strobing data transfer from Program Memory.

The following data, in Table II are observed using the Power Mill simulator program. Data are in milliamps, "mA". Data are provided for the IDU, and for the CPU 12 as a whole, to permit a determination of the IDU current as a percentage of the total CPU 12 current. <tables id="tabl0002" num="0002"><table frame="all"><title>Table II</title><tgroup cols="7" colsep="1" rowsep="1"><colspec colnum="1" colname="col1" colwidth="22.50mm" /><colspec colnum="2" colname="col2" colwidth="22.50mm" /><colspec colnum="3" colname="col3" colwidth="22.50mm" /><colspec colnum="4" colname="col4" colwidth="22.50mm" /><colspec colnum="5" colname="col5" colwidth="22.50mm" /><colspec colnum="6" colname="col6" colwidth="22.50mm" /><colspec colnum="7" colname="col7" colwidth="22.50mm" /><thead valign="top"><row rowsep="1"><entry namest="col1" nameend="col1" rowsep="0" align="left">Col. 1</entry><entry namest="col2" nameend="col2" align="left">Col. 2</entry><entry namest="col3" nameend="col3" align="left">Col. 3</entry><entry namest="col4" nameend="col4" align="left">Col. 4</entry><entry namest="col5" nameend="col5" align="left">Col. 5</entry><entry namest="col6" nameend="col6" align="left">Col. 6</entry><entry namest="col7" nameend="col7" align="left">Col. 7</entry></row><row><entry namest="col1" nameend="col1" /><entry namest="col2" nameend="col2" align="left">OBSERVED MIN MAX</entry><entry namest="col3" nameend="col3" align="left">NOP (5 cy)</entry><entry namest="col4" nameend="col4" align="left">PM_DT (80 cy)</entry><entry namest="col5" nameend="col5" align="left">FSM loop (34 cy)</entry><entry namest="col6" nameend="col6" align="left">SS_FIR kernel (18 cy)</entry><entry namest="col7" nameend="col7" align="left">RB_FIR 1st 50 cy of t.c.</entry></row></thead><tbody valign="top"><row><entry namest="col1" nameend="col1" align="left">IDU</entry><entry namest="col2" nameend="col2" align="left">18.6 52.96</entry><entry namest="col3" nameend="col3" align="left">20.7</entry><entry namest="col4" nameend="col4" align="left">25.85</entry><entry namest="col5" nameend="col5" align="left">31.29</entry><entry namest="col6" nameend="col6" align="left">24.6</entry><entry namest="col7" nameend="col7" align="left">31.73</entry></row><row><entry namest="col1" nameend="col1" align="left">CPU 12</entry><entry namest="col2" nameend="col2" align="left">100.37 355.48</entry><entry namest="col3" nameend="col3" align="left">105</entry><entry namest="col4" nameend="col4" align="left">122.3</entry><entry namest="col5" nameend="col5" align="left">165</entry><entry namest="col6" nameend="col6" align="left">164.3</entry><entry namest="col7" nameend="col7" align="left">220.1</entry></row><row rowsep="1"><entry namest="col1" nameend="col1" align="left">% CPU</entry><entry namest="col2" nameend="col2" /><entry namest="col3" nameend="col3" align="left">20%</entry><entry namest="col4" nameend="col4" align="left">21%</entry><entry namest="col5" nameend="col5" align="left">19%</entry><entry namest="col6" nameend="col6" align="left">15%</entry><entry namest="col7" nameend="col7" align="left">14%</entry></row></tbody></tgroup></table></tables>

In column 2, minimum and maximum current simulation values for one cycle, observed over all test cycles, are provided, to show the absolute range of current behavior for the unit. In columns 3 through 7, the instruction execution is begun, and allowed to execute over 20 cycles or more, to assure full loading of the pipeline, and "steady-state" conditions for the condition being examined.

Now, it will be recalled that the Group 1 units' power consumption is dependent primarily on how the code is written, i.e., the extent of parallelism in the code, etc. The code blocks run to produce the data in Table II were selected to provide current values that demonstrate the current drawn for a representative cross-section of types of coding, from which the algorithm will be derived. Five test cases were selected: NOP, PM_DT, FSM, SSFIR and RBFIR. A sixth test case was used to understand the effect of varying degrees of instruction parallelism on different blocks for different pipeline phases.

In column 3, the simulation value for current drawn during a series of NOP instructions, averaged over 5 cycles to a single cycle is provided. Averaging over 5 cycles assures an accurate average value, that averages random cycle-to-cycle variations. This operation provides the baseline current consumption for the unit, 20.7 mA per cycle, which can be rounded to 21 mA per cycle.

In column 4, the simulation value for current drawn during a register file data transfer ("PM_DT") test case, averaged over 80 cycles, is provided. This operation is an operation performed by a block of code that effects a data transfer between register files. This block of code is executed in execute packets containing one to three instructions. Assuming the CPU 12 is running at a clock frequency of 200 MHz, this represents an effective MIPs rate of 200 - 600. Averaging over 80 cycles assures that the full block of code is completely executed through the pipeline, for accuracy. The average current per cycle is 25.85 mA.

In column 5, the simulation value for current drawn during execution of a finite state machine ("FSM") block of code is provided. This block of code is executed in execute packets containing one to four instructions. Again, assuming the CPU 12 is running at a clock frequency of 200 MHz, this represents an effective MIPs rate of 400 - 800. The average current per cycle is 31.29 mA.

In column 6, the simulation value for current drawn during execution of a block of code implementing a single sample finite impulse response ("SS_FIR") calculation is provided. The kernel of this block of code contains a single cycle loop that contains an execute packet of eight instructions which perform the multiply-accumulate ("MAC") operations. This inside loop is executed with eight instructions in parallel, representing an effective MIPs rate of 1600 (8 instructions in parallel) for the CPU 12. In addition, since this is a single sample FIR calculation, the data value does not change, so toggle activity within the unit is relatively low. The average current per cycle is 24.6 mA.

Finally, in column 7, the simulation value for current drawn during execution of a block of code implementing a real-block finite impulse response ("RB_FIR") calculation is provided. As with the SS_FIR test case, the kernel of this block of code contains an inside loop that includes execute packets which implement the MAC operations by implementing adds and multiplies in both data paths in parallel. This inside loop is also executed with eight instructions in parallel, representing an effective MIPs rate of 1600. However, since real data is processed, toggle activity within the unit is relatively high. The average current per cycle is 31.73 mA.

Now, from the foregoing data the algorithm for the IDU may be derived. The algorithm is provided below, as a listing of C-code-like statements. Comments are provided at the end of the listing below.<img file="EP0875833A1_D0003.tif" /><img file="EP0875833A1_D0004.tif" /><img file="EP0875833A1_D0005.tif" />

Note that "cc-1" stands for "the previous cycle, "exec packet" stands for "execute packet," and "NBC" stands for "number of bits changing." Also, "mA/BC(cc-1)" stands for the average current per bit changing in the previous cycle. Likewise, "mA/BC(cc)" stands for the average current per bit changing in the current cycle.

The block of lines 3 through 9 represent the case where neither PAS nor PDS are changing, and both are static low. Thus, no new fetch packets are being fetched, i.e., the IDU is not receiving new data from memory.

The block of lines 10 through 32 represent the case where neither PAS nor PDS are changing, and both are static high. In this case, a new fetch packet is fetched to the IDU in every cycle. This is the extreme case of maximum parallel instruction execution.

Relevant comments for selected lines for the above two cases are as follows. Line 3 represents the condition where the IDU is not receiving data from memory. In line 4, MCNOP stands for multi-cycle NOP, which is an instruction that is part of the CPU 12 instruction set. Line 10 represents the condition where there are no transitions in PAS/PDS. Line 16 represents the condition where there is no change in the execute packet from the previous cycle. Line 21 represents the condition where a different execute packet from that of the previous cycle is being operated on in the current cycle. Line 33 represents the condition where PAS/PDS transition from low to high. Line 38 represents the condition where PAS/PDS transition from high to low. Line 39 represents the condition where a different fetch packet is received from Program Memory.

The step in line 22 illustrates quite clearly the relative average current contributions from the baseline condition, <i>A1, A2, A3, A4,</i> and the non-baseline contributions <i>A5, A6</i> (Figure 5). The value of 19 mA represents the baseline current. The term [NBC(cc-1)*mA/BC(cc-1)] represents the <i>A5</i> average current contribution. This represents the current drawn due to bits changes from the previous cycle, as described above in connection with the description of <i>A5</i> in Figure 5. Similarly, the term [NBC(cc) * 0.01mA/BC] represents the <i>A6</i> average current contribution. This represents the current drawn due to the arrival of new data in the present cycle from the Program Memory, which depends on the number of bits changing as a result of the arrival of this new data, as described above in connection with the description of <i>A6</i> in Figure 5.

Thus, the application of the principles of the present invention provide a way of determining the power consumption of an integrated circuit, on a module-by-module and cycle-by-cycle basis, providing visibility into the integrated circuit not heretofore provided. All significant power contribution variables are modeled in the algorithms, and their sensitivities are thereby tracked. Very high accuracy is possible, therefore, by the application of the principles of the present invention in power modeling.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.