Silicon on insulator buried plate trench capacitor

A method of forming a DRAM storage cell with a trench capacitor in an SOI substrate involves forming a field effect transistor (FET) consisting of a source, drain, channel regions in a device layer, a gate oxide layer on the surface of the device layer and a gate electrode over the channel region. The trench capacitor is formed by the following steps: 1) forming a masking layer over the device layer and patterning an opening corresponding to the trench in the masking layer, 2) anisotropically etching a first trench corresponding to the opening in the masking layer to a first depth, through the SC device layer and the buried oxide layer, extending slightly into the substrate body, 3) forming a diffusion barrier collar along the sides of the first trench to the first depth, 4) forming a second trench by anisotropically etching the substrate body exposed by the first trench to a second depth, so that the silicon of substrate body exposed by the second trench becomes a first electrode of the trench capacitor, 5) forming a node dielectric layer on surface of the substrate body exposed by the first trench, 6) forming a doped polysilicon plug in the first and second trench so as to form a second electrode of the trench capacitor, said plug further making contact to the drain region of the FET. A separate substrate contact to the substrate body is formed through the front or backside so as to contact to the first electrode of the capacitor. Oxide isolation regions between adjacent transistors are formed to complete the SOI-DRAM.