QAM receiver with baseband compensation for phase and frequency errors

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION:

0001The present invention relates to a demodulation method and apparatus for performing a quasi-coherent detection of a modulated digital signal using a signal having a fixed frequency and compensating for the phase and frequency of a tentative demodulated signal obtained by the detection.

2. DESCRIPTION OF THE RELATED ART:

0002It is well known that a modulated digital signal can be demodulated by, for example, a coherent detection system is widely used for obtaining ideal demodulation characteristics. By the coherent detection system, a modulated digital signal s(t) is multiplied by <maths id="math0001"><math display="inline"><mrow><mtext>cosωct</mtext></mrow></math><img file="EP0820173A2_D0001.tif" /></maths> (ωc: radian frequency of the carrier), a signal representing the result of the multiplication is filtered by a low-pass filter, and an output from the low-pass filter is used as a baseband signal.

0003In order to perform the coherent detection system, which requires a carrier, various technologies have been proposed, for example, of extracting a suppressed carrier included in a modulated wave from a modulated signal and reproducing the suppressed carrier. In general, a signal having a radian frequency ωc is generated using a demodulated code and the frequency is controlled by a VCO (voltage-controlled oscillator).

0004By a quasi-coherent detection system, to which the present invention is related, a modulated signal is detected using an oscillation signal having a fixed oscillation frequency which is substantially equal to the radian frequency ωc of the carrier and the phase of the tentative demodulated signal generated by the detection is controlled to obtain a determined demodulated signal.

0005One example of the quasi-coherent detection system is described in the United States Patent No. 5,287,067.

0006The system described in the above-mentioned document operates in the following manner.

0007A complex demodulated signal which is received is treated by quadrature detection to generate a tentative complex demodulated signal. The correlation value between the complex demodulated signal and the complex identification signal obtained as a final signal by the quasi-coherent detection system. Based on the correlation value, a frequency error of one symbol cycle (the cycle by which the tentative demodulated signal is input in repetition) is estimated. An initial phase error is estimated based on the frequency error, the tentative complex demodulated signal, and the demodulated determined complex signal. An optimum phase compensation amount is obtained based on the frequency error and the initial phase error. By compensating for the tentative complex demodulated signal in accordance with the optimum phase compensation amount, a determined complex demodulated signal is generated. Based on the determined complex demodulated signal, a complex identification signal is generated.

0008The above-described conventional system involves many points to be improved, such as, for example, reduction in pull-in time (time required to compensate for a phase shift or frequency error) when there is no training signal, improvement in signal quality, and simplification of the entire circuit system. For example, when there is no training signal, a circuit used for performing this system has a complicated configuration including a large number of complex multipliers. Moreover, the number of signals to be processed and the number of processes to be performed during one symbol cycle are excessive. In the case where such a circuit is used for high-speed digital transmission having a high transmission rate, the power consumption of the circuit is excessive.

0009According to the above-described system, the phase shift caused by the frequency error is estimated based on the tentative demodulated signal and the identification signal. Thus, when the identification signal performs erroneous identification due to a noise or the like, the pull-in time of the phase shift is prolonged and signal quality is deteriorated.

0010Furthermore, demodulation of a modulated signal accompanying amplitude change such as QAM (quadrature amplitude modulation) requires a circuit for normalizing the complex signal, an orthogonal coordinate - polar coordinate conversion circuit and a polar coordinate - orthogonal coordinate conversion circuit, which prolongs the signal processing time and enlarges the size of the circuit.

SUMMARY OF THE INVENTION

0011According to one aspect of the invention, a demodulation method for tentatively demodulating a modulated input signal by a signal having a fixed frequency to form a tentative complex demodulated signal and then generating a determined complex demodulated signal from the tentative complex demodulated signal, the method including: step (a) of obtaining a determined complex demodulated signal by compensating for the tentative complex demodulated signal based on an optimum phase compensation amount; step (b) of estimating an optimum frequency compensation amount based on a shift in the optimum phase compensation amount during a predetermined cycle; and step (c) of estimating an immediately subsequent optimum phase compensation amount to be used in the steps (a) and (b) performed in repetition, based on the tentative complex demodulated signal, the determined complex demodulated signal, and the optimum frequency compensation amount.

0012In one embodiment of the invention, the step (c) includes: step (h1) of obtaining a complex error signal which represents a distance between the determined complex demodulated signal obtained by the step (a) and a complex identification signal; step (h2) of obtaining a phase correction direction signal which represents a correction direction or the optimum phase compensation amount, based on the complex error signal and the tentative complex demodulated signal; step (h3) of performing weighting of the phase correction direction signal; step (h4) of obtaining the tentative phase compensation amount based on the optimum frequency compensation amount estimated by the step (b) and the optimum phase compensation amount estimated by the step (c); and step (h5) of obtaining the immediately subsequent optimum phase compensation amount to be used in the steps (a) and (b) performed in repetition, based on the tentative phase compensation amount and the weighted phase correction direction signal.

0013In one embodiment of the invention, the step (h1) includes: step (i1) of obtaining the complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal obtained by the step (a); step (i2) of obtaining a complex error signal which represents a distance between the determined complex demodulated signal and the complex identification signal; step (i3) of determining whether or not each of a real part and an imaginary part of the complex error signal is required, based on the determined complex demodulated signal; and step (i4) of, when either one of the real part or the imaginary part is determined to be required, outputting the real part or the imaginary part which is determined to be required, and when either one of the real part or the imaginary part is determined not to be required, outputting zero in place of the real part or the imaginary part which is determined not to be required.

0014In one embodiment of the invention, the step (b) includes: step (k1) of obtaining a frequency correction direction signal which represents a correction direction of the optimum frequency compensation amount, based on the optimum phase compensation amounts estimated in repetition by the step (c) and the optimum frequency compensation amount estimated by the step (b); step (k2) of performing weighting of the frequency correction direction signal; and step (k3) of estimating an optimum frequency compensation amount to be used in the step (c) by updating the optimum frequency compensation amount estimated by the step (b) based on the weighted frequency correction direction signal.

0015In one embodiment of the invention, the step (k1) includes: step (l1) of obtaining a complex multiplication value by performing complex multiplication of a first optimum phase compensation amount among the optimum phase compensation amounts estimated by the step (c) and the optimum frequency compensation amount estimated by the step (b); step (l2) of obtaining a complex subtraction value by performing complex subtraction of the complex multiplication value from a second optimum phase compensation amount among the optimum phase compensation amounts estimated by the step (c), the second optimum phase compensation amounts being estimated later than the first optimum phase compensation amount; and step (l3) of obtaining a complex multiplication value by performing complex multiplication of the first optimum phase compensation amount and the complex subtraction value.

0016In one embodiment of the invention, the step (k1) includes: step (m1) of obtaining a complex division value by performing complex division of the second optimum phase compensation amount among the optimum phase compensation amounts estimated by the step (c) by the first optimum phase compensation amount which is estimated before the second optimum phase compensation amount by the step (c); and step (m2) of obtaining a complex subtraction value by performing complex subtraction of the optimum frequency compensation amount estimated by the step (b) from the complex division value.

0017In one embodiment of the invention, the step (k1) includes: step (n1) of obtaining an auto-correlation value by performing complex multiplication of the first optimum phase compensation amount estimated by the step (c) and the second optimum phase compensation amount estimated by the step (c) later than the first optimum phase compensation amount; step (n2) of obtaining a square of a magnitude of the first optimum phase compensation amount; step (n3) of obtaining a multiplication value of the square value and the optimum frequency compensation amount estimated by the step (b); and step (n4) of obtaining the multiplication value from the auto-correlation value obtained by the step (n1) by complex subtraction.

0018In one embodiment of the invention, the step (k1) includes: step (o1) of obtaining an auto-correlation value by performing complex multiplication of the optimum phase compensation amounts estimated in repetition by the step (c); and step (o2) of performing complex subtraction of the optimum frequency compensation amount estimated by the step (b) from the auto-correlation value.

0019In one embodiment of the invention, the step (b) includes: step (p1) of obtaining an auto-correlation value by performing complex multiplication of the optimum phase compensation amounts estimated in repetition by the step (c); and step (p2) of performing complex addition of the auto-correlation value and the optimum frequency compensation amount estimated by the step (b) which is weighted.

0020In one embodiment of the invention, the step (h3) is the step of performing weighting based on the optimum frequency compensation amount.

0021In one embodiment of the invention, the step (k1) includes step (r) of smoothing the frequency correction direction signal which represents the correction direction of the optimum frequency compensation amount.

0022In one embodiment of the invention, the step (h3) includes step (t) of smoothing the phase correction direction signal which represents the correction direction of the optimum phase compensation amount based on the optimum frequency compensation amount.

0023In one embodiment of the invention, the step (c) is performed based on the following expression:<maths id="math0002"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>E(n)U*(n)+F(n)H(n)=H(n+1),</mtext></mrow></math><img file="EP0820173A2_D0002.tif" /></maths> where <ul id="ul0001" list-style="none" compact="compact"><li>µ₁ is a step parameter,</li><li>E(n) is a complex error signal,</li><li>H(n) is the optimum phase compensation amount,</li><li>U(n) is the tentative complex demodulated signal,</li><li>U*(n) is a complex conjugate of U(n),</li><li>F(n) is the optimum frequency compensation amount,</li></ul> and <ul id="ul0002" list-style="none" compact="compact"><li>H(n+1) is the immediately subsequent optimum phase compensation amount to be used in the steps (a) and (b) performed in repetition.</li></ul>

0024In one embodiment of the invention, the step (b) is performed based on the following expression:<maths id="math0003"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>[H(n)-F(n)H(n-1)]H*(n-1)+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0003.tif" /></maths> where <ul id="ul0003" list-style="none" compact="compact"><li>µ₂ is a step parameter,</li><li>H(n) and H(n-1) are optimum phase compensation amounts,</li><li>H*(n) is a complex conjugate of H(n),</li><li>F(n) is the optimum frequency compensation amount already estimated, and</li><li>F(n+1) is the optimum frequency compensation amount to be estimated.</li></ul>

0025According to another aspect of the invention, a demodulation method for tentatively demodulating a modulated input signal by a signal having a fixed frequency to form a tentative complex demodulated signal and then generating a determined complex demodulated signal from the tentative complex demodulated signal, the method including: step (a) of obtaining a determined complex demodulated signal by compensating for the tentative complex demodulated signal based on an optimum phase compensation amount; step (d) of obtaining a complex error signal which represents a distance between the determined complex demodulated signal and a complex identification signal; step (b) of estimating an optimum frequency compensation amount based on the determined complex demodulated signal and the complex error signal; and step (c) of estimating an immediately subsequent optimum phase compensation amount to be used in the step (a) performed in repetition, based on the tentative complex demodulated signal, the determined complex demodulated signal, and the optimum frequency compensation amount.

0026In one embodiment of the invention, the step (c) includes: step (h1) of obtaining the complex error signal which represents a distance between the determined complex demodulated signal obtained by the step (a) and a complex identification signal; step (h2) of obtaining a phase correction direction signal which represents a correction direction of the optimum phase compensation amount, based on the complex error signal obtained by the step (h1) and the tentative complex demodulated signal; step (h3) of performing weighting of the phase correction direction signal; step (h4) of obtaining the tentative phase compensation amount based on the optimum frequency compensation amount estimated by the step (b) and the optimum phase compensation amount estimated by the step (c); and step (h5) of obtaining the immediately subsequent optimum phase compensation amount to be used in the step (a) performed in repetition, based on the tentative phase compensation amount and the weighted phase correction direction signal.

0027In one embodiment of the invention, the step (d) includes: step (i1) of obtaining the complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal; step (i2) of obtaining a complex error signal which represents a distance between the determined complex demodulated signal and the complex identification signal; step (i3) of determining whether or not each of a real part and an imaginary part of the complex error signal is required, based on the determined complex demodulated signal; and step (i4) of, when either one of the real part or the imaginary part is determined to be required, outputting the real part or the imaginary part which is determined to be required, and when either one of the real part or the imaginary part is determined not to be required, outputting zero in place of the real part or the imaginary part which is determined not to be required.

0028In one embodiment of the invention, the step (h1) includes: step (i1) of obtaining the complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal; step (i2) of obtaining a complex error signal which represents a distance between the determined complex demodulated signal and the complex identification signal; step (i3) of determining whether or not each of a real part and an imaginary part of the complex error signal is required, based on the determined complex demodulated signal; and step (i4) of, when either one of the real part or the imaginary part is determined to be required, outputting the real part or the imaginary part which is determined to be required, and when either one of the real part or the imaginary part is determined not to be required, outputting zero in place of the real part or the imaginary part which is determined not to be required.

0029In one embodiment of the invention, the step (c) includes: step (j1) of obtaining a complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal; step (j2) of obtaining a cross-correlation value by performing complex multiplication of the tentative complex demodulated signal and the complex identification signal; step (j3) of obtaining a complex addition value by performing complex addition of the cross-correlation value and the optimum phase compensation amount estimated by the step (c) which is weighted; and step (j4) of obtaining a complex multiplication value by performing complex multiplication of the complex addition value and the optimum frequency compensation amount estimated by the step (b).

0030In one embodiment of the invention, the step (b) includes: step (q1) of obtaining a frequency correction direction signal which represents the correction direction of the optimum frequency compensation amount based on the determined complex demodulated signal obtained by the step (a) and the complex error signal obtained by the step (d); step (q2) of performing weighting of the frequency correction direction signal; and step (q3) of updating the optimum frequency compensation amount estimated by the step (b) based on the weighted frequency correction direction signal.

0031In one embodiment of the invention, the step (h3) is the step of performing weighting based on the optimum frequency compensation amount.

0032In one embodiment of the invention, the step (q2) is the step of performing weighting based on the optimum frequency compensation amount.

0033In one embodiment of the invention, the step (q1) includes step (r) of smoothing the frequency correction direction signal which represents the correction direction of the optimum frequency compensation amount.

0034In one embodiment of the invention, the step (h3) includes step (t) of smoothing the phase correction direction signal which represents the correction direction of the optimum phase compensation amount based on the optimum frequency compensation amount.

0035In one embodiment of the invention, the step (c) is performed based on the following expression:<maths id="math0004"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>E(n)U*(n)+F(n)H(n)=H(n+1),</mtext></mrow></math><img file="EP0820173A2_D0004.tif" /></maths> where <ul id="ul0004" list-style="none" compact="compact"><li>µ₁ is a step parameter,</li><li>E(n) is a complex error signal,</li><li>H(n) is the optimum phase compensation amount,</li><li>U(n) is the tentative complex demodulated signal,</li><li>U*(n) is a complex conjugate of U(n),</li><li>F(n) is the optimum frequency compensation amount,</li></ul> and <ul id="ul0005" list-style="none" compact="compact"><li>H(n+1) is the immediately subsequent optimum phase compensation amount to be used in the step (a) performed in repetition.</li></ul>

0036In one embodiment of the invention, the step (b) is performed based on the following expression:<maths id="math0005"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>E(n)U*(n)H*(n)+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0005.tif" /></maths> where <ul id="ul0006" list-style="none" compact="compact"><li>µ₁ and µ₂ step parameters,</li><li>E(n) is a complex error signal,</li><li>H(n) is the optimum phase compensation amount,</li><li>U(n) is the tentative complex demodulated signal,</li><li>U*(n) is a complex conjugate of U(n),</li><li>H*(n) is a complex conjugate of H(n),</li><li>F(n) is the optimum frequency compensation amount already estimated, and</li><li>F(n+1) is the optimum frequency compensation amount to be estimated.</li></ul>

0037According to still another aspect of the invention, a demodulation apparatus for tentatively demodulating a modulated input signal by a signal having a fixed frequency to form a tentative complex demodulated signal and then generating a determined complex demodulated signal from the tentative complex demodulated signal, the apparatus including: means (A) for obtaining a determined complex demodulated signal by compensating for the tentative complex demodulated signal based on an optimum phase compensation amount; means (B) for estimating an optimum frequency compensation amount based on a shift in the optimum phase compensation amount during a predetermined cycle; and means (C) for estimating an immediately subsequent optimum phase compensation amount to be used by means (A) and (B) in repetition, based on the tentative complex demodulated signal, the determined complex demodulated signal, and the optimum frequency compensation amount.

0038In one embodiment of the invention, the means (C) includes: means (H1) for obtaining a complex error signal which represents a distance between the determined complex demodulated signal obtained by the means (A) and a complex identification signal; means (H2) for obtaining a phase correction direction signal which represents a correction direction of the optimum phase compensation amount, based on the complex error signal and the tentative complex demodulated signal; means (H3) for performing weighting of the phase correction direction signal; means (H4) for obtaining the tentative phase compensation amount based on the optimum frequency compensation amount estimated by the means (B) and the optimum phase compensation amount estimated by the means (C); and means (H5) for obtaining the immediately subsequent optimum phase compensation amount to be used by the means (A) and (B) in repetition, based on the tentative phase compensation amount and the weighted phase correction direction signal.

0039In one embodiment of the invention, the means (H1) includes: means (I1) for obtaining the complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal; means (I2) for obtaining a complex error signal which represents a distance between the determined complex demodulated signal and the complex identification signal; means (I3) for determining whether or not each of a real part and an imaginary part of the complex error signal is required, based on the determined complex demodulated signal; and means (I4) for, when either one of the real part or the imaginary part is determined to be required, outputting the real part or the imaginary part which is determined to be required, and when either one of the real part or the imaginary part is determined not to be required, outputting zero in place of the real part or the imaginary part which is determined not to be required.

0040In one embodiment of the invention, the means (B) includes: means (K1) for obtaining a frequency correction direction signal which represents a correction direction of the optimum frequency compensation amount, based on the optimum phase compensation amounts estimated in repetition by the means (C) and the optimum frequency compensation amount estimated by the means (B); means (K2) for performing weighting of the frequency correction direction signal; and means (K3) for estimating an optimum frequency compensation amount to be used by the means (C) by updating the optimum frequency compensation amount estimated by the means (B) based on the weighted frequency correction direction signal.

0041In one embodiment of the invention, the means (K1) includes: means (L1) for obtaining a complex multiplication value by performing complex multiplication of a first optimum phase compensation amount among the optimum phase compensation amounts estimated by means (C) and the optimum frequency compensation amount estimated by the means (B); means (L2) for obtaining a complex subtraction value by performing complex subtraction of the complex multiplication value from a second optimum phase compensation amount among the optimum phase compensation amounts estimated by the means (C), the second optimum phase compensation amounts being estimated later than the first optimum phase compensation amount; and means (L3) for obtaining a complex multiplication value by performing complex multiplication of the first optimum phase compensation amount and the complex subtraction value.

0042In one embodiment of the invention, the means (K1) includes: means (M1) for obtaining a complex division value by performing complex division of the second optimum phase compensation amount among the optimum phase compensation amounts estimated by the means (C) by the first optimum phase compensation amount which is estimated before the second optimum phase compensation amount by the means (C); and means (M2) for obtaining a complex subtraction value by performing complex subtraction of the optimum frequency compensation amount estimated by the means (B) from the complex division value.

0043In one embodiment of the invention, the means (K1) includes: means (N1) for obtaining an auto-correlation value by performing complex multiplication of the first optimum phase compensation amount estimated by the means (C) and the second optimum phase compensation amount estimated by the means (C) later than the first optimum phase compensation amount; means (N2) for obtaining a square of a magnitude of the first optimum phase compensation amount; means (N3) for obtaining a multiplication value of the square value and the optimum frequency compensation amount estimated by the means (B); and means (N4) for obtaining the multiplication value from the auto-correlation value obtained by the means (N1) by complex subtraction.

0044In one embodiment of the invention, the means (K1) includes: means (O1) for obtaining an auto-correlation value by performing complex multiplication of the optimum phase compensation amounts estimated in repetition by the means (C); and means (O2) for performing complex subtraction of the optimum frequency compensation amount estimated by the means (B) from the auto-correlation value.

0045In one embodiment of the invention, the means (B) includes: means (P1) for obtaining an auto-correlation value by performing complex multiplication of the optimum phase compensation amounts estimated in repetition by the means (C); and means (P2) for performing complex addition of the auto-correlation value and the optimum frequency compensation amount estimated by the means (B) which is weighted.

0046In one embodiment of the invention, the means (H3) performs weighting based on the optimum frequency compensation amount.

0047In one embodiment of the invention, the means (K1) includes means (R) for smoothing the frequency correction direction signal which represents the correction direction of the optimum frequency compensation amount.

0048In one embodiment of the invention, the means (H3) includes means (T) for smoothing the phase correction direction signal which represents the correction direction of the optimum phase compensation amount based on the optimum frequency compensation amount.

0049According to still another aspect of the invention, a demodulation apparatus for tentatively demodulating a modulated input signal by a signal having a fixed frequency to form a tentative complex demodulated signal and then generating a determined complex demodulated signal from the tentative complex demodulated signal, the apparatus including: means (A) for obtaining a determined complex demodulated signal by compensating for the tentative complex demodulated signal based on an optimum phase compensation amount; means (D) for obtaining a complex error signal which represents a distance between the determined complex demodulated signal and a complex identification signal; means (B) for estimating an optimum frequency compensation amount based on the determined complex demodulated signal and the complex error signal; and means (C) for estimating an immediately subsequent optimum phase compensation amount to be used by the means (A) and (B) in repetition, based on the tentative complex demodulated signal, the determined complex demodulated signal, and the optimum frequency compensation amount.

0050In one embodiment of the invention, the means (C) includes: means (H1) for obtaining a complex error signal which represents a distance between the determined complex demodulated signal obtained by the means (A) and a complex identification signal; means (H2) for obtaining a phase correction direction signal which represents a correction direction of the optimum phase compensation amount, based on the complex error signal obtained by the means (H1) and the tentative complex demodulated signal; means (H3) for performing weighting of the phase correction direction signal; means (H4) for obtaining the tentative phase compensation amount based on the optimum frequency compensation amount estimated by the means (B) and the optimum phase compensation amount estimated by the means (C); and means (H5) for obtaining the immediately subsequent optimum phase compensation amount to be used by the means (A) in repetition, based on the tentative phase compensation amount and the weighted phase correction direction signal.

0051In one embodiment of the invention, the means (D) includes: means (I1) for obtaining the complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal; means (I2) for obtaining a complex error signal which represents a distance between the determined complex demodulated signal and the complex identification signal; means (I3) for determining whether or not each of a real part and an imaginary part of the complex error signal is required, based on the determined complex demodulated signal; and means (I4) for, when either one of the real part or the imaginary part is determined to be required, outputting the real part or the imaginary part which is determined to be required, and when either one of the real part or the imaginary part is determined not to be required, outputting zero in place of the real part or the imaginary part which is determined not to be required.

0052In one embodiment of the invention, the means (C) includes: means (J1) for obtaining a complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal; means (J2) for obtaining a cross-correlation value by performing complex multiplication of the tentative complex demodulated signal and the complex identification signal; means (J3) for obtaining a complex addition value by performing complex addition of the cross-correlation value and the optimum phase compensation amount estimated by the means (C) which is weighted; and means (J4) for obtaining a complex multiplication value by performing complex multiplication of the complex addition value and the optimum frequency compensation amount estimated by the means (B).

0053In one embodiment of the invention, the means (H1) includes: means (I1) for obtaining the complex identification signal which is closest to the determined complex demodulated signal by identifying the determined complex demodulated signal; means (I2) for obtaining a complex error signal which represents a distance between the determined complex demodulated signal and the complex identification signal; means (I3) for determining whether or not each of a real part and an imaginary part of the complex error signal is required, based on the determined complex demodulated signal; and means (I4) for, when either one of the real part or the imaginary part is determined to be required, outputting the real part or the imaginary part which is determined to be required, and when either one of the real part or the imaginary part is determined not to be required, outputting zero in place of the real part or the imaginary part which is determined not to be required.

0054In one embodiment of the invention, the means (B) includes: means (Q1) for obtaining a frequency correction direction signal which represents the correction direction of the optimum frequency compensation amount based on the determined complex demodulated signal obtained by the means (A) and the complex error signal obtained by the means (D); means (Q2) for performing weighting of the frequency correction direction signal; and means (Q3) for updating the optimum frequency compensation amount estimated by the means (B) based on the weighted frequency correction direction signal.

0055In one embodiment of the invention, the means (H3) performs weighting based on the optimum frequency compensation amount.

0056In one embodiment of the invention, the means (Q2) performs weighting based on the optimum frequency compensation amount.

0057In one embodiment of the invention, the means (Q1) includes means (R) for smoothing the frequency correction direction signal which represents the correction direction of the optimum frequency compensation amount.

0058In one embodiment of the invention, the means (H3) includes means (T) for smoothing the phase correction direction signal which represents the correction direction of the optimum phase compensation amount based on the optimum frequency compensation amount.

0059According to the above-described demodulation method, since a tentative complex demodulated signal generated by demodulating a modulated input signal using a signal having a fixed frequency includes a phase shift or a frequency error, a determined complex demodulated signal is obtained by the compensating for the phase shift or the frequency error of the tentative complex demodulated signal.

0060In this specification, compensating for a phase shift or a frequency error of a tentative complex demodulated signal is also referred to as "compensating for the phase or frequency of the tentative complex demodulated signal" or "compensating for the tentative complex demodulated signal".

0061In accordance with the above-described principle, in step (a), a determined complex demodulated signal is obtained by compensating for the tentative complex demodulated signal based on an optimum phase compensation amount. Then, in step (b), an optimum frequency compensation amount is estimated based on a shift in the optimum phase compensation amount during a predetermined cycle. In step (c), an immediately subsequent optimum phase compensation amount to be used in the steps (a) and (b) performed in repetition is estimated based on the tentative complex demodulated signal, the determined complex demodulated signal, and the optimum frequency compensation amount. By performing complex multiplication of the immediately subsequent optimum phase compensation amount and the next tentative complex demodulated signal, phase compensation and frequency compensation are performed. Such control is performed based on (1) the error between the tentative complex demodulated signal and the complex identification signal and (2) the error between the shift in the optimum phase compensation amount during a predetermined cycle and the optimum frequency compensation amount. As a result of the control, the error in the determined complex demodulated signal is reduced cycle by cycle, and thus a proper complex signal is stably obtained.

0062In the case where the immediately subsequent optimum phase compensation amount is estimated based on the optimum frequency compensation amount, the optimum phase compensation amount and a weighted correction direction signal, the size of the entire circuit system can be reduced.

0063In the case where the optimum frequency compensation amount is estimated based on the optimum phase compensation amounts obtained by estimations performed in repetition, the size of the entire circuit system can be reduced and also the signal processing amount required for one cycle of estimation can be reduced. For demodulating a signal modulated by the QAM system, the optimum frequency compensation amount is estimated using an optimum phase compensation amount having a sufficiently small amplitude change. Accordingly, the optimum frequency compensation amount can be estimated in stable state. Moreover, an AGC function by which the amplitude is controlled with respect to the amplitude change over time can be realized.

0064In the case where the optimum frequency compensation amount is estimated based on the determined complex demodulated signal and a complex error signal, the optimum frequency compensation amount and the optimum phase compensation amount can be estimated in parallel. Thus, the size of the entire circuit system can be reduced and also the signal processing amount required for one cycle of estimation can be reduced.

0065In the case where the complex error signal is selectively used, the pull-in time of the optimum frequency compensation amount can be shortened.

0066In the case where the optimum phase compensation amount is obtained based on the cross-correlation value between the tentative complex demodulated signal and the complex identification signal and also based on the optimum frequency compensation amount, the size of the entire circuit system can be reduced. For demodulating a signal modulated by the QAM system, the optimum frequency compensation amount is estimated using an optimum phase compensation amount having a sufficiently small amplitude change. Accordingly, for demodulating a signal modulated by the M-ary QAM system using the RLS (recursive least squares) algorithm, a circuit for normalizing a complex demodulated signal, or an orthogonal coordinate - polar coordinate conversion circuit or a polar coordinate - orthogonal coordinate conversion circuit which is formed of a ROM or the like is not required. Thus, signal processing time is shortened and the size of the entire circuit system is reduced. Since the circuit for normalizing a complex demodulated signal or a ROM is not required to estimate an optimum frequency compensation amount, an AGC function by which the amplitude is controlled with respect to the amplitude change over time can be realized. When an RLS algorithm is used, optimum phase compensation can be realized at high speed by use of a training signal.

0067In the case where weighting with respect to the phase correction direction signal and the frequency correction direction signal is performed based on the optimum frequency compensation amount, a correction direction signal can be generated in consideration of the frequency error, and thus the range in which the frequency can be corrected can be enlarged.

0068In the case where the frequency correction direction signal is smoothed, noise components can be restricted.

0069In the case where the phase correction direction signal is smoothed based on the optimum frequency compensation amount, noise components can be restricted.

0070Thus, the invention described herein makes possible the advantage of providing a demodulation method and apparatus for compensating for the phase and the frequency of a tentative demodulated signal formed after quasi-coherent detection by a sufficiently simple configuration.

0071These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

0072<ul id="ul0007" list-style="none"><li>Figure <b>1</b> is a block diagram of a demodulation apparatus in a first example according to the present invention;</li><li>Figure <b>2</b> is a block diagram of an optimum phase estimation circuit in the demodulation apparatus shown in Figure <b>1</b>;</li><li>Figure <b>3</b> is a block diagram of a phase shift estimation circuit in the demodulation apparatus shown in Figure <b>1</b>;</li><li>Figure <b>4</b> is a block diagram of a phase error detection circuit in an optimum phase estimation circuit of a demodulation apparatus in a second example according to the present invention;</li><li>Figure <b>5A</b> is a view for illustrating the operation of the phase error detection circuit shown in Figure <b>4</b>, which shows symbols and areas in the in-phase axis direction;</li><li>Figure <b>5B</b> is a view for illustrating the operation of the phase error detection circuit shown in Figure <b>4</b>, which shows symbols and areas in the quadrature axis direction;</li><li>Figure <b>6</b> is a block diagram of a phase shift estimation circuit of a demodulation apparatus in a third example according to the present invention;</li><li>Figure <b>7</b> is a block diagram of a phase shift estimation circuit of a demodulation apparatus in a fourth example according to the present invention;</li><li>Figure <b>8</b> is a block diagram of a phase shift estimation circuit of a demodulation apparatus in a fifth example according to the present invention;</li><li>Figure <b>9</b> is a block diagram of a phase control circuit of a demodulation apparatus including a phase shift estimation circuit and an optimum phase estimation circuit in a sixth example according to the present invention;</li><li>Figure <b>10</b> is a block diagram showing a modification of the phase shift estimation circuit and optimum phase estimation circuit shown in Figure <b>9</b>;</li><li>Figure <b>11</b> is a block diagram of an optimum phase estimation circuit of a demodulation apparatus in a seventh example according to the present invention;</li><li>Figure <b>12</b> is a block diagram of a phase shift estimation circuit of the demodulation apparatus in the seventh example according to the present invention;</li><li>Figure <b>13</b> is a block diagram of a phase control circuit of a demodulation apparatus in an eighth example according to the present invention;</li><li>Figure <b>14A</b> is a block diagram of a weighting circuit in the optimum phase estimation circuit in an optimum phase estimation circuit of a demodulation apparatus in a ninth example according to the present invention;</li><li>Figure <b>14B</b> is a block diagram of a weighting circuit in the optimum phase estimation circuit in an optimum phase estimation circuit of a demodulation apparatus in a tenth example according to the present invention;</li><li>Figure <b>15</b> is a block diagram showing a modification of the phase control circuit shown in Figure <b>13</b>;</li><li>Figure <b>16A</b> is a block diagram of a smoothing circuit in a phase shift estimation circuit of a demodulation apparatus in an eleventh example according to the present invention;</li><li>Figure <b>16B</b> is a block diagram showing a modification of the smoothing circuit shown in Figure <b>16A</b>;</li><li>Figure <b>17A</b> is a block diagram of a smoothing circuit in an optimum phase estimation circuit of a demodulation apparatus in a twelfth example according to the present invention;</li><li>Figure <b>17B</b> is a block diagram showing a modification of the smoothing circuit shown in Figure <b>17A</b>;</li><li>Figure <b>18</b> is a block diagram showing another modification of the phase control circuit shown in Figure <b>13</b>;</li><li>Figure <b>19</b> is a schematic block diagram showing a general configuration of a phase control circuit;</li><li>Figure <b>20</b> is a view showing an orthogonal coordinate system having symbols arranged;</li><li>Figure <b>21</b> is a graph showing a square error in the LMS algorithm;</li><li>Figures <b>22A</b>, <b>22B</b>, <b>22C</b> and <b>22D</b> are graphs used for describing the state of phase error generation when phase control is not performed for the QPSK system;</li><li>Figures <b>23A</b>, <b>23B</b>, <b>23C</b> and <b>23D</b> are graphs used for describing the state of phase error generation when phase control is performed for the QPSK system;</li><li>Figures <b>24A</b>, <b>23B</b>, <b>24C</b> and <b>24D</b> are graphs used for describing the state of phase error generation and frequency error generation when phase control is not performed for the QPSK system;</li><li>Figures <b>25A</b> and <b>25B</b> are graphs illustrating vectors regarding an example of an optimum frequency compensation amount and optimum phase compensation amount; and</li><li>Figures <b>26A</b> and <b>26B</b> are graphs illustrating vectors regarding another example of an optimum frequency compensation amount and optimum phase compensation amount.</li></ul>

DESCRIPTION OF THE PREFERRED EMBODIMENTS

0073Hereinafter, the present invention will be described by way of examples with reference to the attached drawings.

(Example 1)

0074A basic principle of a demodulation method and apparatus in a first example according to the present invention will be described.

0075Generally in a signal processing circuit, an error e(n) generated in an output signal from the signal processing circuit at time n of the "n"th sample of the symbol cycle T can be reduced by optimizing the transmission function h(n) in accordance with the least mean square (LMS) algorithm. By the LMS algorithm, the optimum transmission function h(n+1) at time (n+1) is obtained by expression (0), where x(n) represents the input signal and α represents the step parameter.<maths id="math0006" num="(0)"><math display="block"><mrow><mtext>α·e(n)·x(n)+h(n)=h(n+1)</mtext></mrow></math><img file="EP0820173A2_D0006.tif" /></maths>

0076The above-described LMS algorithm can be adopted for a phase control signal in a quasi-coherent detection system, i.e., a phase control circuit for obtaining a determined demodulated signal by controlling the phase of the tentative demodulated signal generated by demodulation with a frequency which is substantially equal to that of the carrier.

0077Figure <b>19</b> shows a general configuration of such a phase control circuit, which includes a multiplier <b>M1</b>, an identifier <b>D1</b>, and a complex adder <b>A1</b>. In the following description, capital letters represent a complex scalar.

0078A complex demodulated signal U(n), which is generated by tentatively demodulating a signal modulated by a QPSK (quadrature phase shift keying) system using a signal having a fixed frequency, is a baseband signal including an in-phase component and a quadrature component which are separated from each other. When the tentative complex demodulated signal U(n) is input to the complex multiplier <b>M1</b>, the complex multiplier <b>M1</b> compensates for the phase of the tentative complex demodulated signal U(n) by an optimum phase compensation amount H(n) and thus outputs a determined complex modulated signal U(n)H(n).

0079The identifier <b>D1</b> identifies a symbol which is closest to the determined complex demodulated signal U(n)H(n) among the symbols obtained by demodulating the signals modulated by the QPSK system, and outputs an identification signal D(n) representing the resultant symbol.

0080Figure <b>20</b> shows symbols P₁, P₂, P₃ and P₄ in an orthogonal coordinate system. In Figure <b>20</b>, vector OP_n corresponds to the determined complex modulated signal U(n)H(n), and vector OP₁ corresponds to the identification signal D(n). Since the determined complex modulated signal U(n)H(n) is closest to the symbol P₁ in Figure <b>20</b>, the identification signal D(n) representing the symbol P₁ is output from the identifier <b>D1</b>.

0081The complex adder <b>A1</b> performs complex subtraction of the threshold complex demodulated signal U(n)H(n) from the identification signal D(n) and thus outputs an estimated error E(n). The estimated error E(n) can be represented by expression (1).<maths id="math0007" num="(1)"><math display="block"><mrow><mtext>E(n)=D(n)-U(n)H(n)</mtext></mrow></math><img file="EP0820173A2_D0007.tif" /></maths>

0082Although the identification signal D(n) is a signal closest to the determined complex demodulated signal U(n)H(n) herein, the identification signal D(n) may be a training signal.

0083In the LMS algorithm, a square error J(n) is used as the evaluation reference of the estimated error E(n). The optimum phase compensation amount H(n) is updated so as to minimize the estimated error E(n).

0084The square error J(n) can be represented by expression (2) using expression (1).<maths id="math0008" num="(2)"><math display="block"><mrow><msup><mrow><mtext>J(n)=[E(n)]</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msup><mrow><mtext>=[D(n)-U(n)H(n)]</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></math><img file="EP0820173A2_D0008.tif" /></maths>

0085As can be appreciated from expression (2), the square error J(n) and the optimum phase compensation amount H(n) have the secondary function relationship as shown in Figure <b>21</b>. Accordingly, there is a level of the optimum phase compensation amount H(n) at which the square error J(n) is the minimum value Jmin.

0086In the LMS algorithm, the gradient of the characteristic curve of the secondary function regarding the optimum phase compensation amount H(n) at arbitrary time n. By repeating an update operation of adding a small value in the opposite direction to that of the gradient to the optimum phase compensation amount H(n) at every symbol cycle T, the level of the optimum phase compensation amount H(n) at which the secondary function is the minimum value Jmin is obtained.

0087The optimum phase compensation amount H(n) is updated as represented by expression (3), where c is a constant.<maths id="math0009" num="(3)"><math display="block"><mrow><mtext>H(n+1)=H(n)-c∂J(n)/∂H(n)</mtext></mrow></math><img file="EP0820173A2_D0009.tif" /></maths>

0088In order to develop the second term of the right side of expression (3), the estimated error E(n) is divided into a real part E_i(n) and an imaginary part E_q(n) as represented by expression (4). Hereinafter, "_i" represents a real part, and "_q" represents an imaginary part.<maths id="math0010" num="(4)"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><msub><mrow><mtext>E</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>(n)=D</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>(n)-[H</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>(n)U</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>(n)-H</mtext></mrow><mrow><mtext>q</mtext></mrow></msub><msub><mrow><mtext>(n)U</mtext></mrow><mrow><mtext>q</mtext></mrow></msub><mtext>(n)]</mtext></mrow></mtd></mtr><mtr><mtd><mrow><msub><mrow><mtext>E</mtext></mrow><mrow><mtext>q</mtext></mrow></msub><msub><mrow><mtext>(n)=D</mtext></mrow><mrow><mtext>q</mtext></mrow></msub><msub><mrow><mtext>(n)-[H</mtext></mrow><mrow><mtext>q</mtext></mrow></msub><msub><mrow><mtext>(n)U</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>(n)+H</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msub><mrow><mtext>(n)U</mtext></mrow><mrow><mtext>q</mtext></mrow></msub><mtext>(n)]</mtext></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0820173A2_D0010.tif" /></maths>

0089The square error J(n) is represented by expression (5) using E_i(n) and E_q(n).<maths id="math0011" num="(5)"><math display="block"><mrow><msub><mrow><mtext>J(n)=[E</mtext></mrow><mrow><mtext>i</mtext></mrow></msub><msup><mrow><mtext>(n)]</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><msub><mrow><mtext>+[E</mtext></mrow><mrow><mtext>q</mtext></mrow></msub><msup><mrow><mtext>(n)]</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></math><img file="EP0820173A2_D0011.tif" /></maths>

0090The gradient ∂J(n)/∂H(n) of the second term of the right side of expression (3) is obtained using expressions (4) and (5) as represented by expression (6).<maths id="math0012" num="(6)"><math display="block"><mrow><mfrac><mrow><mtext>dJ(n)</mtext></mrow><mrow><mtext>dH(n)</mtext></mrow></mfrac><mtext> = </mtext><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mfrac><mrow><mtext>∂J(n)</mtext></mrow><mrow><mtext>∂Hi(n)</mtext></mrow></mfrac></mtd></mtr><mtr><mtd><mfrac><mrow><mtext>∂J(n)</mtext></mrow><mrow><mtext>∂Hq(n)</mtext></mrow></mfrac></mtd></mtr></mtable></mrow></mfenced><mtext> = </mtext><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>2Ei(n) </mtext><mfrac><mrow><mtext>∂Ei(n)</mtext></mrow><mrow><mtext>∂Hi(n)</mtext></mrow></mfrac><mtext>+2Eq(n)</mtext></mtd><mtd><mfrac><mrow><mtext>∂Eq(n)</mtext></mrow><mrow><mtext>∂Hi(n)</mtext></mrow></mfrac></mtd></mtr><mtr><mtd><mtext>2Ei(n) </mtext><mfrac><mrow><mtext>∂Ei(n)</mtext></mrow><mrow><mtext>∂Hq(n)</mtext></mrow></mfrac><mtext>+2Eq(n)</mtext></mtd><mtd><mfrac><mrow><mtext>∂Eq(n)</mtext></mrow><mrow><mtext>∂Hq(n)</mtext></mrow></mfrac></mtd></mtr></mtable></mrow></mfenced><mspace linebreak="newline" /><mtext> = 2</mtext><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mfrac><mrow><mtext>∂Ei(n)</mtext></mrow><mrow><mtext>∂Hi(n)</mtext></mrow></mfrac></mtd><mtd><mfrac><mrow><mtext>∂Eq(n)</mtext></mrow><mrow><mtext>∂Hi(n)</mtext></mrow></mfrac></mtd></mtr><mtr><mtd><mfrac><mrow><mtext>∂Ei(n)</mtext></mrow><mrow><mtext>∂Hq(n)</mtext></mrow></mfrac></mtd><mtd><mfrac><mrow><mtext>∂Eq(n)</mtext></mrow><mrow><mtext>∂Hq(n)</mtext></mrow></mfrac></mtd></mtr></mtable></mrow></mfenced><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>Ei(n)</mtext></mtd></mtr><mtr><mtd><mtext>Eq(n)</mtext></mtd></mtr></mtable></mrow></mfenced><mspace linebreak="newline" /><mtext> = 2</mtext><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>-Ui(n)</mtext></mtd><mtd><mtext>-Uq(n)</mtext></mtd></mtr><mtr><mtd><mtext>Uq(n)</mtext></mtd><mtd><mtext>-Ui(n)</mtext></mtd></mtr></mtable></mrow></mfenced><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>Ei(n)</mtext></mtd></mtr><mtr><mtd><mtext>Eq(n)</mtext></mtd></mtr></mtable></mrow></mfenced><mspace linebreak="newline" /><mtext> = -2</mtext><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>Ui(n)</mtext></mtd><mtd><mtext>Uq(n)</mtext></mtd></mtr><mtr><mtd><mtext>-Uq(n)</mtext></mtd><mtd><mtext>Ui(n)</mtext></mtd></mtr></mtable></mrow></mfenced><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>Ei(n)</mtext></mtd></mtr><mtr><mtd><mtext>Eq(n)</mtext></mtd></mtr></mtable></mrow></mfenced><mspace linebreak="newline" /><mtext> = -2</mtext><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>Ei(n)</mtext></mtd><mtd><mtext>-Eq(n)</mtext></mtd></mtr><mtr><mtd><mtext>Eq(n)</mtext></mtd><mtd><mtext>Ei(n)</mtext></mtd></mtr></mtable></mrow></mfenced><mfenced open="[" close="]"><mrow><mtable><mtr><mtd><mtext>Ui(n)</mtext></mtd></mtr><mtr><mtd><mtext>-Uq(n)</mtext></mtd></mtr></mtable></mrow></mfenced></mrow></math><img file="EP0820173A2_D0012.tif" /></maths>

0091By substituting the result of expression (6) into expression (3), expressions (7) and (8) are obtained, where µ=2c and µ and 2c are both step parameters.<maths id="math0013"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(7)</mtext><mtd><mrow><mtext>H(n+1)=H(n)+2cE(n)U*(n)</mtext></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(8)</mtext><mtd><mrow><mtext>H(n+1)=H(n)+µ[D(n)-H(n)U(n)]U*(n) </mtext></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0820173A2_D0013.tif" /></maths>

0092The step parameters are set sufficiently small to prevent dispersion of the optimum phase compensation amount H(n) even when noise is added to the tentative complex demodulated signal U(n) and also to stabilize the optimum phase compensation amount H(n) after convergence. U*(n) represents the conjugate complex number of U(n). H*(n) (infra) represents the conjugate complex number of H(n).

0093Expression (8) obtained in the above-described manner is used for updating the optimum phase compensation amount H(n) for controlling the phase using the estimated error E(n) by the LMS algorithm.

0094In the case where, for example, the tentative complex demodulated signal U(n) has an error of phase angle θ with respect to the transmission symbol of the QPSK system, amplitude phase control (APC) can be performed in accordance with expression (8). As shown in Figures <b>23A</b>, <b>23B</b>, <b>23C</b> and <b>23D</b>, at time n (n=0, 1, 2, ... k) at which the tentative complex demodulated signal U(n) is sampled at every symbol cycle T, the error between the identification signal D(n) and the demodulated signal U(n), i.e., the phase angle θ is gradually reduced.

0095In the case where the phase control is not performed, as shown in Figures <b>22A</b>, <b>22B</b>, <b>22C</b> and <b>22D</b>, the phase angle θ between the identification signal D(n) and the demodulated signal U(n) is not improved at sampling time n (n=0, 1, 2, ... k).

0096In the case where the tentative complex demodulated signal U(n) rotates with respect to the transmission symbol of the QPSK system at phase angle δ at every symbol cycle T (the frequency error is included in the tentative complex demodulated signal U(n)), if the phase control is not performed, the phase angle θ between the identification signal D(n) and the demodulated signal U(n) is gradually increased at sampling time n (n=0, 1, 2, ... k) as shown in Figures <b>24A</b>, <b>24B</b>, <b>24C</b> and <b>24D</b>. In other words, phase angle δ is added to phase angle θ at time n=0 at every symbol cycle T.

0097However, in the case where the frequency error is included in the tentative complex demodulated signal U(n), even if the phase control is performed, the optimum phase compensation amount H(n) cannot be accurately estimated for the following reason. The updating amount of the optimum phase compensation amount H(n) for each symbol cycle T in expression (8) relies on the magnitude of the step parameter µ. Since the step parameter µ is set to be sufficiently small to prevent dispersion of the optimum phase compensation amount H(n) for stabilization thereof, the updating amount of the optimum phase compensation amount H(n) for each symbol cycle T is also small. Accordingly, the phase shift larger than the updating amount cannot be compensated for.

0098In order to accurately estimate the optimum phase compensation amount H(n), the frequency error needs to be considered. Under such circumstances, frequency correction is performed for the right side of expression (8) with the provision that the tentative complex demodulated signal U(n) includes the frequency error as well as the phase error. In other words, the optimum phase compensation amount H(n) needs to include an optimum frequency compensation amount F(n) for giving rotation in the opposite direction to the phase angle δ. It is considered that the compensation amount obtained by performing complex multiplication of the optimum phase compensation amount H(n) in expression (8) and the optimum frequency compensation amount F(n) is close to the optimum phase compensation amount H(n+1) at time <maths id="math0014"><math display="inline"><mrow><mtext>t=(n+1)</mtext></mrow></math><img file="EP0820173A2_D0014.tif" /></maths>. Expression (9) represents the LMS algorithm for performing phase control in consideration of the frequency error as described above.<maths id="math0015" num="(9)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>[D(n)-H(n)U(n)]U*(n)+F(n)H(n)=H(n+1)</mtext></mrow></math><img file="EP0820173A2_D0015.tif" /></maths> In expression (9), µ₁ represents a real number and a step parameter of the optimum phase compensation amount H(n).

0099In order to estimate the optimum frequency compensation amount F(n) in accordance with the LMS algorithm, the optimum frequency compensation amount F(n) can be updated based on expression (10).<maths id="math0016" num="(10)"><math display="block"><mrow><msup><mrow><mtext>F(n+1)=F(n)-c∂[Ef(n)]</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>/∂F(n)</mtext></mrow></math><img file="EP0820173A2_D0016.tif" /></maths>

0100In order to develop expression (10), the estimated error Ef(n) of the frequency included in the second term of the right side is obtained in the following manner.

0101Herein, estimation of the optimum frequency compensation amount F(n) refers to obtaining the optimum frequency compensation amount F(n) which, when the tentative complex demodulated signal U(n) including the frequency error rotates by phase angle δ during the symbol cycle T, provides the tentative complex demodulated signal U(n) with the phase angle -δ in the direction opposite to the rotation direction.

0102Where θ(n) is the phase angle of the optimum phase compensation amount H(n), the phase angle -δ in the opposite direction (=∠F(n)) can be represented by shift in the optimum phase compensation amount H(n) during the symbol cycle T as in expression (11).<maths id="math0017" num="(11)"><math display="block"><mrow><mtext>[θ(n)-θ(n-1)]=-δ</mtext></mrow></math><img file="EP0820173A2_D0017.tif" /></maths>

0103Expression (11) can be represented using the optimum phase compensation amount H(n) and the optimum frequency compensation amount F(n) as in expression (12).<maths id="math0018" num="(12)"><math display="block"><mrow><mtext>H(n)-F(n)H(n-1)=0</mtext></mrow></math><img file="EP0820173A2_D0018.tif" /></maths>

0104Expression (12) is valid when the optimum phase compensation amount H(n) and the optimum frequency compensation amount F(n) are accurately estimated and is invalid when optimum frequency compensation amount F(n) is not accurately estimated.

0105Where the estimated error caused when the optimum frequency compensation amount F(n) is not accurately estimated is Ef(n), Ef(n) can be defined by expression (13) based on expression (12).<maths id="math0019" num="(13)"><math display="block"><mrow><mtext>Ef(n)=H(n)-F(n)H(n-1)</mtext></mrow></math><img file="EP0820173A2_D0019.tif" /></maths>

0106By developing expression (10) using expression (13), expression (14) is obtained.<maths id="math0020" num="(14)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>[H(n)-F(n)H(n-1)]H*(n-1)+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0020.tif" /></maths> In expression (14), µ₂ represents a real number and a step parameter.

0107Expression (14) is used for updating the optimum frequency compensation amount F(n) for controlling the phase using the estimated error Ef(n) by the LMS algorithm.

0108By performing phase control based on expression (9) and frequency control based on expression (14), the phase error and the frequency error of the tentative complex demodulated signal U(n) accompanying a frequency error is compensated for and thus a determined complex demodulated signal U(n)H(n) can be obtained. In other words, accurate demodulation can be performed.

0109Figure <b>1</b> shows a demodulation apparatus adopting the above-described basic principle of the first example according to the present invention.

0110As shown in Figure <b>1</b>, a demodulation apparatus includes a quadrature detector <b>1</b>, a local oscillator <b>2</b>, A/D converters <b>3</b> and <b>4</b>, digital transversal filters (DTFs) <b>5</b> and <b>6</b>, and a phase control circuit <b>10</b> represented by the dotted box.

0111The phase control circuit <b>10</b> includes a complex multiplier <b>7</b>, an optimum phase estimation circuit <b>8</b>, and a phase shift estimation circuit <b>9</b>. The thick solid lines in the dotted box indicate signal lines represented by complex scalar, and the thin solid lines outside the dotted box indicate signal lines represented by scalar.

0112In such a configuration, the quadrature detector <b>1</b> receives a modulated input signal S and an oscillation signal from the local oscillator <b>2</b>. The quadrature detector <b>1</b> converts I and Q baseband signals using the oscillation signal. The I and Q baseband signals have quadrature relationship to each other. The I and Q baseband signals are respectively converted into digital signals via the A/D converters <b>3</b> and <b>4</b>, and have waves thereof shaped by the DTFs <b>5</b> and <b>6</b> to be tentative demodulated signals U(n) (in-phase signal ui(n) and quadrature signal uq(n)). The demodulated signals U(n) are input to the phase control circuit <b>10</b>.

0113In the case of the QPSK system, where the original signal of the baseband is d(t) and the frequency of the carrier is f0, the modulated input signal S is represented by <maths id="math0021"><math display="inline"><mrow><mtext>s(2π·f0·t+d(t))</mtext></mrow></math><img file="EP0820173A2_D0021.tif" /></maths>. Where the oscillation frequency of the local oscillator <b>2</b>, the phase of the output obtained by quadrature detection of the modulated input signal S performed using the oscillation signal of the frequency f1 is <maths id="math0022"><math display="inline"><mrow><mtext>2π·Δf·t+d(t)+Φ</mtext></mrow></math><img file="EP0820173A2_D0022.tif" /></maths>.

0114Δf represents the frequency error, Φ represents the initial phase error, and t represents the time, and <maths id="math0023"><math display="inline"><mrow><mtext>Δf=f0-f1=ω/2π</mtext></mrow></math><img file="EP0820173A2_D0023.tif" /></maths>. Where the phase error of the tentative complex demodulated signal U(n) obtained at time n during the symbol cycle T for one symbol is θ1 and the phase error of the complex demodulated signal U(n+1) obtained at time (n+1) is θ2, <maths id="math0024"><math display="inline"><mrow><mtext>ω=(θ2-θ1)/T</mtext></mrow></math><img file="EP0820173A2_D0024.tif" /></maths>.

0115The phase control circuit <b>10</b> is used for obtaining the determined complex demodulated signal U(n) from the tentative demodulated signal U, and compensates for the phase represented by <maths id="math0025"><math display="inline"><mrow><mtext>2π·Δf·t+Φ</mtext></mrow></math><img file="EP0820173A2_D0025.tif" /></maths>.

0116In the phase control circuit <b>10</b>, the tentative complex demodulated signal U(n) is input to the complex multiplier <b>7</b> having a phase rotation function. The complex multiplier <b>7</b> rotates the phase of the tentative complex demodulated signal U(n) in correspondence with <maths id="math0026"><math display="inline"><mrow><mtext>-(2π·Δf·t+Φ)</mtext></mrow></math><img file="EP0820173A2_D0026.tif" /></maths> in accordance with the optimum phase compensation amount H(n) output by the optimum phase estimation circuit <b>8</b>, and outputs a determined complex demodulated signal <maths id="math0027"><math display="inline"><mrow><mtext>H(n)U(n)=V(n)</mtext></mrow></math><img file="EP0820173A2_D0027.tif" /></maths>. The optimum phase compensation amount H(n) is also output to the phase shift estimation circuit <b>9</b>. The phase shift estimation circuit <b>9</b> obtains the optimum frequency compensation amount F(n), which is output to the optimum phase estimation circuit <b>8</b>. The optimum phase estimation circuit <b>8</b> receives the tentative complex demodulated signal U(n), the determined complex demodulated signal V(n) and the optimum frequency compensation amount F(n), and generates an optimum phase compensation amount H(n+1) used for the next processing. At the next processing, i.e., when a tentative complex demodulated signal U(n+1) is input to the complex multiplier <b>7</b>, the optimum phase estimation circuit <b>8</b> sends the optimum phase compensation amount H(n+1) to the complex multiplier <b>7</b>.

0117Figure <b>2</b> is a block diagram showing a configuration of the optimum phase estimation circuit <b>8</b>. The optimum phase estimation circuit <b>8</b> obtains an optimum phase compensation amount H(n+1) based on the optimum frequency compensation amount F(n) and the optimum phase compensation amount H(n) in accordance with the LMS algorithm.

0118The optimum phase estimation circuit <b>8</b>, which is provided for estimating the optimum phase compensation amount H(n+1) represented by expression (9), includes a complex conjugate circuit <b>11</b>, a phase error detection circuit <b>12</b>, a complex multiplier <b>13</b>, a weighting circuit <b>14</b>, a complex adder <b>15</b>, a delay circuit <b>16</b>, and another complex multiplier <b>17</b>. The phase error detection circuit <b>12</b> includes an identifier <b>12-1</b> and a complex subtractor <b>12-2</b>.

0119The complex conjugate circuit <b>11</b> receives the tentative complex demodulated signal U(n) and outputs a complex conjugate demodulated signal U*(n) which acts as a complex conjugate with respect to the tentative complex demodulated signal U(n) to the complex multiplier <b>13</b>.

0120The phase error detection circuit <b>12</b> receives the determined complex demodulated signal V(n) from the complex multiplier <b>7</b>. The determined complex demodulated signal V(n) includes an in-phase signal v_i(n) and a quadrature signal v_q(n). The identifier <b>12-1</b> of the phase error detection circuit <b>12</b> identifies a symbol which is closest to the determined complex demodulated signal V(n) and outputs an identification signal D(n) representing the symbol. The complex subtractor <b>12-2</b> of the phase error detection circuit <b>12</b> performs complex subtraction of the determined complex demodulated signal V(n) from the identification signal D(n) and outputs a complex error signal representing the distance between the identification signal D(n) and the determined complex demodulated signal V(n).

0121The complex multiplier <b>13</b> performs complex multiplication of the complex error signal and the complex conjugate demodulated signal U*(n) and outputs a phase correction direction signal representing the correction direction of the optimum phase compensation to the weighting circuit <b>14</b>. The phase correction direction signal corresponds to a part the first term of the left side of expression (9), i.e., <maths id="math0028"><math display="inline"><mrow><mtext>[D(n)-H(n)U(n)]U*(n)</mtext></mrow></math><img file="EP0820173A2_D0028.tif" /></maths>.

0122The weighting circuit <b>14</b> performs weighting corresponding to the step parameter µ₁ (0&lt;µ₁) with respect to the phase correction direction signal and outputs the resultant value to the complex adder <b>15</b>.

0123The delay circuit <b>16</b> outputs the optimum phase compensation amount H(n) estimated at the previous processing to the complex multiplier <b>17</b>. The complex multiplier <b>17</b> performs complex multiplication of the optimum phase compensation amount H(n) from the delay circuit <b>16</b> and the optimum frequency compensation amount F(n) from the phase shift estimation circuit <b>9</b> and outputs the resultant value to the complex adder <b>15</b>. The complex adder <b>15</b> performs complex addition of the value from the weighting circuit <b>14</b> and the value from the complex multiplier <b>17</b> and outputs the optimum phase compensation amount H(n+1) represented by expression (9) to the delay circuit <b>16</b>. The optimum phase compensation amount H(n+1) is output from the delay circuit <b>16</b> at the next processing, i.e., at time (n+1) at which the tentative complex demodulated signal U(n+1) is received and the optimum phase compensation amount H(n+2) is estimated.

0124Figure <b>3</b> is a block diagram showing the phase shift estimation circuit <b>9</b>. The phase shift estimation circuit <b>9</b> obtains an optimum frequency compensation amount F(n) in accordance with the LMS algorithm.

0125The phase shift estimation circuit <b>9</b>, which is provided for estimating the optimum frequency compensation amount F(n) represented by expression (14), includes a delay circuit <b>18</b>, a complex subtractor <b>19</b>, a complex multiplier <b>20</b>, a complex conjugate circuit <b>21</b>, another complex multiplier <b>22</b>, a weighting circuit <b>23</b>, a complex adder <b>24</b>, and another delay circuit <b>25</b>.

0126The delay circuit <b>18</b> received an optimum phase compensation amount H(n-1) from the optimum phase estimation circuit <b>8</b> at the previous processing, and outputs the optimum phase compensation amount H(n-1) to the complex multiplier <b>20</b> and the complex conjugate circuit <b>21</b> at time n, i.e., at the present processing. The delay circuit <b>25</b> outputs the optimum frequency compensation amount F(n) estimated at the previous processing to the complex multiplier <b>20</b>. The complex multiplier <b>20</b> receives the optimum phase compensation amount H(n-1) from the delay circuit <b>18</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25</b>, performs complex multiplication of the optimum phase compensation amount H(n-1) and the optimum frequency compensation amount F(n), and outputs the resultant value, i.e., F(n)H(n-1) to the complex subtractor <b>19</b>. The complex subtractor <b>19</b> performs complex subtraction of the F(n)H(n-1) from the optimum phase compensation amount H(n) to obtain a phase shift error signal, which is output.

0127The complex conjugate circuit <b>21</b> outputs H*(n-1) which acts as a complex conjugate with respect to the optimum phase compensation amount H(n-1) to the complex multiplier <b>22</b>. The complex multiplier <b>22</b> performs complex multiplication of the phase error signal from the complex subtractor <b>19</b> and the signal H*(n-1) from the complex conjugate circuit <b>21</b> to generate and output a frequency correction direction signal representing the correction direction of the optimum frequency compensation. The frequency correction direction signal corresponds to a part of the first term of the left side of expression (14), i.e., <maths id="math0029"><math display="inline"><mrow><mtext>[H(n)-F(n)H(n-1)]H*(n-1)</mtext></mrow></math><img file="EP0820173A2_D0029.tif" /></maths>.

0128The weighting circuit <b>23</b> performs weighting corresponding to the step parameter µ₂ with respect to the frequency correction direction signal and outputs the resultant value to the complex adder <b>24</b>. The complex adder <b>24</b> performs complex addition of the value from the weighting circuit <b>23</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25</b> and outputs the optimum frequency compensation amount F(n+1) represented by expression (14) to the delay circuit <b>25</b>. The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>25</b> at the next processing, i.e., when the optimum phase compensation amount H(n+1) is input from the optimum phase estimation circuit <b>8</b> and the optimum frequency compensation amount F(n+2) is estimated.

0129The operation of the phase control circuit <b>10</b> in the first example can be summarized as follows. The tentative complex demodulated signal U(n), the determined complex demodulated signal V(n) and the optimum frequency compensation amount F(n) are input to the optimum phase estimation circuit <b>8</b>. The optimum phase compensation amount H(n+1) used for the next processing is obtained based on the optimum phase estimation circuit <b>8</b>, and the optimum phase compensation amount H(n+1) is output to the complex multiplier <b>7</b> and the phase shift estimation circuit <b>9</b> at the next processing.

0130At the next processing, i.e., at time (n+1), the complex multiplier <b>7</b> receives the tentative complex demodulated signal U(n+1) and the optimum phase compensation amount H(n+1), performs complex multiplication thereof, and outputs the determined complex demodulated signal V(n+1). The phase shift estimation circuit <b>9</b> obtains the optimum frequency compensation amount F(n+2) from the optimum phase compensation amounts H(n+1) and H(n) and outputs the optimum frequency compensation amount F(n+1) to the optimum phase estimation circuit <b>8</b>. Accordingly, the optimum phase compensation amount H(n+2) used for the next processing is obtained by the optimum phase estimation circuit <b>8</b>.

0131According to such a configuration, as can be appreciated from expression (9), the optimum phase compensation amount H(n) is estimated based on the tentative complex demodulated signal U(n), the determined complex demodulated signal V(n), and the optimum frequency compensation amount F(n).

0132The demodulation apparatus in the first example requires a smaller number of circuits such as delay circuits, complex multipliers and adders than the conventional apparatus. Accordingly, the entire circuit system can be reduced in size.

0133According to the system in the first example, the optimum phase compensation amount H(n) is used to estimate the optimum frequency compensation amount F(n). In the case where a quadrature amplitude modulated signal is demodulated, the optimum frequency compensation amount F(n) can be estimated in a stable state. Furthermore, since the optimum frequency compensation amount F(n) controls the tentative complex demodulated signal in the amplitude direction as well as in the rotation direction, an AGC function of controlling the amplitude with respect to the amplitude change over time can be realized.

0134In the first example, a signal modulated by the QPSK system is tentatively demodulated by the circuits before the phase control circuit <b>10</b>, namely, circuits from the quadrature detector <b>1</b> up to the DTFs <b>5</b> and <b>6</b>. The present invention is not limited to such a system. Alternatively, a signal modulated by the M-ary QAM system may be tentatively demodulated by the circuits before the phase control circuit <b>10</b> and input to the phase control circuit <b>10</b>. In this case also, a determined demodulated signal can be obtained by the phase control circuit <b>10</b>.

(Example 2)

0135A demodulation apparatus in a second example according to the present invention will be described. Figure <b>4</b> is a block diagram of a phase error detection circuit <b>12A</b> used in place of the phase error detection circuit <b>12</b> in the optimum phase estimation circuit <b>8</b> shown in Figure <b>2</b>. In the demodulation apparatus in the second example, the configuration of the optimum phase estimation circuit <b>8</b>, except for the phase error detection circuit <b>12A</b> and the phase shift estimation circuit <b>9</b>, is identical with configurations of those in the first example (see Figures <b>1</b>, <b>2</b> and <b>3</b>).

0136The phase error detection circuit <b>12A</b> includes an identifier <b>12A-1</b>, a complex subtractor <b>12A-2</b>, an evaluation function circuit <b>12A-3</b>, and a switch <b>12A-4</b>. The phase error detection circuit <b>12A</b> is different from the phase error detection circuit <b>12</b> shown in Figure <b>2</b> in further including the evaluation function circuit <b>12A-3</b> for independently evaluating an in-phase signal v_i(n) and a quadrature signal v_q(n) of the determined complex demodulated signal V(n) and the switch circuit <b>12A-4</b> for controlling the output from the complex subtractor <b>12A-2</b> using a complex control signal output from the evaluation function circuit <b>12A-3</b>.

0137In the case where a signal modulated by the 64-bit QAM system is tentatively demodulated into a tentative demodulated signal U(n) and input to the phase control circuit <b>10</b>, and a tentative demodulated signal V(n) is generated from the tentative demodulated signal U(n), the evaluation function circuit <b>12A-3</b> evaluates the position of the determined demodulated signal V(n) with respect to 64 symbols arranged as shown in Figures <b>5A</b> and <b>5B</b>.

0138Figure <b>5A</b> shows areas (shaded areas and unshaded areas) used for determining the position of the in-phase signal v_i(n) in an in-phase direction. Figure <b>5B</b> shows areas (shaded areas and unshaded areas) used for determining the position of the quadrature signal v_q(n) in a quadrature direction. In Figures <b>5A</b> and <b>5B</b>, letter <b>A</b> represents a value obtained by dividing the sum of squares of the distances between the origin and 6A QAM symbols by the sum of the distances between the origin and the 64 QAM symbols.

0139In the case where there is an in-phase signal v_i(n) in any of the lined areas shown in Figure <b>5A</b>, the error ratio for generating an identification signal by identifying the in-phase signal v_i(n) increases. In the case where there is an in-phase signal v_i(n) in any of the blank areas in Figure <b>5A</b>, the error ratio for identifying the in-phase signal v_i(n) decreases. In the same manner, in the case where there is a quadrature signal v_q(n) in any of the lined areas shown in Figure <b>5B</b>, the error ratio for identifying the quadrature signal v_q(n) increases. In the case where there is a quadrature signal v_q(n) in any of the blank areas in Figure <b>5B</b>, the error ratio for identifying the quadrature signal v_q(n) decreases.

0140The switch circuit <b>12A-4</b> receives the in-phase signal v_i(n) and the quadrature signal v_q(n) from the complex subtractor <b>12A-2</b> separately, and outputs either one of the in-phase signal v_i(n) or the ground level, and either one of the quadrature signal v_q(n) or the ground level.

0141The phase error detection circuit <b>12A</b> operates in the following manner. The determined complex demodulated signal V(n) is input to the identifier <b>12A-1</b>, the complex subtractor <b>12A-2</b> and the evaluation function circuit <b>12A-3</b>. The identifier <b>12A-1</b> identifies a symbol which is closest to the determined complex demodulated signal V(n) and outputs an identification signal D(n) representing the symbol. The complex subtractor <b>12A-2</b> performs complex subtraction of the determined complex demodulated signal V(n) from the identification signal D(n) and outputs a complex error signal representing the distance between the identification signal D(n) and the determined complex demodulated signal V(n).

0142The evaluation function circuit <b>12A-3</b> receives the determined complex demodulated signal V(n). When an in-phase signal v_i(n) is in any of the lined areas in Figure <b>5A</b>, the evaluation function circuit <b>12A-3</b> adds a high level signal to the switch <b>12A-4</b>. In response to the high level signal, the switch <b>12A-4</b> selects and outputs the in-phase signal v_i(n) from the complex subtractor <b>12A-2</b>. When an in-phase signal v_i(n) is in any of the blank areas in Figure <b>5A</b>, the evaluation function circuit <b>12A-3</b> adds a low level signal to the switch <b>12A-4</b>. In response to the low level signal, the switch <b>12A-4</b> selects and outputs the ground level.

0143When a quadrature signal v_q(n) is in any of the lined areas in Figure <b>5B</b>, the evaluation function circuit <b>12A-3</b> adds a high level signal to the switch <b>12A-4</b>. In response to the high level signal, the switch <b>12A-4</b> selects and outputs the quadrature signal v_q(n) from the complex subtractor <b>12A-2</b>. When a quadrature signal v_q(n) is in any of the blank areas in Figure <b>5B</b>, the evaluation function circuit <b>12A-3</b> adds a low level signal to the switch <b>12A-4</b>. In response to the low level signal, the switch <b>12A-4</b> selects and outputs the ground level.

0144Due to such a system, the phase error detection circuit <b>12A</b> outputs "0" as a complex error signal when the determined complex demodulated signal V(n) is in any of the blank areas, which indicates the error ratio for identifying the determined complex demodulated signal V(n) increases. Accordingly, update of the coefficient (optimum phase compensation amount H(n) and the optimum frequency compensation amount F(n)) based on a wrong complex error signal can be prevented. Thus, the pull-in time can be shortened, and the amplitude of the determined complex demodulated signal V(n) can be stabilized.

(Example 3)

0145A basic principle of a demodulation method and apparatus in a third example according to the present invention will be described.

0146In the third example, expression (14) is modified as described below to obtain expression (17). The processing is performed based on expression (17). Since expression (14) is used for the phase shift estimation circuit 9 shown in Figure 3, expression (17) is used for obtaining the optimum frequency compensation amount F(n) in a similar manner.

0147First, the first term of the left side of expression (14) is developed to obtain expression (15).<maths id="math0030" num="(15)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msup><mrow><mtext>[H(n)H*(n-1)-F(n)|H(n-1)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>]+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0030.tif" /></maths>

0148By normalizing the part inside "[]" of expression (15) with |H(n-1)|², expression (16) is obtained.<maths id="math0031" num="(16)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msup><mrow><mtext>|H(n-1)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>[{H(n)/H(n-1)}-F(n)]+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0031.tif" /></maths>

0149The value of the step parameter µ₂ for adjusting the updating amount of the optimum frequency compensation amount F(n) is arbitrary. Accordingly, by replacing µ₂|H(n-1)|² with the step parameter µ₃, expression (17) is obtained.<maths id="math0032" num="(17)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>3</mtext></mrow></msub><mtext>[{H(n)/H(n-1)}-F(n)]+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0032.tif" /></maths>

0150The first term of the left side of expression (16) and that of expression (17) have different updating amounts but an identical updating direction of the coefficient (optimum phase compensation amount H(n) and optimum frequency compensation amount F(n)).

0151Figure <b>6</b> is a block diagram of a phase shift estimation circuit <b>9A</b> adopting the above-described basic principle in the third example. The configuration of the optimum phase estimation circuit <b>8</b> in the third example is identical with the configuration shown in Figure <b>2</b> and the configuration in which the phase error detection circuit <b>12</b> in Figure <b>2</b> is replaced with the phase error detection circuit <b>12A</b> in Figure <b>4</b>.

0152The phase shift estimation circuit <b>9A</b> includes a delay circuit <b>18A</b>, a complex subtractor <b>19A</b>, a complex divider <b>20A</b>, a weighting circuit <b>23A</b>, a complex adder <b>24A</b>, and a delay circuit <b>25A</b>. The phase shift estimation circuit <b>9A</b> is different from the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b> in including the complex divider <b>20A</b> in place of the complex multipliers <b>20</b> and <b>22</b> and the complex conjugate circuit <b>21</b>.

0153The complex divider <b>20A</b> receives the optimum phase compensation amount H(n) and also receives the optimum phase compensation amount H(n+1) used for the previous processing via the delay circuit <b>18A</b>, performs complex division of the optimum phase compensation amount H(n) by the optimum phase compensation amount H(n-1), and outputs the resultant value to the complex subtractor <b>19A</b>. The delay circuit <b>25A</b> outputs the optimum frequency compensation amount F(n) estimated by the previous processing to the complex subtractor <b>19A</b>. The complex subtractor <b>19A</b> receives the output from the complex divider <b>20A</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25A</b>, performs complex subtraction of the optimum frequency compensation amount F(n) from the output obtained by the complex divider <b>20A</b>, and generates and outputs a frequency correction direction signal. The frequency correction direction signal corresponds a part of the first term of the left side of expression (17), i.e., [<maths id="math0033"><math display="inline"><mrow><mtext>{H(n)/H(n-1)}-F(n)</mtext></mrow></math><img file="EP0820173A2_D0033.tif" /></maths>].

0154The weighting circuit <b>23A</b> performs weighting corresponding to the step parameter µ₃ with respect to the frequency correction direction signal. The resultant value is output to the complex adder <b>24A</b>. The complex adder <b>24A</b> performs complex addition of the value from the weighting circuit <b>23A</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25A</b>, and outputs the optimum frequency compensation amount F(n+1) to the delay circuit <b>25A</b>. The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>25A</b> at the next processing, i.e., at time (n+1) when the optimum phase compensation amount H(n+1) is input from the optimum phase estimation circuit <b>8</b> and the optimum frequency compensation amount F(n+2).

0155As described above, the phase shift estimation circuit <b>9A</b> in the third example can estimate the optimum frequency compensation amount F(n+1) as in the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b> and also simplifies and reduces the size of the entire circuit system by providing the complex divider <b>20A</b> in place of the complex multipliers <b>20</b> and <b>22</b> and the complex conjugate circuit <b>21</b>.

(Example 4)

0156Figure <b>7</b> is a block diagram of a phase shift estimation circuit <b>9B</b> in a fourth example according to the present invention. The phase shift estimation circuit <b>9B</b> is provided in place of the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b> or the phase shift estimation circuit <b>9A</b> shown in Figure <b>6</b>. The configuration of the optimum phase estimation circuit <b>8</b> in the fourth example is identical with the configuration shown in Figure <b>2</b> and the configuration in which the phase error detection circuit <b>12</b> in Figure <b>2</b> is replaced with the phase error detection circuit <b>12A</b> in Figure <b>4</b>.

0157The phase shift estimation circuit <b>9B</b> includes a delay circuit <b>18B</b>, a complex subtractor <b>19B</b>, an absolute value square circuit <b>20B</b>, a complex conjugate circuit <b>21B</b>, a complex multiplier <b>22B</b>, a weighting circuit <b>23B</b>, a complex adder <b>24B</b>, a delay circuit <b>25B</b>, and another weighting circuit <b>26B</b>. The phase shift estimation circuit <b>9B</b> is different from the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b> in including the absolute value square circuit <b>20B</b> and the weighting circuit <b>26B</b> in place of the complex multiplier <b>20</b>.

0158In such a configuration, the delay circuit <b>18B</b> received the optimum phase compensation amount H(n-1) at the previous processing and outputs the optimum phase compensation amount H(n-1) to the absolute value square circuit <b>20B</b> and the complex conjugate circuit <b>21B</b> at the present processing. The complex conjugate circuit <b>21B</b> outputs H*(n-1) which acts as a complex conjugate with respect to the optimum phase compensation amount H(n-1) to the absolute value square circuit <b>20B</b> and the complex multiplier <b>22B</b>. The absolute value square circuit <b>20B</b> obtains a square of the magnitude of the optimum phase compensation amount based on the optimum phase compensation amount H(n-1) and H*(n-1), and outputs the scalar |H(n-1)|² to the weighting circuit <b>26B</b>. The delay circuit <b>25B</b> outputs the optimum frequency compensation amount F(n) estimated by the previous processing to the weighting circuit <b>26B</b> and the complex adder <b>24B</b>. The weighting circuit <b>26B</b> performs weighting of the optimum frequency compensation amount F(n) based on the scalar |H(n-1)|² from the absolute value square circuit <b>20B</b>, and outputs the resultant value to the complex subtractor <b>19B</b>.

0159The complex multiplier <b>22B</b> performs complex multiplication of the optimum phase compensation amount H(n) and H*(n-1) from the complex conjugate circuit <b>21B</b>, and outputs the resultant value to the complex subtractor <b>19B</b>. The complex subtractor <b>19B</b> performs complex subtraction of the value obtained by the weighting circuit <b>26B</b> from the value obtained by the complex multiplier <b>22B</b>, and thus generates and outputs a frequency correction direction signal. The frequency correction direction signal corresponds to a part of the first term of the left side of expression (14), i.e., <maths id="math0034"><math display="inline"><mrow><mtext>[H(n)-F(n)H(n- 1)]H*(n-1)</mtext></mrow></math><img file="EP0820173A2_D0034.tif" /></maths>.

0160The weighting circuit <b>23B</b> performs weighting corresponding to the step parameter µ₂ with respect to the frequency correction direction signal, and outputs the resultant value to the complex adder <b>24B</b>. The complex adder <b>24B</b> performs complex addition of the value from the weighting circuit <b>23B</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25B</b>, and outputs the optimum frequency compensation amount F(n+1) represented by expression (14) to the delay circuit <b>25B</b>. The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>25B</b> at the next processing, i.e., time (n+1) when the optimum phase compensation amount H(n+1) is input from the optimum phase estimation circuit <b>8</b> and the optimum frequency compensation amount F(n+2) is estimated.

0161As described above, the phase shift estimation circuit <b>9B</b> in the fourth example can estimate the optimum frequency compensation amount F(n+1) as in the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b>, and also simplifies and reduces the size of the entire circuit system by providing the absolute value square circuit <b>20B</b> and the weighting circuit <b>26B</b> in place of the complex multiplier <b>20</b>. Moreover, since the processing performed by the complex multiplier <b>22B</b> and the absolute value square circuit <b>20B</b> and the processing performed by the weighting circuit <b>26B</b> are conducted in parallel, signal processing can be performed at higher speed. Since one complex multiplier includes two adders and four multipliers, elimination of even one complex multiplier significantly contributes to the size reduction of the entire circuit system.

(Example 5)

0162A basic principle of a demodulation method and apparatus in a fifth example according to the present invention will be described.

0163In the fifth example, expression (14) is modified as described below to obtain expression (18). The processing is performed based on expression (18). Since expression (14) is used for the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b>, expression (18) is used for obtaining the optimum frequency compensation amount F(n) in a similar manner.

0164First, expression (15) obtained by developing the first term of the left side of expression (14) is the following.<maths id="math0035" num="(15)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msup><mrow><mtext>[H(n)H*(n-1)-F(n)|H(n-1)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>]+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0035.tif" /></maths>

0165In order to control the phase of a signal modulated by an M-ary PSK (phase shift keying) system, it can be considered that <maths id="math0036"><math display="inline"><mrow><msup><mrow><mtext>|H(n-1)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>≒1</mtext></mrow></math><img file="EP0820173A2_D0036.tif" /></maths>.

0166By substituting 1 to |H(n-1)|² in expression (15), expression (18) is obtained.<maths id="math0037" num="(18)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>[H(n)H*(n-1)-F(n)]+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0037.tif" /></maths>

0167Figure <b>8</b> is a block diagram of a phase shift estimation circuit <b>9C</b> adopting the above-described basic principle in the fifth example. The configuration of the optimum phase estimation circuit <b>8</b> in the fifth example is identical with the configurations shown in Figure <b>2</b> and the configuration in which the phase error detection circuit <b>12</b> in Figure <b>2</b> is replaced with the phase error detection circuit <b>12A</b> in Figure <b>4</b>.

0168The phase shift estimation circuit <b>9C</b> includes a delay circuit <b>18C</b>, a complex subtractor <b>19C</b>, a complex conjugate circuit <b>21C</b>, a complex multiplier <b>22C</b>, a weighting circuit <b>23C</b>, a complex adder <b>24C</b>, and a delay circuit <b>25C</b>. The phase shift estimation circuit <b>9C</b> is different from the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b> in excluding the complex multiplier <b>20</b>.

0169In such a configuration, the delay circuit <b>18C</b> received the optimum phase compensation amount H(n-1) at the previous processing and outputs the optimum phase compensation amount H(n-1) to the complex conjugate circuit <b>21C</b> at the present processing. The complex conjugate circuit <b>21C</b> outputs H*(n-1) which acts as a complex conjugate with respect to the optimum phase compensation amount H(n-1) to the complex multiplier <b>22C</b>. The complex multiplier <b>22C</b> performs complex multiplication of the optimum phase compensation amount H(n) and H*(n-1) from the complex conjugate circuit <b>21C</b>, and outputs the resultant value to the complex subtractor <b>19C</b>. The delay circuit <b>25C</b> outputs the optimum frequency compensation amount F(n) estimated by the previous processing to the complex subtractor <b>19C</b> and the complex adder <b>24C</b>. The complex adder <b>19C</b> performs complex subtraction of the optimum frequency compensation amount F(n) obtained by the delay circuit <b>25C</b> from the value obtained by the complex multiplier <b>22C</b>, and thus generates and outputs a frequency correction direction signal. The frequency correction direction signal corresponds to a part of the first term of the left side of expression (18), i.e., [<maths id="math0038"><math display="inline"><mrow><mtext>H(n)H*(n-1)-F(n)</mtext></mrow></math><img file="EP0820173A2_D0038.tif" /></maths>].

0170The weighting circuit <b>23C</b> performs weighting corresponding to the step parameter µ₂ with respect to the frequency correction direction signal, and outputs the resultant value to the complex adder <b>24C</b>. The complex adder <b>24C</b> performs complex addition of the value from the weighting circuit <b>23C</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25C</b>, and outputs the optimum frequency compensation amount F(n+1) represented by expression (18) to the delay circuit <b>25C</b>. The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>25C</b> at the next processing, i.e., time (n+1) when the optimum phase compensation amount H(n+1) is input from the optimum phase estimation circuit <b>8</b> and the optimum frequency compensation amount F(n+2) is estimated.

0171As described above, the phase shift estimation circuit <b>9C</b> in the fifth example, when used for a signal modulated by the M-ary PSK system, can estimate the optimum frequency compensation amount F(n+1) as in the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b>, and also simplifies and reduces the size of the entire circuit system by eliminating the complex multiplier <b>20</b>.

(Example 6)

0172A basic principle of a demodulation method and apparatus in a sixth example according to the present invention will be described.

0173In the sixth example, expression (10) is modified as described below to obtain expression (20). The processing is performed based on expression (20). Since expression (10) is used for the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b>, expression (20) is used for obtaining the optimum frequency compensation amount F(n) in a similar manner.

0174First, expression (13) which defines the estimated error Ef(n) is the following.<maths id="math0039" num="(13)"><math display="block"><mrow><mtext>Ef(n)=H(n)-F(n)H(n-1)</mtext></mrow></math><img file="EP0820173A2_D0039.tif" /></maths>

0175Expression (13) defines the estimated error Ef(n) at time n as change in the optimum phase compensation amount H(n) and the optimum phase compensation amount H(n-1). In the sixth example, the estimated error Ef(n) is defined as change in the optimum phase compensation amount H(n+1) and the optimum phase compensation amount H(n). Accordingly, expression (13) is replaced by expression (19).<maths id="math0040" num="(19)"><math display="block"><mrow><mtext>Ef(n)=H(n+1)-F(n)H(n)</mtext></mrow></math><img file="EP0820173A2_D0040.tif" /></maths>

0176By modifying expression (10) using expression (19), expression (20) is obtained.<maths id="math0041" num="(20)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>[H(n+1)-F(n)H(n)]H*(n)+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0041.tif" /></maths>

0177Figure <b>9</b> is a block diagram of a phase control circuit <b>10A</b> which includes a phase shift estimation circuit <b>9D-1</b> adopting the above-described basic principle in the sixth example. The phase shift estimation circuit <b>9D-1</b> is combined with the optimum phase estimation circuit <b>8</b> in the phase control circuit <b>10A</b>. In the phase shift estimation circuit <b>9D-1</b>, the delay circuit <b>18</b> and the complex multiplier <b>20</b> in the phase shift estimation circuit <b>9</b> are eliminated. The operation of the optimum phase estimation circuit <b>8</b> in the sixth example is identical with the configurations shown in Figure <b>2</b> and the configuration in which the phase error detection circuit <b>12</b> in Figure <b>2</b> is replaced with the phase error detection circuit <b>12A</b> in Figure <b>4</b>. The optimum phase compensation amount H(n) is estimated based on expression (9).

0178In Figure <b>9</b>, elements having the same functions as those in Figures <b>2</b> and <b>3</b> bear identical reference numerals therewith.

0179In such a configuration, the weighting circuit <b>14</b> performs weighting corresponding to the step parameter µ₁ with respect to a phase correction direction signal, and outputs the resultant value to the complex adder <b>15</b>. The delay circuit <b>25</b> outputs the optimum frequency compensation amount F(n) estimated by the previous processing to the complex multiplier <b>17</b>. The delay circuit <b>16</b> outputs the optimum phase compensation amount H(n) estimated by the previous processing to the complex multiplier <b>17</b>. The complex multiplier <b>17</b> performs complex multiplication of the optimum frequency compensation amount F(n) from the delay circuit <b>25</b> and the optimum phase compensation amount H(n) from the delay circuit <b>16</b>, and outputs F(n)H(n) to the complex adder <b>15</b>. The complex adder <b>15</b> performs complex addition of the value from the weighting circuit <b>14</b> and the value from the complex multiplier <b>17</b>, and outputs the optimum phase compensation amount H(n+1) represented by expression (9) to the delay circuit <b>16</b> and the complex subtractor <b>19</b>. The optimum phase compensation amount H(n+1) is output from the delay circuit <b>16</b> at the next processing.

0180The complex subtractor <b>19</b> performs complex subtraction of the value F(n)H(n) obtained by the complex multiplier <b>17</b> from the optimum phase compensation amount H(n+1) obtained by the complex adder <b>15</b>, and outputs the resultant value to the complex multiplier <b>22</b>. The complex conjugate circuit <b>21</b> outputs H*(n) which acts as a complex conjugate with respect to the optimum phase compensation amount H(n) to the complex multiplier <b>22</b>. The complex multiplier <b>22</b> performs complex multiplication of the value from the complex subtractor <b>19</b> and H*(n) from the complex conjugate circuit <b>21</b>, and thus generates and outputs a frequency correction direction signal which indicates a frequency correction direction. The frequency correction direction signal corresponds to a part of the first term of the left side of expression (20), i.e., <maths id="math0042"><math display="inline"><mrow><mtext>[H(n+1)-F(n)H(n)]H*(n)</mtext></mrow></math><img file="EP0820173A2_D0042.tif" /></maths>.

0181The weighting circuit <b>23</b> outputs the resultant value to the complex adder <b>24</b>. The complex adder <b>24</b> performs complex addition of the value from the weighting circuit <b>23</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25</b>, and outputs the optimum frequency compensation amount F(n+1) represented by expression (20). The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>25</b> at the next processing.

0182As described above, the phase shift estimation circuit <b>9D-1</b> in the sixth example, which estimates one delay circuit and one complex multiplier from the circuit shown in Figure <b>3</b>, simplifies and reduces the size of the entire circuit system. Since the optimum frequency compensation amount F(n+1) is estimated based on expression (20), only H(n+1), F(n) and H(n) are required. Since H(n-1) is not required as opposed to the case of expression (14), the delay circuit <b>18</b> can be eliminated. Thus, the pull-in time is shortened and accurate phase correction is realized.

0183Figure <b>10</b> is a block diagram of a phase control circuit <b>10B</b>, which is obtained by modifying the phase shift estimation circuit <b>9D-2</b> and the optimum phase estimation circuit <b>8</b>.

0184In the phase control circuit <b>10B</b>, the complex subtractor <b>19</b> is eliminated, and the value obtained by the weighting circuit <b>19</b> is directly input to the complex multiplier <b>22</b>. The value output by the complex subtractor <b>19</b> in Figure <b>9</b> is obtained by subtracting the value output by the complex multiplier <b>17</b> from the sum of the values output by the complex multiplier <b>17</b> and the weighting circuit <b>14</b>. Accordingly, the value output by the complex subtractor <b>19</b> in Figure <b>9</b> equals to the value output by the weighting circuit <b>14</b>. Thus, the value sent by the weighting circuit <b>14</b> can be directly input to the complex multiplier <b>22</b>.

(Example 7)

0185A basic principle of a demodulation method and apparatus in a seventh example according to the present invention will be described.

0186In the first through sixth examples, the optimum phase compensation amount H(n) and the optimum frequency compensation amount F(n) are estimated in accordance with the LMS algorithm. In the seventh example, the optimum phase compensation amount H(n) and the optimum frequency compensation amount F(n) are estimated in accordance with an RLS (recursive least squares) algorithm.

0187According to the RLS algorithm, where the auto-correlation function of the tentative complex demodulated signal U(n) at time n is Φ(n) (scalar) and the cross-correlation function of the tentative complex demodulated signal U(n) and the identification signal D(n) at time n is Θ(n) (complex scalar), expressions (21) and (22) are valid.<maths id="math0043"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(21)</mtext><mtd><mrow><msub><mrow><mtext>Φ(n)=λ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>Φ(n-1)+U(n)U*(n)</mtext><mspace linebreak="newline" /><msub><mrow><mtext> =λ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msup><mrow><mtext>Φ(n-1)+|U(n)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(22)</mtext><mtd><mrow><msub><mrow><mtext>Θ(n)=F(n)[λ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>Θ(n-1)+D(n)U*(n)] </mtext></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0820173A2_D0043.tif" /></maths> In expressions (21) and (22), λ₁ represents a real number and a weighting coefficient of the optimum phase compensation amount H(n).

0188In this case, the optimum phase compensation amount H(n) is represented by expression (23).<maths id="math0044" num="(23)"><math display="block"><mrow><msub><mrow><mtext>H(n+1)=Θ(n)/Φ(n) ={F(n)[λ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>Θ(n-1)+D(n)U*(n)]}/{λ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msup><mrow><mtext>Φ(n-1)+|U(n)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup><mtext>}</mtext></mrow></math><img file="EP0820173A2_D0044.tif" /></maths>

0189In the seventh example, the optimum phase compensation amount H(n) is estimated based on expression (23).

0190Where the auto-correlation function of the optimum phase compensation amount H(n) at time n is Φ_f(n) and the auto-correlation function between two adjacent symbols is Θ_f(n), expressions (24) and (25) are valid.<maths id="math0045"><math display="block"><mrow><mtable><mtr><mtd><mrow><mtable><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(24)</mtext><mtd><mrow><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>(n)=λ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><mtext>(n-1)+H(n-1)H*(n-1)</mtext><mspace linebreak="newline" /><msub><mrow><mtext> =λ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msup><mrow><mtext>(n-1)+|H(n-1)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr><mtr><mtd><mrow><mtable><mlabeledtr><mtext>(25)</mtext><mtd><mrow><msub><mrow><mtext>Θ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>(n)=λ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>Θ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><mtext>(n-1)+H(n-1)H*(n-1) </mtext></mrow></mtd></mlabeledtr></mtable></mrow></mtd></mtr></mtable></mrow></mtd></mtr></mtable></mrow></math><img file="EP0820173A2_D0045.tif" /></maths> In expressions (24) and (25), λ₂ represents a real number and a weighting coefficient of the optimum frequency compensation amount F(n).

0191In this case, the optimum frequency compensation amount F(n) is represented by expression (26) as a value obtained by normalizing a change of H(n) between two adjacent symbols, i.e., θ_f(n) by the amount Φ_f(n) thereof.<maths id="math0046" num="(26)"><math display="block"><mrow><msub><mrow><mtext>F(n+1)=Θ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>(n)/Φ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><mtext>(n)</mtext><mspace linebreak="newline" /><msub><mrow><mtext> ={λ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>Θ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>(n-1)+H(n)H*(n-1)}/λ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msup><mrow><mtext>(n-1)+|H(n-1)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></math><img file="EP0820173A2_D0046.tif" /></maths>

0192In the seventh example, the optimum frequency compensation amount F(n) is estimated based on expression (26).

0193By advancing the time for the optimum phase compensation amount H(n) by one symbol cycle T, expression (27) is obtained.<maths id="math0047" num="(27)"><math display="block"><mrow><msub><mrow><mtext>F(n+1)=Θ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>(n)/Φ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><mtext>(n)</mtext><mspace linebreak="newline" /><msub><mrow><mtext> ={λ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>Θ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msub><mrow><mtext>(n-1)+H(n+1)H*(n)}/λ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><msub><mrow><mtext>Φ</mtext></mrow><mrow><mtext>f</mtext></mrow></msub><msup><mrow><mtext>(n-1)+|H(n)|</mtext></mrow><mrow><mtext>2</mtext></mrow></msup></mrow></math><img file="EP0820173A2_D0047.tif" /></maths>

0194Figure <b>11</b> is a block diagram of an optimum phase estimation circuit <b>8A</b> for estimating the optimum phase compensation amount H(n) based on expression (23), and Figure <b>12</b> is a block diagram of a phase shift estimation circuit <b>9E</b> for estimating the optimum frequency compensation amount F(n) based on expression (26).

0195As shown in Figure <b>11</b>, the optimum phase estimation circuit <b>8A</b> includes an identifier <b>27</b>, a complex multiplier <b>28</b>, a complex adder <b>29</b>, another complex multiplier <b>30</b>, a weighting circuit <b>31</b>, a delay circuit <b>32</b>, a divider <b>33</b>, a complex conjugate circuit <b>34</b>, an absolute value square circuit <b>35</b>, an adder <b>36</b>, another weighting circuit <b>37</b>, another delay circuit <b>38</b>, and still another delay circuit <b>39</b>.

0196In the optimum phase estimation circuit <b>8A</b>, the identifier <b>27</b> receives a determined complex demodulated signal V(n), identifies a symbol closest to the determined complex demodulated signal V(n) among the 64 symbols, and outputs an identification signal D(n) representing the identified symbol. The complex conjugate circuit <b>34</b> receives a tentative complex demodulated signal U(n) and outputs a conjugate complex demodulated signal U*(n). The complex multiplier <b>28</b> performs complex multiplication of the identification signal D(n) and the conjugate complex demodulated signal U*(n) and outputs the resultant value to the complex adder <b>29</b>. The delay circuit <b>32</b> outputs λ₁Θ(n-1) obtained by the previous processing to the complex adder <b>29</b>. The complex adder <b>29</b> performs complex addition of the value from the complex multiplier <b>28</b> and the value from the delay circuit <b>32</b>, and outputs the resultant value to the complex multiplier <b>30</b>. The complex multiplier <b>30</b> performs complex multiplication of the value from the complex adder <b>29</b> and the optimum frequency compensation amount F(n) from the phase shift estimation circuit <b>9E</b>, and outputs the resultant value, i.e., Θ(n) to the weighting circuit <b>31</b> and the divider <b>33</b>. The weighting circuit <b>31</b> performs weighting corresponding to the weighting factor λ₁ with respect to Θ(n), and outputs the resultant value to the delay circuit <b>32</b>. The delay circuit <b>32</b> outputs λ₁Θ(n) to the complex adder <b>29</b> at the next processing.

0197The absolute value square circuit <b>35</b> receives the tentative complex demodulated signal U(n) and the conjugate complex demodulated signal U*(n) from the complex conjugate circuit <b>34</b>, calculates a square of the magnitude of U(n), and outputs the resultant value, i.e., the auto-correlation function to the adder <b>36</b>. The delay circuit <b>38</b> outputs λ₁Φ(n-1) obtained by the previous processing to the adder <b>36</b>. The adder <b>36</b> adds the value from the absolute value square circuit <b>35</b> and the value from the delay circuit <b>36</b>, and outputs the resultant value, i.e., Φ(n) to the weighting circuit <b>37</b> and the divider <b>33</b>. The weighting circuit <b>37</b> performs weighting corresponding to the weighting factor λ₁ with respect to Φ(n), and outputs the resultant value to the delay circuit <b>38</b>. The delay circuit <b>38</b> outputs λ₁Φ(n) to the adder <b>36</b>.

0198The divider <b>33</b> divides the complex scalar Θ(n) by the scalar Φ(n), and outputs the optimum phase compensation amount H(n+1) represented by expression (23) to the delay circuit <b>39</b>. The optimum phase compensation amount H(n+1) is output from the delay circuit <b>39</b> at the next processing, i.e., time (n+1) when the tentative complex demodulated signal U(n+1) is input and the optimum phase compensation amount H(n+2) is estimated.

0199As shown in Figure <b>12</b>, the phase shift estimation circuit <b>9E</b> includes a delay circuit <b>40</b>, a complex conjugate circuit <b>41</b>, a complex multiplier <b>42</b>, a complex adder <b>43</b>, a weighting circuit <b>44</b>, another delay circuit <b>45</b>, a divider <b>46</b>, an absolute value square circuit <b>48</b>, an adder <b>49</b>, another weighting circuit <b>50</b>, another delay circuit <b>51</b>, and still another delay circuit <b>52</b>.

0200In the phase shift estimation circuit <b>9E</b>, the delay circuit <b>40</b> outputs the optimum phase compensation amount H(n-1) received at the previous processing to the complex conjugate circuit <b>41</b>. The complex conjugate circuit <b>41</b> receives the optimum phase compensation amount H(n-1) and outputs an complex optimum phase compensation amount H*(n-1). The complex multiplier <b>42</b> performs complex multiplication of the optimum phase compensation amount H(n) and the complex optimum phase compensation amount H*(n-1), and outputs the auto-correlation value between two adjacent symbols of the optimum phase compensation amount H(n) to the complex adder <b>43</b>. The delay circuit <b>45</b> outputs λ₂Θ_f(n-1) obtained by the previous processing to the complex adder <b>43</b>.

0201The complex adder <b>43</b> performs complex addition of the value from the complex multiplier <b>42</b> and the value from the delay circuit <b>45</b>, and outputs the resultant value, i.e., Θ_f(n) to the weighting circuit <b>44</b> and the divider <b>46</b>. The weighting circuit <b>44</b> performs weighting corresponding to the weighting factor λ₂ with respect to Θ_f(n), and outputs the resultant value to the delay circuit <b>45</b>. The delay circuit <b>45</b> outputs λ₂Θ_f(n) to the complex adder <b>43</b> at the next processing.

0202The absolute value square circuit <b>48</b> receives the optimum phase compensation amount H(n-1) from the delay circuit <b>40</b> and H*(n-1) from the complex conjugate circuit <b>41</b>, calculates a square of the magnitude of H(n-1), and outputs the resultant value, i.e., the auto-correlation function to the adder <b>49</b>. The delay circuit <b>51</b> outputs λ₂Φ_f(n-1) obtained by the previous processing to the adder <b>49</b>. The adder <b>49</b> adds the value from the delay circuit <b>51</b> and the value from the absolute value square circuit <b>48</b>, and outputs the resultant value, i.e., Φ_f(n) to the weighting circuit <b>50</b> and the divider <b>46</b>. The weighting circuit <b>50</b> performs weighting corresponding to the weighting factor λ₂ with respect to Φ_f(n), and outputs the resultant value to the delay circuit <b>45</b>. The delay circuit <b>51</b> outputs λ₂Φ_f(n) to the adder <b>49</b>.

0203The divider <b>46</b> divides the complex scalar Θ_f(n) by the scalar Φ_f(n), and outputs the optimum frequency compensation amount F(n+1) represented by expression (26) to the delay circuit <b>52</b>. The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>52</b> at the next processing, i.e., time (n+1) when the optimum phase compensation amount H(n+1) is input.

0204As described above, in the seventh example, the optimum phase compensation amount H(n+1) and the optimum frequency complex F(n+1) are obtained in accordance with the RLS algorithm, and the optimum frequency compensation amount F(n) is obtained from a change in the optimum phase compensation amount H(n) between two adjacent symbols. Accordingly, demodulation of a signal modulated by the M-ary QAM system does not require circuits which are required in the conventional system, i.e., a circuit for normalizing a complex signal, or an orthogonal coordinate - polar coordinate conversion circuit or a polar coordinate - orthogonal coordinate conversion circuit which is formed of a ROM or the like. Thus, signal processing time is shortened and the size of the entire circuit system is reduced.

(Example 8)

0205A basic principle of a demodulation method and apparatus in an eighth example according to the present invention will be described.

0206In the eighth example, the LMS algorithm is used again. Expression (9) is modified as described below to obtain expression (29). The optimum frequency compensation amount F(n) is obtained by applying expression (29) to the phase shift estimation circuit.

0207First, expression (9) is modified to obtain expression (29).<maths id="math0048" num="(28)"><math display="block"><mrow><msub><mrow><mtext>H(n+1)-F(n)H(n)=µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>[D(n)-H(n)U(n)]U*(n)</mtext></mrow></math><img file="EP0820173A2_D0048.tif" /></maths>

0208By substituting expression (28) to a part of the first term of the left side of expression (20), i.e., [<maths id="math0049"><math display="inline"><mrow><mtext>H(n+1)-F(n)H(n)</mtext></mrow></math><img file="EP0820173A2_D0049.tif" /></maths>], expression (29) is obtained.<maths id="math0050" num="(29)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>[D(n)-H(n)U(n)]U*(n)H*(n)+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0050.tif" /></maths>

0209In the eighth example, the optimum phase compensation amount H(n) is estimated based on expression (9), and the optimum frequency compensation amount F(n) is estimated based on expression (29).

0210Figure <b>13</b> is a block diagram of a phase control circuit <b>10C</b> of the demodulation apparatus in the eighth example. As shown in Figure <b>13</b>, the phase control circuit <b>10C</b> includes a complex multiplier <b>7</b>, an optimum phase estimation circuit <b>80</b>, and a phase shift estimation circuit <b>9F</b>. The complex multiplier <b>7</b> is identical with that in Figure <b>1</b>. The optimum phase estimation circuit <b>80</b> is obtained by adding the phase error detection circuit <b>12A</b> shown in Figure <b>4</b> to the optimum phase estimation circuit <b>8</b> shown in Figures <b>1</b> and <b>2</b>, and thus the configuration and operation thereof are the same as described above.

0211The phase shift estimation circuit <b>9F</b> includes a complex conjugate circuit <b>21F</b>, a complex multiplier <b>22F</b>, a weighting circuit <b>23F</b>, a complex adder <b>24F</b>, and a delay circuit <b>25F</b>. The phase shift estimation circuit <b>9F</b> receives a determined complex demodulated signal V(n) and the complex error signal output from the phase error detection circuit <b>12A</b> instead of the optimum phase compensation amount H(n).

0212The phase shift estimation circuit <b>9F</b> having the above-described configuration operates in the following manner.

0213The complex conjugate circuit <b>21F</b> receives the determined complex demodulated signal V(n) and outputs V*(n) which acts as a complex conjugate with respect to the complex demodulated signal V(n) to the complex multiplier <b>22F</b>.

0214The determined complex demodulated signal V(n) is also output to the phase error detection circuit <b>12A</b> of the optimum phase estimation circuit <b>80</b>. The identifier <b>12A-1</b> identifies a symbol closest to the determined complex demodulated signal V(n) among the 64 symbols and outputs an identification signal D(n) representing the identified symbol. The complex subtractor <b>12A-2</b> performs complex subtraction of the determined complex demodulated signal V(n) from the identification signal D(n) and outputs the resultant value as a complex error signal. The complex error signal represents a scalar indicating the distance between the identification signal D(n) and the complex demodulated signal V(n), and is input to the complex multiplier <b>22F</b> via the switch <b>12A-4</b>.

0215The complex multiplier <b>22F</b> performs complex multiplication of the complex error signal from the phase error detection circuit <b>12A</b> and the complex conjugate demodulated signal V*(n) from the complex conjugate circuit <b>21F</b>, and thus generates and outputs a frequency correction direction signal representing the correction direction of the optimum frequency compensation amount F(n). The frequency correction direction signal corresponds to a part of the first term of the left side, i.e., [D(n)-H(n)U(n)]U*(n)H*(n).

0216The weighting circuit <b>23F</b> performs weighting corresponding to the step parameter µ₁µ₂ (0&lt;µ₁µ₂) with respect to the frequency correction direction signal, and outputs the resultant value to the complex adder <b>24F</b>. The complex adder <b>24F</b> performs complex addition of the value from the weighting circuit <b>23F</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25F</b>, and outputs the optimum frequency compensation amount F(n+1) represented by expression (29) to the delay circuit <b>25F</b>. The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>25F</b> to the optimum phase estimation circuit <b>80</b> at the next processing, and is used to estimate the optimum phase compensation amount H(n+2).

0217Compared with the phase shift estimation circuit <b>9</b> shown in Figure <b>1</b>, the phase shift estimation circuit <b>9F</b> in the eighth example eliminates the delay circuit <b>18</b>, the complex subtractor <b>19</b> and the complex multiplier <b>20</b>. Thus, the circuit configuration is simplified and the size of the entire circuit system is reduced. Moreover, the phase shift estimation circuit <b>9F</b> does not use the output from the complex adder <b>15</b> or the weighting circuit <b>14</b> despite being substantially the same size as that of the phase shift estimation circuits <b>9D-1</b> and <b>9D-2</b> shown in Figures <b>9</b> and <b>10</b>, and estimates the optimum frequency compensation amount F(n) using the complex error signal from the phase error detection circuit <b>12</b> and the determined complex demodulated signal V(n). Accordingly, the signal processing amount required for one symbol can be reduced.

(Example 9)

0218A basic principle of a demodulation method and apparatus in a ninth example according to the present invention will be described.

0219Performing complex multiplication of the phase correction direction signal corresponding to a part of the first term of the left side of expression (9), i.e., [D(n)-H(n)U(n)]U*(n) and the optimum frequency compensation amount F(n) in consideration of the influence of the optimum frequency compensation amount F(n) on the phase correction direction signal results in expression (30).<maths id="math0051" num="(30)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>F(n)[D(n)-H(n)U(n)]U*(n)+F(n)H(n)=H(n+1)</mtext></mrow></math><img file="EP0820173A2_D0051.tif" /></maths>

0220Hereinafter, expression (30) will be considered with reference to Figures <b>1</b>, <b>25A</b>, <b>25B</b>, <b>26A</b> and <b>26B</b>. Figures <b>25A</b>, <b>25B</b>, <b>26A</b> and <b>26B</b> are orthogonal coordinate systems representing the tentative complex demodulated signal U(k), the optimum phase compensation amount H(k), the optimum frequency compensation amount F(k), and the identification signal D(k) at sampling time n (=k). The phase angle of the optimum phase compensation amount H(k) with respect to axis I is <maths id="math0052"><math display="inline"><mrow><mtext>α=∠H(k)</mtext></mrow></math><img file="EP0820173A2_D0052.tif" /></maths>, the phase angle of the optimum frequency compensation amount F(k) with respect to axis I is <maths id="math0053"><math display="inline"><mrow><mtext>γ=∠F(k)</mtext></mrow></math><img file="EP0820173A2_D0053.tif" /></maths>, and the phase angle of the tentative complex demodulated signal U(k) with respect to axis I is <maths id="math0054"><math display="inline"><mrow><mtext>β=∠U(k)</mtext></mrow></math><img file="EP0820173A2_D0054.tif" /></maths>.

0221When a tentative complex demodulated signal U(k) including no noise is input to the phase control circuit <b>10</b>, vector OC representing the tentative complex demodulated signal U(k) rotates counterclockwise by phase angle α of the optimum phase compensation amount H(k) by the complex multiplier <b>7</b> (Figure <b>25A</b>) to be vector OB representing a determined complex demodulated signal <maths id="math0055"><math display="inline"><mrow><mtext>V(k)=H(k)U(k)</mtext></mrow></math><img file="EP0820173A2_D0055.tif" /></maths>. The determined complex demodulated signal V(k) is identified as vector OA of the symbol closest to the determined complex demodulated signal V(k). Vector OA represents the identification signal D(k). At this point, the complex error signal is represented by vector OB and corresponds to a part of the first term of the left side of expression (30), i.e., [D(n)-H(n)U(n)].

0222With reference to Figure <b>25B</b>, [D(n)-H(n)U(n)]U*(n) of the first term of the left side of expression (30) at the same sampling time n (=k) will be considered.

0223Where the magnitude of the tentative complex demodulated signal U(k) including no noise is 1, |U(n)|²=1. Accordingly, [D(n)-H(n)U(n)]U*(n) can be expressed as [D(n)U*(n)-H(n)]. Since <maths id="math0056"><math display="inline"><mrow><mtext>∠U*(k)=-β</mtext></mrow></math><img file="EP0820173A2_D0056.tif" /></maths>, D(k)U*(k) can be represented by vector OD resulting from clockwise rotation of vector OA by angle β. H(k) can be represented by vector OE. Accordingly, [D(k)U*(k)-H(k)] can be represented by vector ED.

0224With reference to Figure <b>26A</b>, the optimum phase compensation amount F(n) based on expression (30) at the same sampling time n (=k) will be described.

0225The second term of the left side of expression (30), i.e., F(k)H(k) (n→k) can be represented by vector OF resulting from counterclockwise rotation of vector OE by angle γ, the vector OE representing H(k).

0226Estimation of the optimum phase compensation amount H(k+1) performed by adding F(k)H(k) and [D(n)-H(n)U(n)]U*(n) in accordance with expression (30) refers to addition of vector P1 to vector OF, vector P1 being in the same direction as vector ED. The direction of vectors P1 and ED is different from the direction of vector P2 (vector which should be added) which is tangent to the unit circumference (indicated by a dotted line). Geometrically, vector P2 is resultant from counterclockwise rotation of vector P1 by angle γ.

0227Accordingly, when the value of γ is excessively large, it is effective to correct the direction of vector P1 toward vector P2. Such a correction of vector P1 corresponds to complex multiplication of F(n) and [D(n)-H(n)U(n)]U*(n) in expression (30).

0228From the above consideration, when the value of γ is excessively large, i.e., the tentative complex demodulated signal U(k) involves an excessively large frequency error, it can be regarded as effective to estimate the optimum phase compensation amount H(n+1) in accordance with expression (30).

0229In the ninth example, demodulation of |U(n)|²=1 is described. The above-described principle can be applied regardless of the modulation system of the signal as long as the average level of the complex demodulated signal U(n) over time is maintained at a certain value.

0230In order to adopt the principle of the ninth example, a weighting operation section <b>14A</b> shown in Figure <b>14A</b> is used in place of the weighting circuit <b>14</b> in the optimum phase estimation circuit shown in Figures <b>1</b> and <b>2</b>. Except for this, it is not necessary to change the configuration of the optimum phase estimation circuit <b>8</b>.

0231The weighting operation section <b>14A</b> includes a complex multiplier <b>14A-1</b> and a weighting circuit <b>14A-2</b>. Compared with the weighting circuit <b>14</b> in Figure <b>1</b>, the complex multiplier <b>14A-1</b> is additionally provided.

0232The weighting operation section <b>14A</b> operates in the following manner.

0233The complex multiplier <b>14A-1</b> receives a phase correction direction signal representing the output from the complex multiplier <b>13</b> of the optimum phase estimation circuit <b>8</b> (Figures <b>1</b> and <b>2</b>), namely, [D(n)-H(n)U(n)]U*(n) and the optimum frequency compensation amount F(n) from the phase shift estimation circuit <b>9</b> (Figure <b>2</b>), performs complex multiplication of these two values, and outputs the resultant value. The resultant value corresponds to a part of the first term of the left side of expression (30), i.e., F(n)[D(n)-H(n)U(n)]U*(n).

0234The weighting circuit <b>14A-2</b> performs weighting corresponding to the step parameter µ₁ (0&lt;µ₁) with respect to the output from the complex multiplier <b>14A-1</b>, and outputs the resultant value to the complex adder <b>15</b> in the optimum phase estimation circuit <b>8</b>. The complex adder <b>15</b> performs complex addition of the output from the weighting circuit <b>14A-2</b> and the output from the complex multiplier <b>17</b> of the optimum phase estimation circuit <b>8</b>, and outputs the optimum phase compensation amount H(n+1) represented by expression (30) to the delay circuit <b>16</b>. The optimum phase compensation amount H(n+1) is output from the delay circuit <b>16</b> at the next processing.

0235In the ninth example, since weighting is performed with respect to the phase correction direction signal based on the optimum frequency compensation amount F(n) as described above, the range in which the frequency is corrected can be enlarged.

(Example 10)

0236A basic principle of a demodulation method and apparatus in a tenth example according to the present invention will be described.

0237Expression (30) is modified to obtain expression (31).<maths id="math0057" num="(31)"><math display="block"><mrow><msub><mrow><mtext>H(n+1)-F(n)H(n)=µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><mtext>F(n)[D(n)-H(n)U(n)]U*(n)</mtext></mrow></math><img file="EP0820173A2_D0057.tif" /></maths>

0238By substituting expression (31) to a part of the first term of the left side of expression (30), i.e., [D(n)-H(n)U(n)], expression (32) is obtained.<maths id="math0058" num="(32)"><math display="block"><mrow><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>1</mtext></mrow></msub><msub><mrow><mtext>µ</mtext></mrow><mrow><mtext>2</mtext></mrow></msub><mtext>F(n)[D(n)-H(n)U(n)]U*(n)H*(n)+F(n)=F(n+1)</mtext></mrow></math><img file="EP0820173A2_D0058.tif" /></maths>

0239With reference to Figure <b>26B</b>, expression (32) will be considered. In Figure <b>26B</b>, vector OG is resultant from clockwise rotation of vector OD (Figure <b>26A</b>) by the phase angle α of H(k). Vector OG corresponds to D(k)U*(k)H*(k).

0240A part of the first term of the left side of expression (32), i.e., [D(n)-H(n)U(n)]U*(n)H*(n) can be developed into D(n)U*(n)H*(n)-|H(n)U(n)|². Where |U(n)|²=1 as described above, the optimum magnitude of the optimum phase compensation amount H(n) is 1. Accordingly, D(n)U*(n)H*(n)-|H(n)U(n)|² equals to D(n)U*(n)H*(n)-1.

0241D(k)U*(k)H*(k)-1 at sampling time n (=k) corresponds to vector JG. F(k) in the second term of the left side of expression (32) at sampling time n (=k) corresponds to vector OH.

0242Estimation of the optimum frequency compensation amount F(n+1) performed by adding F(k) in the second term of the left side of expression (32) and [D(n)-H(n)U(n)]U*(n)H*(n) in the first term of the left side in accordance with expression (32) refers to addition of vector P3 to vector OH, vector P3 being in the same direction as vector JG. The direction of vectors P3 and JG is different from the direction of vector P4 (vector which should be added) which is tangent to the unit circumference (indicated by a dotted line). Geometrically, vector P4 is resultant from counterclockwise rotation of vector P3 by angle γ.

0243Accordingly, when the value of γ is excessively large, it is effective to correct the direction of vector P3 toward vector P4. Such a correction of vector P3 corresponds to complex multiplication of F(n) and [D(n)-H(n)U(n)]U*(n)H* in expression (32).

0244From the above consideration, when the value of γ is excessively large, i.e., the tentative complex demodulated signal U(k) involves an excessively large frequency error, it can be regarded as effective to estimate the optimum frequency compensation amount F(n+1) in accordance with expression (32).

0245In order to adopt the principle of the tenth example, a weighting operation section <b>23G</b> shown in Figure <b>14B</b> is used in place of the weighting circuit <b>23F</b> in the phase shift estimation circuit <b>9F</b> shown in Figure <b>13</b>. Except for this, it is not necessary to change the configuration of the phase shift estimation circuit <b>9F</b>.

0246The weighting section <b>23G</b> includes a complex multiplier <b>23G-1</b> and a weighting circuit <b>23G-2</b>. Compared with the weighting circuit <b>23F</b> in Figure <b>13</b>, the complex multiplier <b>23G-1</b> is additionally provided.

0247The weighting operation section <b>23G</b> operates in the following manner.

0248The complex multiplier <b>23G-1</b> receives a frequency correction direction signal representing the output from the complex multiplier <b>22F</b> of the phase shift estimation circuit <b>9F</b> (Figure <b>13</b>), namely, [D(n)-H(n)U(n)]U*(n)H*(n) and the optimum frequency compensation amount F(n) from the delay circuit <b>25F</b>, performs complex multiplication of these two values, and outputs the resultant value. The resultant value corresponds to a part of the first term of the left side of expression (32), i.e., F(n)[D(n)-H(n)U(n)]U*(n)H*(n).

0249The weighting circuit <b>23G-2</b> performs weighting corresponding to the step parameter µ₁µ₂ (0&lt;µ₁µ₂) with respect to the output from the complex multiplier <b>23G-1</b>, and outputs the resultant value to the complex adder <b>24F</b> (Figure <b>13</b>) in the phase shift estimation circuit <b>9F</b>. The complex adder <b>24F</b> performs complex addition of the output from the weighting circuit <b>23G-2</b> and the optimum frequency compensation amount F(n) from the delay circuit <b>25F</b>, and outputs the optimum frequency compensation amount F(n+1) represented by expression (29) to the delay circuit <b>25F</b>. The optimum frequency compensation amount F(n+1) is output from the delay circuit <b>25F</b> at the next processing.

0250In the tenth example, since weighting is performed with respect to the frequency correction direction signal based on the optimum frequency compensation amount F(n) as described above, the range in which the frequency is corrected can be enlarged.

0251Figure <b>15</b> shows a phase control circuit <b>10D</b> modified from the phase control circuit <b>10D</b>. The phase control circuit <b>10D</b> includes a complex multiplier <b>22G</b> in place of the complex multiplier <b>14A-1</b> of the weighting operation section <b>14A</b> shown in Figure <b>14A</b> or the complex multiplier <b>23G-1</b> of the weighting operation section <b>23G</b> shown in Figure <b>14B</b>. The complex multiplier <b>22G</b>, in cooperation with the complex multiplier <b>13</b>, performs complex multiplication of the input to the weighting circuit <b>14</b> and the optimum frequency compensation amount F(n) in place of the complex multiplier <b>14A-1</b> of the weighting operation section <b>14A</b>. In addition, the complex multiplier <b>22G</b>, in cooperation with the complex multiplier <b>22F</b>, performs complex multiplication of the input to the weighting circuit <b>23F</b> and the optimum frequency compensation amount F(n) in place of the complex multiplier <b>23G-1</b> of the weighting operation section <b>23G</b>.

0252By such a system, both of the functions of the complex multiplier <b>14A-1</b> of the weighting operation section <b>14A</b> (Figure <b>14A</b>) and the complex multiplier <b>23G-1</b> of the weighting operation section <b>23G</b> (Figure <b>14B</b>) are achieved. The range in which the frequency is corrected can be enlarged, and the size of the entire circuit system can be reduced by simplified circuit configuration.

(Example 11)

0253Figure <b>16A</b> is a block diagram of a smoothing circuit <b>53</b> in a phase shift estimation circuit of a demodulation apparatus in an eleventh example according to the present invention.

0254The smoothing circuit <b>53</b> is applied to any of the phase shift estimation circuit <b>9</b> shown in Figure <b>3</b>, the phase shift estimation circuits <b>9A</b>, <b>9B</b>, <b>9C</b>, <b>9D-1</b> and <b>9D-2</b> shown in Figures <b>6</b> through <b>10</b>, and the phase shift estimation circuit <b>9F</b> shown in Figures <b>13</b> and <b>15</b>. In detail, the smoothing circuit <b>53</b> is inserted immediately before the weighting circuit (<b>23</b>, <b>23A</b>, <b>23B</b>, <b>23C</b> or <b>23F</b>). The smoothing circuit <b>53</b> smooths the frequency correction direction signal and outputs the smoothed frequency correction direction signal to the weighting circuit.

0255The smoothing circuit <b>53</b> includes a complex adder <b>53-1</b>, a delay circuit <b>53-2</b>, and a weighting circuit <b>53-3</b>.

0256The smoothing circuit <b>53</b> having such a configuration operates in the following manner. The complex adder <b>53-1</b> receives the frequency correction direction signal from either one of the complex multipliers <b>22</b> and <b>22F</b> and the complex subtractors <b>19A</b>, <b>19B</b> and <b>19C</b> provided therebefore, performs complex addition of the frequency correction direction signal and the output from the delay circuit <b>53-2</b> to smooth the frequency correction direction signal, and outputs the smoothed frequency correction direction signal to either one of the weighting circuits <b>23</b>, <b>23A</b>, <b>23B</b>, <b>23C</b> and <b>23F</b> and the weighting circuit <b>53-3</b>. The weighting circuit <b>23</b> performs weighting corresponding to the step parameter µ₂ or µ₁µ₂ with respect to the frequency correction direction signal, and outputs the resultant value to either one of the complex adders <b>24</b>, <b>24A</b>, <b>24B</b>, <b>24C</b> and <b>24F</b>. Thereafter, the above-described operations are performed.

0257The weighting circuit <b>53-3</b> performs weighting corresponding to the parameter α with respect to the smoothed frequency correction direction signal, and outputs the resultant value to the delay circuit <b>53-2</b>. The delay circuit <b>53-2</b> outputs the resultant value to the complex adder <b>53-1</b> at the next processing.

0258As described above, in the eleventh example, the frequency correction direction signal is smoothed, i.e., components of frequency correction direction signals generated in repetition are cumulatively added by weighting by the parameter α. Accordingly, various types of noise can be restricted. Thus, the optimum frequency compensation amount F(n) can be estimated in a stable state.

0259Figure <b>16B</b> shows a smoothing circuit <b>54</b> modified from the smoothing circuit <b>53</b> shown in Figure <b>16A</b>. The smoothing circuit <b>54</b> includes weighting circuits <b>54-1</b> and <b>54-2</b>, complex adders <b>54-3</b> and <b>54-5</b>, and a delay circuit <b>54-4</b>.

0260The smoothing circuit <b>54</b> having such a configuration operates in the following manner when, for example, used for the phase shift estimation circuit <b>9</b> in Figure <b>3</b>. The weighting circuit <b>54-1</b> receives the frequency correction direction signal from the complex multiplier <b>22</b> provided therebefore, performs weighting corresponding to the parameter β with respect to the frequency correction direction signal, and outputs the resultant value to the complex adder <b>54-5</b>. Hereinafter, the output from the weighting circuit <b>54-1</b> will be referred to as the "direct output".

0261The weighting circuit <b>54-2</b> performs weighting corresponding to the parameter α with respect to the frequency correction direction signal, and outputs the resultant value to the complex adder <b>54-3</b>. The complex adder <b>54-3</b> performs complex addition of the output from the weighting circuit <b>54-2</b> and the output from the delay circuit <b>54-4</b>, and outputs the resultant value to the complex adder <b>54-5</b> and the delay circuit <b>54-4</b>. Hereinafter, the output from the complex adder <b>54-3</b> will be referred to as the "integrated output". The delay circuit <b>54-4</b> outputs the integrated output to the complex adder <b>54-3</b>.

0262The complex adder <b>54-5</b> performs complex addition of the direct output obtained by weighting performed by the weighting circuit <b>54-1</b> and the integrated output obtained by weighting performed by the weighting circuit <b>54-2</b> and integrated by the complex adder <b>54-3</b> and the delay circuit <b>54-4</b>, and outputs the resultant value to the complex adder <b>24</b> provided after the complex adder <b>54-4</b> as a smoothed frequency correction direction signal.

0263By obtaining the direct output and the integrated output from the frequency correction direction signal and smoothing the frequency correction direction signal by complex addition, noise components can be further restricted and thus the optimum frequency compensation amount F(n) can be more estimated in a stable state.

(Example 12)

0264Figure <b>17A</b> is a block diagram of a smoothing circuit <b>55</b> in an optimum phase estimation circuit of a demodulation apparatus in a twelfth example according to the present invention.

0265The smoothing circuit <b>55</b> is applied to the optimum phase estimation circuit <b>8</b> shown in Figure <b>2</b>. In detail, the smoothing circuit <b>55</b> is inserted immediately before the weighting circuit <b>14</b>. The smoothing circuit <b>55</b> smooths the phase correction direction signal and outputs the smoothed phase correction direction signal to the weighting circuit <b>14</b>.

0266The smoothing circuit <b>55</b> includes a complex adder <b>55-1</b>, a delay circuit <b>55-2</b>, a weighting circuit <b>55-3</b>, and a complex multiplier <b>55-4</b>.

0267The smoothing circuit <b>55</b> having such a configuration operates in the following manner. The complex adder <b>55-1</b> receives the phase correction direction signal from the complex multiplier <b>13</b> before the complex adder <b>55-1</b>, performs complex addition of the phase correction direction signal and the output from the delay circuit <b>55-2</b>, and outputs the resultant value to the complex multiplier <b>55-4</b>. The complex multiplier <b>55-4</b> performs complex multiplication of the value from the complex adder <b>55-1</b> and the optimum frequency compensation amount F(n) from the phase shift estimation circuit (e.g., the circuit <b>9</b> in Figure <b>1</b>), rotates the value from the complex adder <b>55-1</b> by ∠F(n), and outputs the resultant value to the weighting circuits <b>14</b> and <b>55-3</b> as a smoothed phase correction direction signal. The weighting circuit <b>14</b> performs weighting corresponding to the step parameter µ₁ with respect to the smoothed phase correction direction signal, and outputs the resultant value to the complex adder <b>15</b>. Thereafter, the above-described operations are performed.

0268The weighting circuit <b>55-3</b> performs weighting corresponding to the parameter α with respect to the smoothed phase correction direction signal, and outputs the resultant value to the delay circuit <b>55-2</b>. The delay circuit <b>55-2</b> outputs the resultant value to the complex adder <b>55-1</b> at the next processing.

0269As described above, in the twelfth example, the phase correction direction signal is smoothed by treating the optimum frequency compensation amount F(n) by complex multiplication, weighting and complex addition in consideration of phase shift. Accordingly, noise components are sufficiently restricted and thus the optimum phase compensation amount H(n) can be estimated in a stable state.

0270Figure <b>17B</b> shows a smoothing circuit <b>56</b> modified from the smoothing circuit <b>55</b> shown in Figure <b>17A</b>. The smoothing circuit <b>56</b> includes weighting circuits <b>56-1</b> and <b>56-2</b>, complex adders <b>56-3</b> and <b>56-5</b>, a delay circuit <b>56-4</b>, and complex multipliers <b>56-6</b> and <b>56-7</b>.

0271The smoothing circuit <b>56</b> having such a configuration operates in the following manner. The weighting circuit <b>56-1</b> performs weighting corresponding to the parameter β with respect to the phase correction direction signal, and outputs the resultant value to the complex multiplier <b>56-6</b>. The complex multiplier <b>56-6</b> performs complex multiplication of the value from the weighting circuit <b>56-1</b> and the optimum frequency compensation amount F(n) from the phase shift estimation circuit (e.g., the circuit <b>9</b> in Figure <b>1</b>), rotates the value from the weighting circuit <b>56-1</b> by ∠F(n), and outputs the resultant value (direct output) to the complex adder <b>56-5</b>.

0272The weighting circuit <b>56-2</b> performs weighting corresponding to the parameter α with respect to the phase correction direction signal, and outputs the resultant value to the complex adder <b>56-3</b>. The complex adder <b>56-3</b> performs complex addition of the value from the complex adder <b>56-3</b> and the output from the delay circuit <b>56-4</b>, and outputs the resultant value to the complex multiplier <b>56-7</b>. The complex multiplier <b>56-7</b> performs complex multiplication of the value from the weighting circuit <b>56-2</b> and the optimum frequency compensation amount F(n) from the phase shift estimation circuit <b>9</b>, and outputs the resultant value (integrated output) to the delay circuit <b>56-4</b> and the complex adder <b>56-5</b>. The outputs delay circuit <b>56-4</b> outputs the integrated output to the complex adder <b>56-3</b> at the next processing.

0273The complex adder <b>56-5</b> performs complex addition of the direct output obtained by weighting performed by the weighting circuit <b>56-1</b> and complex multiplication performed with the optimum frequency compensation amount F(n) by the complex multiplier <b>56-6</b>, and the integrated output obtained by weighting performed by the weighting circuit <b>56-2</b>, integration performed by the complex adder <b>56-3</b> and the delay circuit <b>56-4</b> and complex multiplication performed with the optimum frequency compensation amount F(n) by the complex multiplier <b>56-7</b>. Then, the complex adder <b>56-5</b> outputs the resultant value to the weighting circuit <b>14</b> provided after the complex adder <b>56-5</b> as a smoothed phase correction direction signal.

0274By obtaining the direct output and integrated output from the phase correction direction signal and smoothing the phase correction direction signal by complex addition, noise components can be further restricted and thus the optimum frequency compensation amount F(n) can be more estimated in a stable state.

0275The present invention is not limited to the above-described examples and is applicable to many other modifications. For example, the present application is applicable for demodulating a single modulated by the M-ary PSK (phase shift keying) system, M-ary APSK (amplitude phase shift keying) system, or the M-ary QAM (quadrature amplitude modulation) system.

0276The RLS algorithm provides superior initial convergence characteristics of the optimum frequency compensation in the case where a known training signal is used in lieu of the complex identification signal D. Accordingly, it is effective to use a training signal in lieu of the complex identification signal D.

0277In the seventh example, a constant amplitude level of the demodulated signal can be obtained. Accordingly, in the case where a signal modulated by the PSK system is demodulated in the seventh example, some of the circuits in the phase shift estimation circuit <b>9E</b> shown in Figure <b>12</b> may be eliminated. In more detail, the adder <b>49</b>, the delay circuit <b>51</b>, the weighting circuit <b>50</b>, the absolute value square circuit <b>48</b>, and the divider <b>46</b> may be eliminated. In such a case, the output from the complex adder <b>43</b> is directed input to the delay circuit <b>52</b>. Even with such a configuration, the phase control can be performed properly. Moreover, some of the circuits in the optimum phase estimation circuit <b>8A</b> shown in Figure <b>11</b> may be also eliminated. In more detail, even when the adder <b>36</b>, the delay circuit <b>38</b>, the weighting circuit <b>37</b>, the absolute value square circuit <b>35</b>, and the divider <b>33</b> are eliminated and the output from the complex multiplier <b>30</b> is directly sent to the delay circuit <b>39</b>, proper phase control can be performed. In a configuration in which the phase shift estimation circuit <b>9E</b> and the optimum phase estimation circuit <b>8A</b> share some of the circuits, for example, the delay circuits <b>39</b> and <b>40</b>, the size of the entire circuit system is reduced and the signal processing speed can be raised.

0278In the eighth example, as shown in Figure <b>13</b>, the optimum phase estimation circuit <b>80</b> includes the phase error detection circuit <b>12A</b>. Alternatively, the circuit configuration shown in Figure <b>18</b> may be used, in which the optimum phase estimation circuit <b>8</b> includes the phase error detection circuit <b>12</b> and the phase shift estimation circuit (<b>9F</b>) includes the phase error detection circuit <b>12A</b>. Still alternatively, a configuration in which the optimum phase estimation circuit (<b>8</b>) includes the phase error detection circuit <b>12A</b> and the phase shift estimation circuit (<b>9F</b>) includes the phase error detection circuit <b>12</b> (not shown) may be used. Any of such phase error detection circuits receives a determined complex demodulated signal V(n) and outputs the complex error signal to the demodulated multiplier <b>13</b> or <b>22F</b>.

0279Although not described in any of the examples, it is possible to use the RLS algorithm for the optimum phase estimation circuit and the LMS algorithm for the phase shift estimation circuit, or to use the LMS algorithm for the optimum phase estimation circuit and the RLS algorithm for the phase shift estimation circuit.

0280Although analog quadrature detection is performed in the above examples before processing by the phase control circuit, digital quadrature detection may also be used.

0281According to the present invention, the optimum phase compensation amount for the next processing is obtained based on a tentative complex demodulated signal, a determined complex demodulated signal, and an optimum frequency compensation amount; and the optimum frequency compensation amount for the next processing is obtained based on change in the optimum phase compensation amount during a predetermined cycle. Due to such a system, a demodulation circuit can be realized with a satisfactorily simple configuration. Since the optimum frequency compensation amount is obtained from the optimum phase compensation amount having a relatively small amplitude change, the size of the entire circuit is reduced. Furthermore, when the LMS algorithm is used, even under the existence of a frequency error, the pull-in time of the optimum frequency compensation amount is shortened by controlling the complex error signal representing the difference between the determined complex demodulated signal and the identification signal.

0282By performing weighting in consideration of the optimum frequency compensation amount, the range in which the frequency can be corrected can be enlarged. By providing a smoothing circuit for smoothing the frequency correction direction signal in the phase shift estimation circuit, estimation operation can be stabilized. By providing a smoothing circuit for smoothing the phase correction direction signal based on the optimum frequency compensation amount in the optimum phase estimation circuit, estimation operation can be stabilized.

0283Demodulation of a signal modulated by the M-ary QAM using the RLS algorithm eliminates the necessity of a circuit for normalizing a complex demodulated signal, an orthogonal coordinate - polar coordinate conversion circuit or a polar coordinate - orthogonal coordinate conversion circuit which is formed of a ROM or the like. Thus, the signal processing time is shortened and the size of the entire circuit can be reduced.

0284Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.